aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorPete Popov <ppopov@embeddedalley.com>2005-04-21 01:31:59 -0400
committerRalf Baechle <ralf@linux-mips.org>2005-10-29 14:31:10 -0400
commit7de8d2328767cf4cb463dd3ca70c44985ac835a8 (patch)
tree83ab0fde188432875e00cd230e9ca417432b2de4
parent9447cbfc7a95225e9214ccc225c063b305038a34 (diff)
* use 'unsigned long' as address supplied to au_write[bwl]()
* remove two already unused and commented structures * added an ULL suffix to several address constants that use bits 35-32 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h127
1 files changed, 32 insertions, 95 deletions
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index a662b246bdcf..cd6719cf5ede 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -60,34 +60,34 @@ void static inline au_sync_delay(int ms)
60 mdelay(ms); 60 mdelay(ms);
61} 61}
62 62
63void static inline au_writeb(u8 val, int reg) 63void static inline au_writeb(u8 val, unsigned long reg)
64{ 64{
65 *(volatile u8 *)(reg) = val; 65 *(volatile u8 *)(reg) = val;
66} 66}
67 67
68void static inline au_writew(u16 val, int reg) 68void static inline au_writew(u16 val, unsigned long reg)
69{ 69{
70 *(volatile u16 *)(reg) = val; 70 *(volatile u16 *)(reg) = val;
71} 71}
72 72
73void static inline au_writel(u32 val, int reg) 73void static inline au_writel(u32 val, unsigned long reg)
74{ 74{
75 *(volatile u32 *)(reg) = val; 75 *(volatile u32 *)(reg) = val;
76} 76}
77 77
78static inline u8 au_readb(unsigned long port) 78static inline u8 au_readb(unsigned long reg)
79{ 79{
80 return (*(volatile u8 *)port); 80 return (*(volatile u8 *)reg);
81} 81}
82 82
83static inline u16 au_readw(unsigned long port) 83static inline u16 au_readw(unsigned long reg)
84{ 84{
85 return (*(volatile u16 *)port); 85 return (*(volatile u16 *)reg);
86} 86}
87 87
88static inline u32 au_readl(unsigned long port) 88static inline u32 au_readl(unsigned long reg)
89{ 89{
90 return (*(volatile u32 *)port); 90 return (*(volatile u32 *)reg);
91} 91}
92 92
93/* These next three functions should be a generic part of the MIPS 93/* These next three functions should be a generic part of the MIPS
@@ -181,26 +181,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
181#define MEM_SDSLEEP (0x0030) 181#define MEM_SDSLEEP (0x0030)
182#define MEM_SDSMCKE (0x0034) 182#define MEM_SDSMCKE (0x0034)
183 183
184#ifndef ASSEMBLER
185/*typedef volatile struct
186{
187 uint32 sdmode0;
188 uint32 sdmode1;
189 uint32 sdmode2;
190 uint32 sdaddr0;
191 uint32 sdaddr1;
192 uint32 sdaddr2;
193 uint32 sdrefcfg;
194 uint32 sdautoref;
195 uint32 sdwrmd0;
196 uint32 sdwrmd1;
197 uint32 sdwrmd2;
198 uint32 sdsleep;
199 uint32 sdsmcke;
200
201} AU1X00_SDRAM;*/
202#endif
203
204/* 184/*
205 * MEM_SDMODE register content definitions 185 * MEM_SDMODE register content definitions
206 */ 186 */
@@ -286,49 +266,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
286#define MEM_SDSREF (0x08D0) 266#define MEM_SDSREF (0x08D0)
287#define MEM_SDSLEEP MEM_SDSREF 267#define MEM_SDSLEEP MEM_SDSREF
288 268
289#ifndef ASSEMBLER
290/*typedef volatile struct
291{
292 uint32 sdmode0;
293 uint32 reserved0;
294 uint32 sdmode1;
295 uint32 reserved1;
296 uint32 sdmode2;
297 uint32 reserved2[3];
298 uint32 sdaddr0;
299 uint32 reserved3;
300 uint32 sdaddr1;
301 uint32 reserved4;
302 uint32 sdaddr2;
303 uint32 reserved5[3];
304 uint32 sdconfiga;
305 uint32 reserved6;
306 uint32 sdconfigb;
307 uint32 reserved7;
308 uint32 sdstat;
309 uint32 reserved8;
310 uint32 sderraddr;
311 uint32 reserved9;
312 uint32 sdstride0;
313 uint32 reserved10;
314 uint32 sdstride1;
315 uint32 reserved11;
316 uint32 sdstride2;
317 uint32 reserved12[3];
318 uint32 sdwrmd0;
319 uint32 reserved13;
320 uint32 sdwrmd1;
321 uint32 reserved14;
322 uint32 sdwrmd2;
323 uint32 reserved15[11];
324 uint32 sdprecmd;
325 uint32 reserved16;
326 uint32 sdautoref;
327 uint32 reserved17;
328 uint32 sdsref;
329
330} AU1550_SDRAM;*/
331#endif
332#endif 269#endif
333 270
334/* 271/*
@@ -365,9 +302,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
365#define SSI0_PHYS_ADDR 0x11600000 302#define SSI0_PHYS_ADDR 0x11600000
366#define SSI1_PHYS_ADDR 0x11680000 303#define SSI1_PHYS_ADDR 0x11680000
367#define SYS_PHYS_ADDR 0x11900000 304#define SYS_PHYS_ADDR 0x11900000
368#define PCMCIA_IO_PHYS_ADDR 0xF00000000 305#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
369#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 306#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
370#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 307#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
371#endif 308#endif
372 309
373/********************************************************************/ 310/********************************************************************/
@@ -399,13 +336,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
399#define UART3_PHYS_ADDR 0x11400000 336#define UART3_PHYS_ADDR 0x11400000
400#define GPIO2_PHYS_ADDR 0x11700000 337#define GPIO2_PHYS_ADDR 0x11700000
401#define SYS_PHYS_ADDR 0x11900000 338#define SYS_PHYS_ADDR 0x11900000
402#define PCI_MEM_PHYS_ADDR 0x400000000 339#define PCI_MEM_PHYS_ADDR 0x400000000ULL
403#define PCI_IO_PHYS_ADDR 0x500000000 340#define PCI_IO_PHYS_ADDR 0x500000000ULL
404#define PCI_CONFIG0_PHYS_ADDR 0x600000000 341#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
405#define PCI_CONFIG1_PHYS_ADDR 0x680000000 342#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
406#define PCMCIA_IO_PHYS_ADDR 0xF00000000 343#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
407#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 344#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
408#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 345#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
409#endif 346#endif
410 347
411/********************************************************************/ 348/********************************************************************/
@@ -442,9 +379,9 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
442#define GPIO2_PHYS_ADDR 0x11700000 379#define GPIO2_PHYS_ADDR 0x11700000
443#define SYS_PHYS_ADDR 0x11900000 380#define SYS_PHYS_ADDR 0x11900000
444#define LCD_PHYS_ADDR 0x15000000 381#define LCD_PHYS_ADDR 0x15000000
445#define PCMCIA_IO_PHYS_ADDR 0xF00000000 382#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
446#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 383#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
447#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 384#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
448#endif 385#endif
449 386
450/***********************************************************************/ 387/***********************************************************************/
@@ -473,13 +410,13 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
473#define PSC1_PHYS_ADDR 0x11B00000 410#define PSC1_PHYS_ADDR 0x11B00000
474#define PSC2_PHYS_ADDR 0x10A00000 411#define PSC2_PHYS_ADDR 0x10A00000
475#define PSC3_PHYS_ADDR 0x10B00000 412#define PSC3_PHYS_ADDR 0x10B00000
476#define PCI_MEM_PHYS_ADDR 0x400000000 413#define PCI_MEM_PHYS_ADDR 0x400000000ULL
477#define PCI_IO_PHYS_ADDR 0x500000000 414#define PCI_IO_PHYS_ADDR 0x500000000ULL
478#define PCI_CONFIG0_PHYS_ADDR 0x600000000 415#define PCI_CONFIG0_PHYS_ADDR 0x600000000ULL
479#define PCI_CONFIG1_PHYS_ADDR 0x680000000 416#define PCI_CONFIG1_PHYS_ADDR 0x680000000ULL
480#define PCMCIA_IO_PHYS_ADDR 0xF00000000 417#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
481#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000 418#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
482#define PCMCIA_MEM_PHYS_ADDR 0xF80000000 419#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
483#endif 420#endif
484 421
485/***********************************************************************/ 422/***********************************************************************/
@@ -500,15 +437,15 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
500#define DDMA_PHYS_ADDR 0x14002000 437#define DDMA_PHYS_ADDR 0x14002000
501#define PSC0_PHYS_ADDR 0x11A00000 438#define PSC0_PHYS_ADDR 0x11A00000
502#define PSC1_PHYS_ADDR 0x11B00000 439#define PSC1_PHYS_ADDR 0x11B00000
503#define PCMCIA_IO_PHYS_ADDR 0xF00000000
504#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
505#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
506#define SD0_PHYS_ADDR 0x10600000 440#define SD0_PHYS_ADDR 0x10600000
507#define SD1_PHYS_ADDR 0x10680000 441#define SD1_PHYS_ADDR 0x10680000
508#define LCD_PHYS_ADDR 0x15000000 442#define LCD_PHYS_ADDR 0x15000000
509#define SWCNT_PHYS_ADDR 0x1110010C 443#define SWCNT_PHYS_ADDR 0x1110010C
510#define MAEFE_PHYS_ADDR 0x14012000 444#define MAEFE_PHYS_ADDR 0x14012000
511#define MAEBE_PHYS_ADDR 0x14010000 445#define MAEBE_PHYS_ADDR 0x14010000
446#define PCMCIA_IO_PHYS_ADDR 0xF00000000ULL
447#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000ULL
448#define PCMCIA_MEM_PHYS_ADDR 0xF80000000ULL
512#endif 449#endif
513 450
514 451
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-14 22:16:39 -0500