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authorRalf Baechle <ralf@linux-mips.org>2006-07-09 21:27:21 -0400
committerRalf Baechle <ralf@linux-mips.org>2006-07-13 16:26:18 -0400
commit75da124ac0141e463cb2738fdc02dd24fc8b6e95 (patch)
tree07dc0b9209462f7f1362dbf2ee30133d462570c7
parentd1d60ded2b6cca40e2f14ea2771cbe815c11abb5 (diff)
[MIPS] Remove unused code.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/mips-boards/sim/Makefile3
-rw-r--r--arch/mips/mips-boards/sim/sim_IRQ.c147
-rw-r--r--arch/mips/mips-boards/sim/sim_irq.S100
3 files changed, 1 insertions, 249 deletions
diff --git a/arch/mips/mips-boards/sim/Makefile b/arch/mips/mips-boards/sim/Makefile
index 5b977de4ecff..a12e32aafde0 100644
--- a/arch/mips/mips-boards/sim/Makefile
+++ b/arch/mips/mips-boards/sim/Makefile
@@ -15,6 +15,5 @@
15# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. 15# 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16# 16#
17 17
18obj-y := sim_setup.o sim_mem.o sim_time.o sim_printf.o sim_int.o sim_irq.o \ 18obj-y := sim_setup.o sim_mem.o sim_time.o sim_printf.o sim_int.o sim_cmdline.o
19 sim_cmdline.o
20obj-$(CONFIG_SMP) += sim_smp.o 19obj-$(CONFIG_SMP) += sim_smp.o
diff --git a/arch/mips/mips-boards/sim/sim_IRQ.c b/arch/mips/mips-boards/sim/sim_IRQ.c
deleted file mode 100644
index ec549f3e2011..000000000000
--- a/arch/mips/mips-boards/sim/sim_IRQ.c
+++ /dev/null
@@ -1,147 +0,0 @@
1/*
2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 1999, 2000 MIPS Technologies, Inc. All rights reserved.
4 *
5 * This program is free software; you can distribute it and/or modify it
6 * under the terms of the GNU General Public License (Version 2) as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * for more details.
13 *
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
17 *
18 * Interrupt exception dispatch code.
19 */
20
21#include <asm/asm.h>
22#include <asm/mipsregs.h>
23#include <asm/regdef.h>
24#include <asm/stackframe.h>
25
26/* A lot of complication here is taken away because:
27 *
28 * 1) We handle one interrupt and return, sitting in a loop and moving across
29 * all the pending IRQ bits in the cause register is _NOT_ the answer, the
30 * common case is one pending IRQ so optimize in that direction.
31 *
32 * 2) We need not check against bits in the status register IRQ mask, that
33 * would make this routine slow as hell.
34 *
35 * 3) Linux only thinks in terms of all IRQs on or all IRQs off, nothing in
36 * between like BSD spl() brain-damage.
37 *
38 * Furthermore, the IRQs on the MIPS board look basically (barring software
39 * IRQs which we don't use at all and all external interrupt sources are
40 * combined together on hardware interrupt 0 (MIPS IRQ 2)) like:
41 *
42 * MIPS IRQ Source
43 * -------- ------
44 * 0 Software (ignored)
45 * 1 Software (ignored)
46 * 2 Combined hardware interrupt (hw0)
47 * 3 Hardware (ignored)
48 * 4 Hardware (ignored)
49 * 5 Hardware (ignored)
50 * 6 Hardware (ignored)
51 * 7 R4k timer (what we use)
52 *
53 * Note: On the SEAD board thing are a little bit different.
54 * Here IRQ 2 (hw0) is wired to the UART0 and IRQ 3 (hw1) is wired
55 * wired to UART1.
56 *
57 * We handle the IRQ according to _our_ priority which is:
58 *
59 * Highest ---- R4k Timer
60 * Lowest ---- Combined hardware interrupt
61 *
62 * then we just return, if multiple IRQs are pending then we will just take
63 * another exception, big deal.
64 */
65
66 .text
67 .set noreorder
68 .set noat
69 .align 5
70 NESTED(mipsIRQ, PT_SIZE, sp)
71 SAVE_ALL
72 CLI
73 .set at
74
75 mfc0 s0, CP0_CAUSE # get irq bits
76 mfc0 s1, CP0_STATUS # get irq mask
77 and s0, s1
78
79 /* First we check for r4k counter/timer IRQ. */
80 andi a0, s0, CAUSEF_IP7
81 beq a0, zero, 1f
82 andi a0, s0, CAUSEF_IP2 # delay slot, check hw0 interrupt
83
84 /* Wheee, a timer interrupt. */
85 move a0, sp
86 jal mips_timer_interrupt
87 nop
88
89 j ret_from_irq
90 nop
91
921:
93#if defined(CONFIG_MIPS_SEAD)
94 beq a0, zero, 1f
95 andi a0, s0, CAUSEF_IP3 # delay slot, check hw1 interrupt
96#else
97 beq a0, zero, 1f # delay slot, check hw3 interrupt
98 andi a0, s0, CAUSEF_IP5
99#endif
100
101 /* Wheee, combined hardware level zero interrupt. */
102#if defined(CONFIG_MIPS_ATLAS)
103 jal atlas_hw0_irqdispatch
104#elif defined(CONFIG_MIPS_MALTA)
105 jal malta_hw0_irqdispatch
106#elif defined(CONFIG_MIPS_SEAD)
107 jal sead_hw0_irqdispatch
108#else
109#error "MIPS board not supported\n"
110#endif
111 move a0, sp # delay slot
112
113 j ret_from_irq
114 nop # delay slot
115
1161:
117#if defined(CONFIG_MIPS_SEAD)
118 beq a0, zero, 1f
119 andi a0, s0, CAUSEF_IP5 # delay slot, check hw3 interrupt
120 jal sead_hw1_irqdispatch
121 move a0, sp # delay slot
122 j ret_from_irq
123 nop # delay slot
1241:
125#endif
126#if defined(CONFIG_MIPS_MALTA)
127 beq a0, zero, 1f # check hw3 (coreHI) interrupt
128 nop
129 jal corehi_irqdispatch
130 move a0, sp
131 j ret_from_irq
132 nop
1331:
134#endif
135 /*
136 * Here by mistake? This is possible, what can happen is that by the
137 * time we take the exception the IRQ pin goes low, so just leave if
138 * this is the case.
139 */
140 move a1,s0
141 PRINT("Got interrupt: c0_cause = %08x\n")
142 mfc0 a1, CP0_EPC
143 PRINT("c0_epc = %08x\n")
144
145 j ret_from_irq
146 nop
147 END(mipsIRQ)
diff --git a/arch/mips/mips-boards/sim/sim_irq.S b/arch/mips/mips-boards/sim/sim_irq.S
deleted file mode 100644
index b7444e74a6a1..000000000000
--- a/arch/mips/mips-boards/sim/sim_irq.S
+++ /dev/null
@@ -1,100 +0,0 @@
1/*
2 * Copyright (C) 1999, 2005 MIPS Technologies, Inc. All rights reserved.
3 *
4 * This program is free software; you can distribute it and/or modify it
5 * under the terms of the GNU General Public License (Version 2) as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
11 * for more details.
12 *
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
16 *
17 * Interrupt exception dispatch code.
18 *
19 */
20
21#include <asm/asm.h>
22#include <asm/mipsregs.h>
23#include <asm/regdef.h>
24#include <asm/stackframe.h>
25
26#include <asm/mips-boards/simint.h>
27
28
29 .text
30 .set noreorder
31 .set noat
32 .align 5
33 NESTED(simIRQ, PT_SIZE, sp)
34 SAVE_ALL
35 CLI
36 .set at
37
38 mfc0 s0, CP0_CAUSE # get irq bits
39 mfc0 s1, CP0_STATUS # get irq mask
40 andi s0, ST0_IM # CAUSE.CE may be non-zero!
41 and s0, s1
42
43#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
44 .set mips32
45 clz a0, s0
46 .set mips0
47 negu a0
48 addu a0, 31-CAUSEB_IP
49 bltz a0, spurious
50#else
51 beqz s0, spurious
52 li a0, 7
53
54 and t0, s0, 0xf000
55 sltiu t0, t0, 1
56 sll t0, 2
57 subu a0, t0
58 sll s0, t0
59
60 and t0, s0, 0xc000
61 sltiu t0, t0, 1
62 sll t0, 1
63 subu a0, t0
64 sll s0, t0
65
66 and t0, s0, 0x8000
67 sltiu t0, t0, 1
68 # sll t0, 0
69 subu a0, t0
70 # sll s0, t0
71#endif
72
73#ifdef CASCADE_IRQ
74 li a1, CASCADE_IRQ
75 bne a0, a1, 1f
76 addu a0, MIPSCPU_INT_BASE
77
78 jal CASCADE_DISPATCH
79 move a0, sp
80
81 j ret_from_irq
82 nop
831:
84#else
85 addu a0, MIPSCPU_INT_BASE
86#endif
87
88 jal do_IRQ
89 move a1, sp
90
91 j ret_from_irq
92 nop
93
94
95spurious:
96 jal spurious_interrupt
97 nop
98 j ret_from_irq
99 nop
100 END(simIRQ)
generated by cgit v1.2.2 (git 2.25.0) at 2024-10-11 06:30:10 -0400