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authorJohannes Stezenbach <js@linuxtv.org>2005-09-09 16:02:34 -0400
committerLinus Torvalds <torvalds@g5.osdl.org>2005-09-09 16:57:38 -0400
commit6816a4c183e62bca1fa4812214e483ab503dcb7d (patch)
tree095a710b11cef31c2ef253a1e203a4c227bd063d
parentc2026b3af0c8ad33ef253a950c271f2d0da111b6 (diff)
[PATCH] dvb: frontend: ves1820: improve tuning
Reset acgconf register after tuning to improve locking, as suggested by Marco Schluessler. Minor cleanups in ves1820_init(). Signed-off-by: Johannes Stezenbach <js@linuxtv.org> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--drivers/media/dvb/frontends/ves1820.c15
1 files changed, 7 insertions, 8 deletions
diff --git a/drivers/media/dvb/frontends/ves1820.c b/drivers/media/dvb/frontends/ves1820.c
index 70fb44b391a7..c6d276618e86 100644
--- a/drivers/media/dvb/frontends/ves1820.c
+++ b/drivers/media/dvb/frontends/ves1820.c
@@ -194,19 +194,18 @@ static int ves1820_init(struct dvb_frontend* fe)
194{ 194{
195 struct ves1820_state* state = fe->demodulator_priv; 195 struct ves1820_state* state = fe->demodulator_priv;
196 int i; 196 int i;
197 int val;
198 197
199 ves1820_writereg(state, 0, 0); 198 ves1820_writereg(state, 0, 0);
200 199
201 for (i = 0; i < 53; i++) { 200 for (i = 0; i < sizeof(ves1820_inittab); i++)
202 val = ves1820_inittab[i]; 201 ves1820_writereg(state, i, ves1820_inittab[i]);
203 if ((i == 2) && (state->config->selagc)) val |= 0x08; 202 if (state->config->selagc)
204 ves1820_writereg(state, i, val); 203 ves1820_writereg(state, 2, ves1820_inittab[2] | 0x08);
205 }
206 204
207 ves1820_writereg(state, 0x34, state->pwm); 205 ves1820_writereg(state, 0x34, state->pwm);
208 206
209 if (state->config->pll_init) state->config->pll_init(fe); 207 if (state->config->pll_init)
208 state->config->pll_init(fe);
210 209
211 return 0; 210 return 0;
212} 211}
@@ -234,7 +233,7 @@ static int ves1820_set_parameters(struct dvb_frontend* fe, struct dvb_frontend_p
234 ves1820_writereg(state, 0x09, reg0x09[real_qam]); 233 ves1820_writereg(state, 0x09, reg0x09[real_qam]);
235 234
236 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion); 235 ves1820_setup_reg0(state, reg0x00[real_qam], p->inversion);
237 236 ves1820_writereg(state, 2, ves1820_inittab[2] | (state->config->selagc ? 0x08 : 0));
238 return 0; 237 return 0;
239} 238}
240 239