diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-28 19:33:12 -0500 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-01-28 19:33:12 -0500 |
| commit | 3d29935ff0773fe466e957f17284ca777a2aaa89 (patch) | |
| tree | dcbadff76bb481124fe996e4103c138f1810e984 | |
| parent | 474118d06d1d5053f27450224f0541219483ec69 (diff) | |
| parent | e8e06eae4ffd683931b928f460c11c40cd3f7fd8 (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6:
x86/PCI: remove IOH range fetching
PCI: fix nested spinlock hang in aer_inject
| -rw-r--r-- | arch/x86/pci/Makefile | 2 | ||||
| -rw-r--r-- | arch/x86/pci/intel_bus.c | 94 | ||||
| -rw-r--r-- | drivers/pci/pcie/aer/aer_inject.c | 12 |
3 files changed, 7 insertions, 101 deletions
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile index 564b008a51c7..39fba37f702f 100644 --- a/arch/x86/pci/Makefile +++ b/arch/x86/pci/Makefile | |||
| @@ -15,7 +15,7 @@ obj-$(CONFIG_X86_NUMAQ) += numaq_32.o | |||
| 15 | 15 | ||
| 16 | obj-y += common.o early.o | 16 | obj-y += common.o early.o |
| 17 | obj-y += amd_bus.o | 17 | obj-y += amd_bus.o |
| 18 | obj-$(CONFIG_X86_64) += bus_numa.o intel_bus.o | 18 | obj-$(CONFIG_X86_64) += bus_numa.o |
| 19 | 19 | ||
| 20 | ifeq ($(CONFIG_PCI_DEBUG),y) | 20 | ifeq ($(CONFIG_PCI_DEBUG),y) |
| 21 | EXTRA_CFLAGS += -DDEBUG | 21 | EXTRA_CFLAGS += -DDEBUG |
diff --git a/arch/x86/pci/intel_bus.c b/arch/x86/pci/intel_bus.c deleted file mode 100644 index f81a2fa8fe25..000000000000 --- a/arch/x86/pci/intel_bus.c +++ /dev/null | |||
| @@ -1,94 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * to read io range from IOH pci conf, need to do it after mmconfig is there | ||
| 3 | */ | ||
| 4 | |||
| 5 | #include <linux/delay.h> | ||
| 6 | #include <linux/dmi.h> | ||
| 7 | #include <linux/pci.h> | ||
| 8 | #include <linux/init.h> | ||
| 9 | #include <asm/pci_x86.h> | ||
| 10 | |||
| 11 | #include "bus_numa.h" | ||
| 12 | |||
| 13 | static inline void print_ioh_resources(struct pci_root_info *info) | ||
| 14 | { | ||
| 15 | int res_num; | ||
| 16 | int busnum; | ||
| 17 | int i; | ||
| 18 | |||
| 19 | printk(KERN_DEBUG "IOH bus: [%02x, %02x]\n", | ||
| 20 | info->bus_min, info->bus_max); | ||
| 21 | res_num = info->res_num; | ||
| 22 | busnum = info->bus_min; | ||
| 23 | for (i = 0; i < res_num; i++) { | ||
| 24 | struct resource *res; | ||
| 25 | |||
| 26 | res = &info->res[i]; | ||
| 27 | printk(KERN_DEBUG "IOH bus: %02x index %x %s: [%llx, %llx]\n", | ||
| 28 | busnum, i, | ||
| 29 | (res->flags & IORESOURCE_IO) ? "io port" : | ||
| 30 | "mmio", | ||
| 31 | res->start, res->end); | ||
| 32 | } | ||
| 33 | } | ||
| 34 | |||
| 35 | #define IOH_LIO 0x108 | ||
| 36 | #define IOH_LMMIOL 0x10c | ||
| 37 | #define IOH_LMMIOH 0x110 | ||
| 38 | #define IOH_LMMIOH_BASEU 0x114 | ||
| 39 | #define IOH_LMMIOH_LIMITU 0x118 | ||
| 40 | #define IOH_LCFGBUS 0x11c | ||
| 41 | |||
| 42 | static void __devinit pci_root_bus_res(struct pci_dev *dev) | ||
| 43 | { | ||
| 44 | u16 word; | ||
| 45 | u32 dword; | ||
| 46 | struct pci_root_info *info; | ||
| 47 | u16 io_base, io_end; | ||
| 48 | u32 mmiol_base, mmiol_end; | ||
| 49 | u64 mmioh_base, mmioh_end; | ||
| 50 | int bus_base, bus_end; | ||
| 51 | |||
| 52 | /* some sys doesn't get mmconf enabled */ | ||
| 53 | if (dev->cfg_size < 0x120) | ||
| 54 | return; | ||
| 55 | |||
| 56 | if (pci_root_num >= PCI_ROOT_NR) { | ||
| 57 | printk(KERN_DEBUG "intel_bus.c: PCI_ROOT_NR is too small\n"); | ||
| 58 | return; | ||
| 59 | } | ||
| 60 | |||
| 61 | info = &pci_root_info[pci_root_num]; | ||
| 62 | pci_root_num++; | ||
| 63 | |||
| 64 | pci_read_config_word(dev, IOH_LCFGBUS, &word); | ||
| 65 | bus_base = (word & 0xff); | ||
| 66 | bus_end = (word & 0xff00) >> 8; | ||
| 67 | sprintf(info->name, "PCI Bus #%02x", bus_base); | ||
| 68 | info->bus_min = bus_base; | ||
| 69 | info->bus_max = bus_end; | ||
| 70 | |||
| 71 | pci_read_config_word(dev, IOH_LIO, &word); | ||
| 72 | io_base = (word & 0xf0) << (12 - 4); | ||
| 73 | io_end = (word & 0xf000) | 0xfff; | ||
| 74 | update_res(info, io_base, io_end, IORESOURCE_IO, 0); | ||
| 75 | |||
| 76 | pci_read_config_dword(dev, IOH_LMMIOL, &dword); | ||
| 77 | mmiol_base = (dword & 0xff00) << (24 - 8); | ||
| 78 | mmiol_end = (dword & 0xff000000) | 0xffffff; | ||
| 79 | update_res(info, mmiol_base, mmiol_end, IORESOURCE_MEM, 0); | ||
| 80 | |||
| 81 | pci_read_config_dword(dev, IOH_LMMIOH, &dword); | ||
| 82 | mmioh_base = ((u64)(dword & 0xfc00)) << (26 - 10); | ||
| 83 | mmioh_end = ((u64)(dword & 0xfc000000) | 0x3ffffff); | ||
| 84 | pci_read_config_dword(dev, IOH_LMMIOH_BASEU, &dword); | ||
| 85 | mmioh_base |= ((u64)(dword & 0x7ffff)) << 32; | ||
| 86 | pci_read_config_dword(dev, IOH_LMMIOH_LIMITU, &dword); | ||
| 87 | mmioh_end |= ((u64)(dword & 0x7ffff)) << 32; | ||
| 88 | update_res(info, mmioh_base, mmioh_end, IORESOURCE_MEM, 0); | ||
| 89 | |||
| 90 | print_ioh_resources(info); | ||
| 91 | } | ||
| 92 | |||
| 93 | /* intel IOH */ | ||
| 94 | DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, pci_root_bus_res); | ||
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c index 8c30a9544d61..223052b73563 100644 --- a/drivers/pci/pcie/aer/aer_inject.c +++ b/drivers/pci/pcie/aer/aer_inject.c | |||
| @@ -321,7 +321,7 @@ static int aer_inject(struct aer_error_inj *einj) | |||
| 321 | unsigned long flags; | 321 | unsigned long flags; |
| 322 | unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn); | 322 | unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn); |
| 323 | int pos_cap_err, rp_pos_cap_err; | 323 | int pos_cap_err, rp_pos_cap_err; |
| 324 | u32 sever, mask; | 324 | u32 sever, cor_mask, uncor_mask; |
| 325 | int ret = 0; | 325 | int ret = 0; |
| 326 | 326 | ||
| 327 | dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn); | 327 | dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn); |
| @@ -339,6 +339,9 @@ static int aer_inject(struct aer_error_inj *einj) | |||
| 339 | goto out_put; | 339 | goto out_put; |
| 340 | } | 340 | } |
| 341 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever); | 341 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_SEVER, &sever); |
| 342 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &cor_mask); | ||
| 343 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK, | ||
| 344 | &uncor_mask); | ||
| 342 | 345 | ||
| 343 | rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR); | 346 | rp_pos_cap_err = pci_find_ext_capability(rpdev, PCI_EXT_CAP_ID_ERR); |
| 344 | if (!rp_pos_cap_err) { | 347 | if (!rp_pos_cap_err) { |
| @@ -374,17 +377,14 @@ static int aer_inject(struct aer_error_inj *einj) | |||
| 374 | err->header_log2 = einj->header_log2; | 377 | err->header_log2 = einj->header_log2; |
| 375 | err->header_log3 = einj->header_log3; | 378 | err->header_log3 = einj->header_log3; |
| 376 | 379 | ||
| 377 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_COR_MASK, &mask); | 380 | if (einj->cor_status && !(einj->cor_status & ~cor_mask)) { |
| 378 | if (einj->cor_status && !(einj->cor_status & ~mask)) { | ||
| 379 | ret = -EINVAL; | 381 | ret = -EINVAL; |
| 380 | printk(KERN_WARNING "The correctable error(s) is masked " | 382 | printk(KERN_WARNING "The correctable error(s) is masked " |
| 381 | "by device\n"); | 383 | "by device\n"); |
| 382 | spin_unlock_irqrestore(&inject_lock, flags); | 384 | spin_unlock_irqrestore(&inject_lock, flags); |
| 383 | goto out_put; | 385 | goto out_put; |
| 384 | } | 386 | } |
| 385 | 387 | if (einj->uncor_status && !(einj->uncor_status & ~uncor_mask)) { | |
| 386 | pci_read_config_dword(dev, pos_cap_err + PCI_ERR_UNCOR_MASK, &mask); | ||
| 387 | if (einj->uncor_status && !(einj->uncor_status & ~mask)) { | ||
| 388 | ret = -EINVAL; | 388 | ret = -EINVAL; |
| 389 | printk(KERN_WARNING "The uncorrectable error(s) is masked " | 389 | printk(KERN_WARNING "The uncorrectable error(s) is masked " |
| 390 | "by device\n"); | 390 | "by device\n"); |
