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authorMichael Hennerich <michael.hennerich@analog.com>2008-02-25 01:39:50 -0500
committerBryan Wu <cooloney@kernel.org>2008-02-25 01:39:50 -0500
commit3927819d511f5b5855e6f2345f24e7b04e4fd2f5 (patch)
treee3a25b247fe092400649298891325c7681e9094b
parent9253d02041c60d732713c40c59b49fbde8f3bc1c (diff)
[Blackfin] arch: Fix CONFIG_PM support for BF561
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
-rw-r--r--arch/blackfin/mach-common/dpmc.S6
-rw-r--r--include/asm-blackfin/mach-bf561/blackfin.h3
2 files changed, 4 insertions, 5 deletions
diff --git a/arch/blackfin/mach-common/dpmc.S b/arch/blackfin/mach-common/dpmc.S
index fc9f6eb9018b..9d45aa3265b1 100644
--- a/arch/blackfin/mach-common/dpmc.S
+++ b/arch/blackfin/mach-common/dpmc.S
@@ -31,9 +31,6 @@
31#include <asm/blackfin.h> 31#include <asm/blackfin.h>
32#include <asm/mach/irq.h> 32#include <asm/mach/irq.h>
33 33
34.text
35
36#if !defined(CONFIG_BF561)
37 34
38.section .l1.text 35.section .l1.text
39 36
@@ -328,10 +325,12 @@ ENTRY(_set_sic_iwr)
328 RTS; 325 RTS;
329 326
330ENTRY(_set_rtc_istat) 327ENTRY(_set_rtc_istat)
328#ifndef CONFIG_BF561
331 P0.H = hi(RTC_ISTAT); 329 P0.H = hi(RTC_ISTAT);
332 P0.L = lo(RTC_ISTAT); 330 P0.L = lo(RTC_ISTAT);
333 w[P0] = R0.L; 331 w[P0] = R0.L;
334 SSYNC; 332 SSYNC;
333#endif
335 RTS; 334 RTS;
336 335
337ENTRY(_test_pll_locked) 336ENTRY(_test_pll_locked)
@@ -342,4 +341,3 @@ ENTRY(_test_pll_locked)
342 CC = BITTST(R0,5); 341 CC = BITTST(R0,5);
343 IF !CC JUMP 1b; 342 IF !CC JUMP 1b;
344 RTS; 343 RTS;
345#endif
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
index 362617f93845..3a16df2c86d8 100644
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -49,7 +49,8 @@
49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN() 49#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val) 50#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
51 51
52 52#define SIC_IWR0 SICA_IWR0
53#define SIC_IWR1 SICA_IWR1
53#define SIC_IAR0 SICA_IAR0 54#define SIC_IAR0 SICA_IAR0
54#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0 55#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
55#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1 56#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1