diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:39 -0500 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2010-02-27 06:53:39 -0500 |
| commit | 36946d7387ee6f3a331563a1d839240924b65798 (patch) | |
| tree | 6bfb5e1776ebb2bce424c1600d655de09d495853 | |
| parent | 896508705561bea24656680cdaf3b4095c4d7473 (diff) | |
MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
| -rw-r--r-- | arch/mips/sni/rm200.c | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c index c4778e47efa4..90c558f7c0fa 100644 --- a/arch/mips/sni/rm200.c +++ b/arch/mips/sni/rm200.c | |||
| @@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit); | |||
| 132 | * readb/writeb to access them | 132 | * readb/writeb to access them |
| 133 | */ | 133 | */ |
| 134 | 134 | ||
| 135 | static DEFINE_SPINLOCK(sni_rm200_i8259A_lock); | 135 | static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock); |
| 136 | #define PIC_CMD 0x00 | 136 | #define PIC_CMD 0x00 |
| 137 | #define PIC_IMR 0x01 | 137 | #define PIC_IMR 0x01 |
| 138 | #define PIC_ISR PIC_CMD | 138 | #define PIC_ISR PIC_CMD |
| @@ -161,13 +161,13 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq) | |||
| 161 | 161 | ||
| 162 | irq -= RM200_I8259A_IRQ_BASE; | 162 | irq -= RM200_I8259A_IRQ_BASE; |
| 163 | mask = 1 << irq; | 163 | mask = 1 << irq; |
| 164 | spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); | 164 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
| 165 | rm200_cached_irq_mask |= mask; | 165 | rm200_cached_irq_mask |= mask; |
| 166 | if (irq & 8) | 166 | if (irq & 8) |
| 167 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | 167 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); |
| 168 | else | 168 | else |
| 169 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | 169 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); |
| 170 | spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); | 170 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
| 171 | } | 171 | } |
| 172 | 172 | ||
| 173 | static void sni_rm200_enable_8259A_irq(unsigned int irq) | 173 | static void sni_rm200_enable_8259A_irq(unsigned int irq) |
| @@ -177,13 +177,13 @@ static void sni_rm200_enable_8259A_irq(unsigned int irq) | |||
| 177 | 177 | ||
| 178 | irq -= RM200_I8259A_IRQ_BASE; | 178 | irq -= RM200_I8259A_IRQ_BASE; |
| 179 | mask = ~(1 << irq); | 179 | mask = ~(1 << irq); |
| 180 | spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); | 180 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
| 181 | rm200_cached_irq_mask &= mask; | 181 | rm200_cached_irq_mask &= mask; |
| 182 | if (irq & 8) | 182 | if (irq & 8) |
| 183 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | 183 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); |
| 184 | else | 184 | else |
| 185 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | 185 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); |
| 186 | spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); | 186 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
| 187 | } | 187 | } |
| 188 | 188 | ||
| 189 | static inline int sni_rm200_i8259A_irq_real(unsigned int irq) | 189 | static inline int sni_rm200_i8259A_irq_real(unsigned int irq) |
| @@ -216,7 +216,7 @@ void sni_rm200_mask_and_ack_8259A(unsigned int irq) | |||
| 216 | 216 | ||
| 217 | irq -= RM200_I8259A_IRQ_BASE; | 217 | irq -= RM200_I8259A_IRQ_BASE; |
| 218 | irqmask = 1 << irq; | 218 | irqmask = 1 << irq; |
| 219 | spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); | 219 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
| 220 | /* | 220 | /* |
| 221 | * Lightweight spurious IRQ detection. We do not want | 221 | * Lightweight spurious IRQ detection. We do not want |
| 222 | * to overdo spurious IRQ handling - it's usually a sign | 222 | * to overdo spurious IRQ handling - it's usually a sign |
| @@ -247,7 +247,7 @@ handle_real_irq: | |||
| 247 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | 247 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); |
| 248 | writeb(0x60+irq, rm200_pic_master + PIC_CMD); | 248 | writeb(0x60+irq, rm200_pic_master + PIC_CMD); |
| 249 | } | 249 | } |
| 250 | spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); | 250 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
| 251 | return; | 251 | return; |
| 252 | 252 | ||
| 253 | spurious_8259A_irq: | 253 | spurious_8259A_irq: |
| @@ -298,7 +298,7 @@ static inline int sni_rm200_i8259_irq(void) | |||
| 298 | { | 298 | { |
| 299 | int irq; | 299 | int irq; |
| 300 | 300 | ||
| 301 | spin_lock(&sni_rm200_i8259A_lock); | 301 | raw_spin_lock(&sni_rm200_i8259A_lock); |
| 302 | 302 | ||
| 303 | /* Perform an interrupt acknowledge cycle on controller 1. */ | 303 | /* Perform an interrupt acknowledge cycle on controller 1. */ |
| 304 | writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */ | 304 | writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */ |
| @@ -325,7 +325,7 @@ static inline int sni_rm200_i8259_irq(void) | |||
| 325 | irq = -1; | 325 | irq = -1; |
| 326 | } | 326 | } |
| 327 | 327 | ||
| 328 | spin_unlock(&sni_rm200_i8259A_lock); | 328 | raw_spin_unlock(&sni_rm200_i8259A_lock); |
| 329 | 329 | ||
| 330 | return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq; | 330 | return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq; |
| 331 | } | 331 | } |
| @@ -334,7 +334,7 @@ void sni_rm200_init_8259A(void) | |||
| 334 | { | 334 | { |
| 335 | unsigned long flags; | 335 | unsigned long flags; |
| 336 | 336 | ||
| 337 | spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); | 337 | raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags); |
| 338 | 338 | ||
| 339 | writeb(0xff, rm200_pic_master + PIC_IMR); | 339 | writeb(0xff, rm200_pic_master + PIC_IMR); |
| 340 | writeb(0xff, rm200_pic_slave + PIC_IMR); | 340 | writeb(0xff, rm200_pic_slave + PIC_IMR); |
| @@ -352,7 +352,7 @@ void sni_rm200_init_8259A(void) | |||
| 352 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); | 352 | writeb(cached_master_mask, rm200_pic_master + PIC_IMR); |
| 353 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); | 353 | writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR); |
| 354 | 354 | ||
| 355 | spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); | 355 | raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags); |
| 356 | } | 356 | } |
| 357 | 357 | ||
| 358 | /* | 358 | /* |
