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authorMike Frysinger <vapier@gentoo.org>2009-11-17 01:15:01 -0500
committerMike Frysinger <vapier@gentoo.org>2009-12-15 00:16:16 -0500
commit31ad0e27ed71c30cd328b503ce6163392b4dd9e2 (patch)
tree6b0a3ef8380fd5f9d44f53c892e46b144e20ff0e
parentb1740549d493d3ea5d16bee1cdc7b1f200163ad5 (diff)
Blackfin: BF51x: unify def/cdef headers
Whole lot of duplicated code here just went bye bye. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF514.h13
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF516.h80
-rw-r--r--arch/blackfin/mach-bf518/include/mach/cdefBF518.h247
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF514.h45
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF516.h213
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF518.h592
6 files changed, 16 insertions, 1174 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
index e1d99911025d..108fa4bde277 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF514.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF514_H 7#ifndef _CDEF_BF514_H
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF514.h" 11#include "defBF514.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF514 is BF512 + RSI */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF512.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
22 15
23/* Removable Storage Interface Registers */ 16/* Removable Storage Interface Registers */
24 17
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
index 6b364eda4947..2751592ef1c1 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF516.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF516_H 7#ifndef _CDEF_BF516_H
@@ -10,15 +10,8 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF516.h" 11#include "defBF516.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF516 is BF514 + EMAC */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF514.h"
15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
22 15
23/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 16/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
24 17
@@ -185,71 +178,4 @@
185#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT) 178#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
186#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val) 179#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
187 180
188/* Removable Storage Interface Registers */
189
190#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
191#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
192#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
193#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
194#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
195#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
196#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
197#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
198#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
199#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
200#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
201#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
202#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
203#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
204#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
205#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
206#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
207#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
208#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
209#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
210#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
211#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
212#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
213#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
214#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
215#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
216#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
217#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
218#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
219#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
220#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
221#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
222#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
223#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
224#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
225#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
226#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
227#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
228#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
229#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
230#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
231#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
232#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
233#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
234#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
235#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
236#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
237#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
238#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
239#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
240#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
241#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
242#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
243#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
244#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
245#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
246#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
247#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
248#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
249#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
250#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
251#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
252#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
253#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
254
255#endif /* _CDEF_BF516_H */ 181#endif /* _CDEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
index 929b90650bd4..7fb7f0eab990 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF518.h
@@ -1,7 +1,7 @@
1/* 1/*
2 * Copyright 2008-2009 Analog Devices Inc. 2 * Copyright 2008-2009 Analog Devices Inc.
3 * 3 *
4 * Licensed under the GPL-2 or later 4 * Licensed under the ADI BSD license or the GPL-2 (or later)
5 */ 5 */
6 6
7#ifndef _CDEF_BF518_H 7#ifndef _CDEF_BF518_H
@@ -10,181 +10,10 @@
10/* include all Core registers and bit definitions */ 10/* include all Core registers and bit definitions */
11#include "defBF518.h" 11#include "defBF518.h"
12 12
13/* include core specific register pointer definitions */ 13/* BF518 is BF516 + IEEE-1588 */
14#include <asm/cdef_LPBlackfin.h> 14#include "cdefBF516.h"
15 15
16/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */ 16/* PTP TSYNC Registers */
17
18/* include cdefBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
19#include "cdefBF51x_base.h"
20
21/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
22
23
24/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
25
26#define bfin_read_EMAC_OPMODE() bfin_read32(EMAC_OPMODE)
27#define bfin_write_EMAC_OPMODE(val) bfin_write32(EMAC_OPMODE, val)
28#define bfin_read_EMAC_ADDRLO() bfin_read32(EMAC_ADDRLO)
29#define bfin_write_EMAC_ADDRLO(val) bfin_write32(EMAC_ADDRLO, val)
30#define bfin_read_EMAC_ADDRHI() bfin_read32(EMAC_ADDRHI)
31#define bfin_write_EMAC_ADDRHI(val) bfin_write32(EMAC_ADDRHI, val)
32#define bfin_read_EMAC_HASHLO() bfin_read32(EMAC_HASHLO)
33#define bfin_write_EMAC_HASHLO(val) bfin_write32(EMAC_HASHLO, val)
34#define bfin_read_EMAC_HASHHI() bfin_read32(EMAC_HASHHI)
35#define bfin_write_EMAC_HASHHI(val) bfin_write32(EMAC_HASHHI, val)
36#define bfin_read_EMAC_STAADD() bfin_read32(EMAC_STAADD)
37#define bfin_write_EMAC_STAADD(val) bfin_write32(EMAC_STAADD, val)
38#define bfin_read_EMAC_STADAT() bfin_read32(EMAC_STADAT)
39#define bfin_write_EMAC_STADAT(val) bfin_write32(EMAC_STADAT, val)
40#define bfin_read_EMAC_FLC() bfin_read32(EMAC_FLC)
41#define bfin_write_EMAC_FLC(val) bfin_write32(EMAC_FLC, val)
42#define bfin_read_EMAC_VLAN1() bfin_read32(EMAC_VLAN1)
43#define bfin_write_EMAC_VLAN1(val) bfin_write32(EMAC_VLAN1, val)
44#define bfin_read_EMAC_VLAN2() bfin_read32(EMAC_VLAN2)
45#define bfin_write_EMAC_VLAN2(val) bfin_write32(EMAC_VLAN2, val)
46#define bfin_read_EMAC_WKUP_CTL() bfin_read32(EMAC_WKUP_CTL)
47#define bfin_write_EMAC_WKUP_CTL(val) bfin_write32(EMAC_WKUP_CTL, val)
48#define bfin_read_EMAC_WKUP_FFMSK0() bfin_read32(EMAC_WKUP_FFMSK0)
49#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
50#define bfin_read_EMAC_WKUP_FFMSK1() bfin_read32(EMAC_WKUP_FFMSK1)
51#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
52#define bfin_read_EMAC_WKUP_FFMSK2() bfin_read32(EMAC_WKUP_FFMSK2)
53#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
54#define bfin_read_EMAC_WKUP_FFMSK3() bfin_read32(EMAC_WKUP_FFMSK3)
55#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
56#define bfin_read_EMAC_WKUP_FFCMD() bfin_read32(EMAC_WKUP_FFCMD)
57#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
58#define bfin_read_EMAC_WKUP_FFOFF() bfin_read32(EMAC_WKUP_FFOFF)
59#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
60#define bfin_read_EMAC_WKUP_FFCRC0() bfin_read32(EMAC_WKUP_FFCRC0)
61#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
62#define bfin_read_EMAC_WKUP_FFCRC1() bfin_read32(EMAC_WKUP_FFCRC1)
63#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
64
65#define bfin_read_EMAC_SYSCTL() bfin_read32(EMAC_SYSCTL)
66#define bfin_write_EMAC_SYSCTL(val) bfin_write32(EMAC_SYSCTL, val)
67#define bfin_read_EMAC_SYSTAT() bfin_read32(EMAC_SYSTAT)
68#define bfin_write_EMAC_SYSTAT(val) bfin_write32(EMAC_SYSTAT, val)
69#define bfin_read_EMAC_RX_STAT() bfin_read32(EMAC_RX_STAT)
70#define bfin_write_EMAC_RX_STAT(val) bfin_write32(EMAC_RX_STAT, val)
71#define bfin_read_EMAC_RX_STKY() bfin_read32(EMAC_RX_STKY)
72#define bfin_write_EMAC_RX_STKY(val) bfin_write32(EMAC_RX_STKY, val)
73#define bfin_read_EMAC_RX_IRQE() bfin_read32(EMAC_RX_IRQE)
74#define bfin_write_EMAC_RX_IRQE(val) bfin_write32(EMAC_RX_IRQE, val)
75#define bfin_read_EMAC_TX_STAT() bfin_read32(EMAC_TX_STAT)
76#define bfin_write_EMAC_TX_STAT(val) bfin_write32(EMAC_TX_STAT, val)
77#define bfin_read_EMAC_TX_STKY() bfin_read32(EMAC_TX_STKY)
78#define bfin_write_EMAC_TX_STKY(val) bfin_write32(EMAC_TX_STKY, val)
79#define bfin_read_EMAC_TX_IRQE() bfin_read32(EMAC_TX_IRQE)
80#define bfin_write_EMAC_TX_IRQE(val) bfin_write32(EMAC_TX_IRQE, val)
81
82#define bfin_read_EMAC_MMC_CTL() bfin_read32(EMAC_MMC_CTL)
83#define bfin_write_EMAC_MMC_CTL(val) bfin_write32(EMAC_MMC_CTL, val)
84#define bfin_read_EMAC_MMC_RIRQS() bfin_read32(EMAC_MMC_RIRQS)
85#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
86#define bfin_read_EMAC_MMC_RIRQE() bfin_read32(EMAC_MMC_RIRQE)
87#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
88#define bfin_read_EMAC_MMC_TIRQS() bfin_read32(EMAC_MMC_TIRQS)
89#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
90#define bfin_read_EMAC_MMC_TIRQE() bfin_read32(EMAC_MMC_TIRQE)
91#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
92
93#define bfin_read_EMAC_RXC_OK() bfin_read32(EMAC_RXC_OK)
94#define bfin_write_EMAC_RXC_OK(val) bfin_write32(EMAC_RXC_OK, val)
95#define bfin_read_EMAC_RXC_FCS() bfin_read32(EMAC_RXC_FCS)
96#define bfin_write_EMAC_RXC_FCS(val) bfin_write32(EMAC_RXC_FCS, val)
97#define bfin_read_EMAC_RXC_ALIGN() bfin_read32(EMAC_RXC_ALIGN)
98#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
99#define bfin_read_EMAC_RXC_OCTET() bfin_read32(EMAC_RXC_OCTET)
100#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
101#define bfin_read_EMAC_RXC_DMAOVF() bfin_read32(EMAC_RXC_DMAOVF)
102#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
103#define bfin_read_EMAC_RXC_UNICST() bfin_read32(EMAC_RXC_UNICST)
104#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
105#define bfin_read_EMAC_RXC_MULTI() bfin_read32(EMAC_RXC_MULTI)
106#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
107#define bfin_read_EMAC_RXC_BROAD() bfin_read32(EMAC_RXC_BROAD)
108#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
109#define bfin_read_EMAC_RXC_LNERRI() bfin_read32(EMAC_RXC_LNERRI)
110#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
111#define bfin_read_EMAC_RXC_LNERRO() bfin_read32(EMAC_RXC_LNERRO)
112#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
113#define bfin_read_EMAC_RXC_LONG() bfin_read32(EMAC_RXC_LONG)
114#define bfin_write_EMAC_RXC_LONG(val) bfin_write32(EMAC_RXC_LONG, val)
115#define bfin_read_EMAC_RXC_MACCTL() bfin_read32(EMAC_RXC_MACCTL)
116#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
117#define bfin_read_EMAC_RXC_OPCODE() bfin_read32(EMAC_RXC_OPCODE)
118#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
119#define bfin_read_EMAC_RXC_PAUSE() bfin_read32(EMAC_RXC_PAUSE)
120#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
121#define bfin_read_EMAC_RXC_ALLFRM() bfin_read32(EMAC_RXC_ALLFRM)
122#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
123#define bfin_read_EMAC_RXC_ALLOCT() bfin_read32(EMAC_RXC_ALLOCT)
124#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
125#define bfin_read_EMAC_RXC_TYPED() bfin_read32(EMAC_RXC_TYPED)
126#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
127#define bfin_read_EMAC_RXC_SHORT() bfin_read32(EMAC_RXC_SHORT)
128#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
129#define bfin_read_EMAC_RXC_EQ64() bfin_read32(EMAC_RXC_EQ64)
130#define bfin_write_EMAC_RXC_EQ64(val) bfin_write32(EMAC_RXC_EQ64, val)
131#define bfin_read_EMAC_RXC_LT128() bfin_read32(EMAC_RXC_LT128)
132#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
133#define bfin_read_EMAC_RXC_LT256() bfin_read32(EMAC_RXC_LT256)
134#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
135#define bfin_read_EMAC_RXC_LT512() bfin_read32(EMAC_RXC_LT512)
136#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
137#define bfin_read_EMAC_RXC_LT1024() bfin_read32(EMAC_RXC_LT1024)
138#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
139#define bfin_read_EMAC_RXC_GE1024() bfin_read32(EMAC_RXC_GE1024)
140#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
141
142#define bfin_read_EMAC_TXC_OK() bfin_read32(EMAC_TXC_OK)
143#define bfin_write_EMAC_TXC_OK(val) bfin_write32(EMAC_TXC_OK, val)
144#define bfin_read_EMAC_TXC_1COL() bfin_read32(EMAC_TXC_1COL)
145#define bfin_write_EMAC_TXC_1COL(val) bfin_write32(EMAC_TXC_1COL, val)
146#define bfin_read_EMAC_TXC_GT1COL() bfin_read32(EMAC_TXC_GT1COL)
147#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
148#define bfin_read_EMAC_TXC_OCTET() bfin_read32(EMAC_TXC_OCTET)
149#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
150#define bfin_read_EMAC_TXC_DEFER() bfin_read32(EMAC_TXC_DEFER)
151#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
152#define bfin_read_EMAC_TXC_LATECL() bfin_read32(EMAC_TXC_LATECL)
153#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
154#define bfin_read_EMAC_TXC_XS_COL() bfin_read32(EMAC_TXC_XS_COL)
155#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
156#define bfin_read_EMAC_TXC_DMAUND() bfin_read32(EMAC_TXC_DMAUND)
157#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
158#define bfin_read_EMAC_TXC_CRSERR() bfin_read32(EMAC_TXC_CRSERR)
159#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
160#define bfin_read_EMAC_TXC_UNICST() bfin_read32(EMAC_TXC_UNICST)
161#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
162#define bfin_read_EMAC_TXC_MULTI() bfin_read32(EMAC_TXC_MULTI)
163#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
164#define bfin_read_EMAC_TXC_BROAD() bfin_read32(EMAC_TXC_BROAD)
165#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
166#define bfin_read_EMAC_TXC_XS_DFR() bfin_read32(EMAC_TXC_XS_DFR)
167#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
168#define bfin_read_EMAC_TXC_MACCTL() bfin_read32(EMAC_TXC_MACCTL)
169#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
170#define bfin_read_EMAC_TXC_ALLFRM() bfin_read32(EMAC_TXC_ALLFRM)
171#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
172#define bfin_read_EMAC_TXC_ALLOCT() bfin_read32(EMAC_TXC_ALLOCT)
173#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
174#define bfin_read_EMAC_TXC_EQ64() bfin_read32(EMAC_TXC_EQ64)
175#define bfin_write_EMAC_TXC_EQ64(val) bfin_write32(EMAC_TXC_EQ64, val)
176#define bfin_read_EMAC_TXC_LT128() bfin_read32(EMAC_TXC_LT128)
177#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
178#define bfin_read_EMAC_TXC_LT256() bfin_read32(EMAC_TXC_LT256)
179#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
180#define bfin_read_EMAC_TXC_LT512() bfin_read32(EMAC_TXC_LT512)
181#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
182#define bfin_read_EMAC_TXC_LT1024() bfin_read32(EMAC_TXC_LT1024)
183#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
184#define bfin_read_EMAC_TXC_GE1024() bfin_read32(EMAC_TXC_GE1024)
185#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
186#define bfin_read_EMAC_TXC_ABORT() bfin_read32(EMAC_TXC_ABORT)
187#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
188 17
189#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL) 18#define bfin_read_EMAC_PTP_CTL() bfin_read16(EMAC_PTP_CTL)
190#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val) 19#define bfin_write_EMAC_PTP_CTL(val) bfin_write16(EMAC_PTP_CTL, val)
@@ -227,72 +56,4 @@
227#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD) 56#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
228#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val) 57#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
229 58
230/* Removable Storage Interface Registers */
231
232#define bfin_read_RSI_PWR_CTL() bfin_read16(RSI_PWR_CONTROL)
233#define bfin_write_RSI_PWR_CTL(val) bfin_write16(RSI_PWR_CONTROL, val)
234#define bfin_read_RSI_CLK_CTL() bfin_read16(RSI_CLK_CONTROL)
235#define bfin_write_RSI_CLK_CTL(val) bfin_write16(RSI_CLK_CONTROL, val)
236#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
237#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
238#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
239#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
240#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
241#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
242#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
243#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
244#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
245#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
246#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
247#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
248#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
249#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
250#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
251#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
252#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
253#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
254#define bfin_read_RSI_DATA_CTL() bfin_read16(RSI_DATA_CONTROL)
255#define bfin_write_RSI_DATA_CTL(val) bfin_write16(RSI_DATA_CONTROL, val)
256#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
257#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
258#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
259#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
260#define bfin_read_RSI_STATUS_CLR() bfin_read16(RSI_STATUSCL)
261#define bfin_write_RSI_STATUS_CLR(val) bfin_write16(RSI_STATUSCL, val)
262#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
263#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
264#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
265#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
266#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
267#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
268#define bfin_read_RSI_CEATA_CTL() bfin_read16(RSI_CEATA_CONTROL)
269#define bfin_write_RSI_CEATA_CTL(val) bfin_write16(RSI_CEATA_CONTROL, val)
270#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
271#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
272#define bfin_read_RSI_E_STATUS() bfin_read16(RSI_ESTAT)
273#define bfin_write_RSI_E_STATUS(val) bfin_write16(RSI_ESTAT, val)
274#define bfin_read_RSI_E_MASK() bfin_read16(RSI_EMASK)
275#define bfin_write_RSI_E_MASK(val) bfin_write16(RSI_EMASK, val)
276#define bfin_read_RSI_CFG() bfin_read16(RSI_CONFIG)
277#define bfin_write_RSI_CFG(val) bfin_write16(RSI_CONFIG, val)
278#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
279#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
280#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
281#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
282#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
283#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
284#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
285#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
286#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
287#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
288#define bfin_read_RSI_PID4() bfin_read16(RSI_PID4)
289#define bfin_write_RSI_PID4(val) bfin_write16(RSI_PID4, val)
290#define bfin_read_RSI_PID5() bfin_read16(RSI_PID5)
291#define bfin_write_RSI_PID5(val) bfin_write16(RSI_PID5, val)
292#define bfin_read_RSI_PID6() bfin_read16(RSI_PID6)
293#define bfin_write_RSI_PID6(val) bfin_write16(RSI_PID6, val)
294#define bfin_read_RSI_PID7() bfin_read16(RSI_PID7)
295#define bfin_write_RSI_PID7(val) bfin_write16(RSI_PID7, val)
296
297
298#endif /* _CDEF_BF518_H */ 59#endif /* _CDEF_BF518_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF514.h b/arch/blackfin/mach-bf518/include/mach/defBF514.h
index b5adca23a788..92e950d6e996 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF514.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF514.h
@@ -7,49 +7,8 @@
7#ifndef _DEF_BF514_H 7#ifndef _DEF_BF514_H
8#define _DEF_BF514_H 8#define _DEF_BF514_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF514 is BF512 + RSI */
11#include <asm/def_LPBlackfin.h> 11#include "defBF512.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF514 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17
18/* The following are the #defines needed by ADSP-BF514 that are not in the common header */
19
20/* SDH Registers */
21
22#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
23#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
24#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
25#define SDH_COMMAND 0xFFC0390C /* SDH Command */
26#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
27#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
28#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
29#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
30#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
31#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
32#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
33#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
34#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
35#define SDH_STATUS 0xFFC03934 /* SDH Status */
36#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
37#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
38#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
39#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
40#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
41#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
42#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
43#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
44#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
45#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
46#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
47#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
48#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
49#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
50#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
51#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
52#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
53 12
54/* Removable Storage Interface Registers */ 13/* Removable Storage Interface Registers */
55 14
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF516.h b/arch/blackfin/mach-bf518/include/mach/defBF516.h
index 7eb18774d727..22a3aa0d2629 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF516.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF516.h
@@ -7,13 +7,8 @@
7#ifndef _DEF_BF516_H 7#ifndef _DEF_BF516_H
8#define _DEF_BF516_H 8#define _DEF_BF516_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF516 is BF514 + EMAC */
11#include <asm/def_LPBlackfin.h> 11#include "defBF514.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF516 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17 12
18/* The following are the #defines needed by ADSP-BF516 that are not in the common header */ 13/* The following are the #defines needed by ADSP-BF516 that are not in the common header */
19/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */ 14/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
@@ -394,208 +389,4 @@
394#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */ 389#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */ 390#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
396 391
397/* SDH Registers */
398
399#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
400#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
401#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
402#define SDH_COMMAND 0xFFC0390C /* SDH Command */
403#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
404#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
405#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
406#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
407#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
408#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
409#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
410#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
411#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
412#define SDH_STATUS 0xFFC03934 /* SDH Status */
413#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
414#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
415#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
416#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
417#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
418#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
419#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
420#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
421#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
422#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
423#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
424#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
425#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
426#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
427#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
428#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
429#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
430
431/* Removable Storage Interface Registers */
432
433#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
434#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
435#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
436#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
437#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
438#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
439#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
440#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
441#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
442#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
443#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
444#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
445#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
446#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
447#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
448#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
449#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
450#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
451#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
452#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
453#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
454#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
455#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
456#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
457#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
458#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
459#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
460#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
461#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
462#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
463#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
464#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
465
466/* ********************************************************** */
467/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
468/* and MULTI BIT READ MACROS */
469/* ********************************************************** */
470
471/* Bit masks for SDH_COMMAND */
472
473#define CMD_IDX 0x3f /* Command Index */
474#define CMD_RSP 0x40 /* Response */
475#define CMD_L_RSP 0x80 /* Long Response */
476#define CMD_INT_E 0x100 /* Command Interrupt */
477#define CMD_PEND_E 0x200 /* Command Pending */
478#define CMD_E 0x400 /* Command Enable */
479
480/* Bit masks for SDH_PWR_CTL */
481
482#define PWR_ON 0x3 /* Power On */
483#if 0
484#define TBD 0x3c /* TBD */
485#endif
486#define SD_CMD_OD 0x40 /* Open Drain Output */
487#define ROD_CTL 0x80 /* Rod Control */
488
489/* Bit masks for SDH_CLK_CTL */
490
491#define CLKDIV 0xff /* MC_CLK Divisor */
492#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
493#define PWR_SV_E 0x200 /* Power Save Enable */
494#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
495#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
496
497/* Bit masks for SDH_RESP_CMD */
498
499#define RESP_CMD 0x3f /* Response Command */
500
501/* Bit masks for SDH_DATA_CTL */
502
503#define DTX_E 0x1 /* Data Transfer Enable */
504#define DTX_DIR 0x2 /* Data Transfer Direction */
505#define DTX_MODE 0x4 /* Data Transfer Mode */
506#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
507#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
508
509/* Bit masks for SDH_STATUS */
510
511#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
512#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
513#define CMD_TIME_OUT 0x4 /* CMD Time Out */
514#define DAT_TIME_OUT 0x8 /* Data Time Out */
515#define TX_UNDERRUN 0x10 /* Transmit Underrun */
516#define RX_OVERRUN 0x20 /* Receive Overrun */
517#define CMD_RESP_END 0x40 /* CMD Response End */
518#define CMD_SENT 0x80 /* CMD Sent */
519#define DAT_END 0x100 /* Data End */
520#define START_BIT_ERR 0x200 /* Start Bit Error */
521#define DAT_BLK_END 0x400 /* Data Block End */
522#define CMD_ACT 0x800 /* CMD Active */
523#define TX_ACT 0x1000 /* Transmit Active */
524#define RX_ACT 0x2000 /* Receive Active */
525#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
526#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
527#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
528#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
529#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
530#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
531#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
532#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
533
534/* Bit masks for SDH_STATUS_CLR */
535
536#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
537#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
538#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
539#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
540#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
541#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
542#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
543#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
544#define DAT_END_STAT 0x100 /* Data End Status */
545#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
546#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
547
548/* Bit masks for SDH_MASK0 */
549
550#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
551#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
552#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
553#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
554#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
555#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
556#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
557#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
558#define DAT_END_MASK 0x100 /* Data End Mask */
559#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
560#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
561#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
562#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
563#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
564#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
565#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
566#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
567#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
568#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
569#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
570#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
571#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
572
573/* Bit masks for SDH_FIFO_CNT */
574
575#define FIFO_COUNT 0x7fff /* FIFO Count */
576
577/* Bit masks for SDH_E_STATUS */
578
579#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
580#define SD_CARD_DET 0x10 /* SD Card Detect */
581
582/* Bit masks for SDH_E_MASK */
583
584#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
585#define SCD_MSK 0x40 /* Mask Card Detect */
586
587/* Bit masks for SDH_CFG */
588
589#define CLKS_EN 0x1 /* Clocks Enable */
590#define SD4E 0x4 /* SDIO 4-Bit Enable */
591#define MWE 0x8 /* Moving Window Enable */
592#define SD_RST 0x10 /* SDMMC Reset */
593#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
594#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
595#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
596
597/* Bit masks for SDH_RD_WAIT_EN */
598
599#define RWR 0x1 /* Read Wait Request */
600
601#endif /* _DEF_BF516_H */ 392#endif /* _DEF_BF516_H */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF518.h b/arch/blackfin/mach-bf518/include/mach/defBF518.h
index 794cf06eb5ba..cb18270e55c2 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF518.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF518.h
@@ -7,461 +7,8 @@
7#ifndef _DEF_BF518_H 7#ifndef _DEF_BF518_H
8#define _DEF_BF518_H 8#define _DEF_BF518_H
9 9
10/* Include all Core registers and bit definitions */ 10/* BF518 is BF516 + IEEE-1588 */
11#include <asm/def_LPBlackfin.h> 11#include "defBF516.h"
12
13/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF518 */
14
15/* Include defBF51x_base.h for the set of #defines that are common to all ADSP-BF51x processors */
16#include "defBF51x_base.h"
17
18/* The following are the #defines needed by ADSP-BF518 that are not in the common header */
19/* 10/100 Ethernet Controller (0xFFC03000 - 0xFFC031FF) */
20
21#define EMAC_OPMODE 0xFFC03000 /* Operating Mode Register */
22#define EMAC_ADDRLO 0xFFC03004 /* Address Low (32 LSBs) Register */
23#define EMAC_ADDRHI 0xFFC03008 /* Address High (16 MSBs) Register */
24#define EMAC_HASHLO 0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
25#define EMAC_HASHHI 0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
26#define EMAC_STAADD 0xFFC03014 /* Station Management Address Register */
27#define EMAC_STADAT 0xFFC03018 /* Station Management Data Register */
28#define EMAC_FLC 0xFFC0301C /* Flow Control Register */
29#define EMAC_VLAN1 0xFFC03020 /* VLAN1 Tag Register */
30#define EMAC_VLAN2 0xFFC03024 /* VLAN2 Tag Register */
31#define EMAC_WKUP_CTL 0xFFC0302C /* Wake-Up Control/Status Register */
32#define EMAC_WKUP_FFMSK0 0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
33#define EMAC_WKUP_FFMSK1 0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
34#define EMAC_WKUP_FFMSK2 0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
35#define EMAC_WKUP_FFMSK3 0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
36#define EMAC_WKUP_FFCMD 0xFFC03040 /* Wake-Up Frame Filter Commands Register */
37#define EMAC_WKUP_FFOFF 0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
38#define EMAC_WKUP_FFCRC0 0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
39#define EMAC_WKUP_FFCRC1 0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
40
41#define EMAC_SYSCTL 0xFFC03060 /* EMAC System Control Register */
42#define EMAC_SYSTAT 0xFFC03064 /* EMAC System Status Register */
43#define EMAC_RX_STAT 0xFFC03068 /* RX Current Frame Status Register */
44#define EMAC_RX_STKY 0xFFC0306C /* RX Sticky Frame Status Register */
45#define EMAC_RX_IRQE 0xFFC03070 /* RX Frame Status Interrupt Enables Register */
46#define EMAC_TX_STAT 0xFFC03074 /* TX Current Frame Status Register */
47#define EMAC_TX_STKY 0xFFC03078 /* TX Sticky Frame Status Register */
48#define EMAC_TX_IRQE 0xFFC0307C /* TX Frame Status Interrupt Enables Register */
49
50#define EMAC_MMC_CTL 0xFFC03080 /* MMC Counter Control Register */
51#define EMAC_MMC_RIRQS 0xFFC03084 /* MMC RX Interrupt Status Register */
52#define EMAC_MMC_RIRQE 0xFFC03088 /* MMC RX Interrupt Enables Register */
53#define EMAC_MMC_TIRQS 0xFFC0308C /* MMC TX Interrupt Status Register */
54#define EMAC_MMC_TIRQE 0xFFC03090 /* MMC TX Interrupt Enables Register */
55
56#define EMAC_RXC_OK 0xFFC03100 /* RX Frame Successful Count */
57#define EMAC_RXC_FCS 0xFFC03104 /* RX Frame FCS Failure Count */
58#define EMAC_RXC_ALIGN 0xFFC03108 /* RX Alignment Error Count */
59#define EMAC_RXC_OCTET 0xFFC0310C /* RX Octets Successfully Received Count */
60#define EMAC_RXC_DMAOVF 0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
61#define EMAC_RXC_UNICST 0xFFC03114 /* Unicast RX Frame Count */
62#define EMAC_RXC_MULTI 0xFFC03118 /* Multicast RX Frame Count */
63#define EMAC_RXC_BROAD 0xFFC0311C /* Broadcast RX Frame Count */
64#define EMAC_RXC_LNERRI 0xFFC03120 /* RX Frame In Range Error Count */
65#define EMAC_RXC_LNERRO 0xFFC03124 /* RX Frame Out Of Range Error Count */
66#define EMAC_RXC_LONG 0xFFC03128 /* RX Frame Too Long Count */
67#define EMAC_RXC_MACCTL 0xFFC0312C /* MAC Control RX Frame Count */
68#define EMAC_RXC_OPCODE 0xFFC03130 /* Unsupported Op-Code RX Frame Count */
69#define EMAC_RXC_PAUSE 0xFFC03134 /* MAC Control Pause RX Frame Count */
70#define EMAC_RXC_ALLFRM 0xFFC03138 /* Overall RX Frame Count */
71#define EMAC_RXC_ALLOCT 0xFFC0313C /* Overall RX Octet Count */
72#define EMAC_RXC_TYPED 0xFFC03140 /* Type/Length Consistent RX Frame Count */
73#define EMAC_RXC_SHORT 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
74#define EMAC_RXC_EQ64 0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
75#define EMAC_RXC_LT128 0xFFC0314C /* Good RX Frame Count - Byte Count 64 < x < 128 */
76#define EMAC_RXC_LT256 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
77#define EMAC_RXC_LT512 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
78#define EMAC_RXC_LT1024 0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
79#define EMAC_RXC_GE1024 0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
80
81#define EMAC_TXC_OK 0xFFC03180 /* TX Frame Successful Count */
82#define EMAC_TXC_1COL 0xFFC03184 /* TX Frames Successful After Single Collision Count */
83#define EMAC_TXC_GT1COL 0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
84#define EMAC_TXC_OCTET 0xFFC0318C /* TX Octets Successfully Received Count */
85#define EMAC_TXC_DEFER 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
86#define EMAC_TXC_LATECL 0xFFC03194 /* Late TX Collisions Count */
87#define EMAC_TXC_XS_COL 0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
88#define EMAC_TXC_DMAUND 0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
89#define EMAC_TXC_CRSERR 0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
90#define EMAC_TXC_UNICST 0xFFC031A4 /* Unicast TX Frame Count */
91#define EMAC_TXC_MULTI 0xFFC031A8 /* Multicast TX Frame Count */
92#define EMAC_TXC_BROAD 0xFFC031AC /* Broadcast TX Frame Count */
93#define EMAC_TXC_XS_DFR 0xFFC031B0 /* TX Frames With Excessive Deferral Count */
94#define EMAC_TXC_MACCTL 0xFFC031B4 /* MAC Control TX Frame Count */
95#define EMAC_TXC_ALLFRM 0xFFC031B8 /* Overall TX Frame Count */
96#define EMAC_TXC_ALLOCT 0xFFC031BC /* Overall TX Octet Count */
97#define EMAC_TXC_EQ64 0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
98#define EMAC_TXC_LT128 0xFFC031C4 /* Good TX Frame Count - Byte Count 64 < x < 128 */
99#define EMAC_TXC_LT256 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
100#define EMAC_TXC_LT512 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
101#define EMAC_TXC_LT1024 0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
102#define EMAC_TXC_GE1024 0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
103#define EMAC_TXC_ABORT 0xFFC031D8 /* Total TX Frames Aborted Count */
104
105/* Listing for IEEE-Supported Count Registers */
106
107#define FramesReceivedOK EMAC_RXC_OK /* RX Frame Successful Count */
108#define FrameCheckSequenceErrors EMAC_RXC_FCS /* RX Frame FCS Failure Count */
109#define AlignmentErrors EMAC_RXC_ALIGN /* RX Alignment Error Count */
110#define OctetsReceivedOK EMAC_RXC_OCTET /* RX Octets Successfully Received Count */
111#define FramesLostDueToIntMACRcvError EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count */
112#define UnicastFramesReceivedOK EMAC_RXC_UNICST /* Unicast RX Frame Count */
113#define MulticastFramesReceivedOK EMAC_RXC_MULTI /* Multicast RX Frame Count */
114#define BroadcastFramesReceivedOK EMAC_RXC_BROAD /* Broadcast RX Frame Count */
115#define InRangeLengthErrors EMAC_RXC_LNERRI /* RX Frame In Range Error Count */
116#define OutOfRangeLengthField EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count */
117#define FrameTooLongErrors EMAC_RXC_LONG /* RX Frame Too Long Count */
118#define MACControlFramesReceived EMAC_RXC_MACCTL /* MAC Control RX Frame Count */
119#define UnsupportedOpcodesReceived EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count */
120#define PAUSEMACCtrlFramesReceived EMAC_RXC_PAUSE /* MAC Control Pause RX Frame Count */
121#define FramesReceivedAll EMAC_RXC_ALLFRM /* Overall RX Frame Count */
122#define OctetsReceivedAll EMAC_RXC_ALLOCT /* Overall RX Octet Count */
123#define TypedFramesReceived EMAC_RXC_TYPED /* Type/Length Consistent RX Frame Count */
124#define FramesLenLt64Received EMAC_RXC_SHORT /* RX Frame Fragment Count - Byte Count x < 64 */
125#define FramesLenEq64Received EMAC_RXC_EQ64 /* Good RX Frame Count - Byte Count x = 64 */
126#define FramesLen65_127Received EMAC_RXC_LT128 /* Good RX Frame Count - Byte Count 64 < x < 128 */
127#define FramesLen128_255Received EMAC_RXC_LT256 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
128#define FramesLen256_511Received EMAC_RXC_LT512 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
129#define FramesLen512_1023Received EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
130#define FramesLen1024_MaxReceived EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024 */
131
132#define FramesTransmittedOK EMAC_TXC_OK /* TX Frame Successful Count */
133#define SingleCollisionFrames EMAC_TXC_1COL /* TX Frames Successful After Single Collision Count */
134#define MultipleCollisionFrames EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
135#define OctetsTransmittedOK EMAC_TXC_OCTET /* TX Octets Successfully Received Count */
136#define FramesWithDeferredXmissions EMAC_TXC_DEFER /* TX Frame Delayed Due To Busy Count */
137#define LateCollisions EMAC_TXC_LATECL /* Late TX Collisions Count */
138#define FramesAbortedDueToXSColls EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count */
139#define FramesLostDueToIntMacXmitError EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count */
140#define CarrierSenseErrors EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count */
141#define UnicastFramesXmittedOK EMAC_TXC_UNICST /* Unicast TX Frame Count */
142#define MulticastFramesXmittedOK EMAC_TXC_MULTI /* Multicast TX Frame Count */
143#define BroadcastFramesXmittedOK EMAC_TXC_BROAD /* Broadcast TX Frame Count */
144#define FramesWithExcessiveDeferral EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count */
145#define MACControlFramesTransmitted EMAC_TXC_MACCTL /* MAC Control TX Frame Count */
146#define FramesTransmittedAll EMAC_TXC_ALLFRM /* Overall TX Frame Count */
147#define OctetsTransmittedAll EMAC_TXC_ALLOCT /* Overall TX Octet Count */
148#define FramesLenEq64Transmitted EMAC_TXC_EQ64 /* Good TX Frame Count - Byte Count x = 64 */
149#define FramesLen65_127Transmitted EMAC_TXC_LT128 /* Good TX Frame Count - Byte Count 64 < x < 128 */
150#define FramesLen128_255Transmitted EMAC_TXC_LT256 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
151#define FramesLen256_511Transmitted EMAC_TXC_LT512 /* Good TX Frame Count - Byte Count 256 <= x < 512 */
152#define FramesLen512_1023Transmitted EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
153#define FramesLen1024_MaxTransmitted EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024 */
154#define TxAbortedFrames EMAC_TXC_ABORT /* Total TX Frames Aborted Count */
155
156/***********************************************************************************
157** System MMR Register Bits And Macros
158**
159** Disclaimer: All macros are intended to make C and Assembly code more readable.
160** Use these macros carefully, as any that do left shifts for field
161** depositing will result in the lower order bits being destroyed. Any
162** macro that shifts left to properly position the bit-field should be
163** used as part of an OR to initialize a register and NOT as a dynamic
164** modifier UNLESS the lower order bits are saved and ORed back in when
165** the macro is used.
166*************************************************************************************/
167
168/************************ ETHERNET 10/100 CONTROLLER MASKS ************************/
169
170/* EMAC_OPMODE Masks */
171
172#define RE 0x00000001 /* Receiver Enable */
173#define ASTP 0x00000002 /* Enable Automatic Pad Stripping On RX Frames */
174#define HU 0x00000010 /* Hash Filter Unicast Address */
175#define HM 0x00000020 /* Hash Filter Multicast Address */
176#define PAM 0x00000040 /* Pass-All-Multicast Mode Enable */
177#define PR 0x00000080 /* Promiscuous Mode Enable */
178#define IFE 0x00000100 /* Inverse Filtering Enable */
179#define DBF 0x00000200 /* Disable Broadcast Frame Reception */
180#define PBF 0x00000400 /* Pass Bad Frames Enable */
181#define PSF 0x00000800 /* Pass Short Frames Enable */
182#define RAF 0x00001000 /* Receive-All Mode */
183#define TE 0x00010000 /* Transmitter Enable */
184#define DTXPAD 0x00020000 /* Disable Automatic TX Padding */
185#define DTXCRC 0x00040000 /* Disable Automatic TX CRC Generation */
186#define DC 0x00080000 /* Deferral Check */
187#define BOLMT 0x00300000 /* Back-Off Limit */
188#define BOLMT_10 0x00000000 /* 10-bit range */
189#define BOLMT_8 0x00100000 /* 8-bit range */
190#define BOLMT_4 0x00200000 /* 4-bit range */
191#define BOLMT_1 0x00300000 /* 1-bit range */
192#define DRTY 0x00400000 /* Disable TX Retry On Collision */
193#define LCTRE 0x00800000 /* Enable TX Retry On Late Collision */
194#define RMII 0x01000000 /* RMII/MII* Mode */
195#define RMII_10 0x02000000 /* Speed Select for RMII Port (10MBit/100MBit*) */
196#define FDMODE 0x04000000 /* Duplex Mode Enable (Full/Half*) */
197#define LB 0x08000000 /* Internal Loopback Enable */
198#define DRO 0x10000000 /* Disable Receive Own Frames (Half-Duplex Mode) */
199
200/* EMAC_STAADD Masks */
201
202#define STABUSY 0x00000001 /* Initiate Station Mgt Reg Access / STA Busy Stat */
203#define STAOP 0x00000002 /* Station Management Operation Code (Write/Read*) */
204#define STADISPRE 0x00000004 /* Disable Preamble Generation */
205#define STAIE 0x00000008 /* Station Mgt. Transfer Done Interrupt Enable */
206#define REGAD 0x000007C0 /* STA Register Address */
207#define PHYAD 0x0000F800 /* PHY Device Address */
208
209#define SET_REGAD(x) (((x)&0x1F)<< 6 ) /* Set STA Register Address */
210#define SET_PHYAD(x) (((x)&0x1F)<< 11 ) /* Set PHY Device Address */
211
212/* EMAC_STADAT Mask */
213
214#define STADATA 0x0000FFFF /* Station Management Data */
215
216/* EMAC_FLC Masks */
217
218#define FLCBUSY 0x00000001 /* Send Flow Ctrl Frame / Flow Ctrl Busy Status */
219#define FLCE 0x00000002 /* Flow Control Enable */
220#define PCF 0x00000004 /* Pass Control Frames */
221#define BKPRSEN 0x00000008 /* Enable Backpressure */
222#define FLCPAUSE 0xFFFF0000 /* Pause Time */
223
224#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time */
225
226/* EMAC_WKUP_CTL Masks */
227
228#define CAPWKFRM 0x00000001 /* Capture Wake-Up Frames */
229#define MPKE 0x00000002 /* Magic Packet Enable */
230#define RWKE 0x00000004 /* Remote Wake-Up Frame Enable */
231#define GUWKE 0x00000008 /* Global Unicast Wake Enable */
232#define MPKS 0x00000020 /* Magic Packet Received Status */
233#define RWKS 0x00000F00 /* Wake-Up Frame Received Status, Filters 3:0 */
234
235/* EMAC_WKUP_FFCMD Masks */
236
237#define WF0_E 0x00000001 /* Enable Wake-Up Filter 0 */
238#define WF0_T 0x00000008 /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*) */
239#define WF1_E 0x00000100 /* Enable Wake-Up Filter 1 */
240#define WF1_T 0x00000800 /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*) */
241#define WF2_E 0x00010000 /* Enable Wake-Up Filter 2 */
242#define WF2_T 0x00080000 /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*) */
243#define WF3_E 0x01000000 /* Enable Wake-Up Filter 3 */
244#define WF3_T 0x08000000 /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*) */
245
246/* EMAC_WKUP_FFOFF Masks */
247
248#define WF0_OFF 0x000000FF /* Wake-Up Filter 0 Pattern Offset */
249#define WF1_OFF 0x0000FF00 /* Wake-Up Filter 1 Pattern Offset */
250#define WF2_OFF 0x00FF0000 /* Wake-Up Filter 2 Pattern Offset */
251#define WF3_OFF 0xFF000000 /* Wake-Up Filter 3 Pattern Offset */
252
253#define SET_WF0_OFF(x) (((x)&0xFF)<< 0 ) /* Set Wake-Up Filter 0 Byte Offset */
254#define SET_WF1_OFF(x) (((x)&0xFF)<< 8 ) /* Set Wake-Up Filter 1 Byte Offset */
255#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset */
256#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset */
257/* Set ALL Offsets */
258#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
259
260/* EMAC_WKUP_FFCRC0 Masks */
261
262#define WF0_CRC 0x0000FFFF /* Wake-Up Filter 0 Pattern CRC */
263#define WF1_CRC 0xFFFF0000 /* Wake-Up Filter 1 Pattern CRC */
264
265#define SET_WF0_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 0 Target CRC */
266#define SET_WF1_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 1 Target CRC */
267
268/* EMAC_WKUP_FFCRC1 Masks */
269
270#define WF2_CRC 0x0000FFFF /* Wake-Up Filter 2 Pattern CRC */
271#define WF3_CRC 0xFFFF0000 /* Wake-Up Filter 3 Pattern CRC */
272
273#define SET_WF2_CRC(x) (((x)&0xFFFF)<< 0 ) /* Set Wake-Up Filter 2 Target CRC */
274#define SET_WF3_CRC(x) (((x)&0xFFFF)<< 16 ) /* Set Wake-Up Filter 3 Target CRC */
275
276/* EMAC_SYSCTL Masks */
277
278#define PHYIE 0x00000001 /* PHY_INT Interrupt Enable */
279#define RXDWA 0x00000002 /* Receive Frame DMA Word Alignment (Odd/Even*) */
280#define RXCKS 0x00000004 /* Enable RX Frame TCP/UDP Checksum Computation */
281#define TXDWA 0x00000010 /* Transmit Frame DMA Word Alignment (Odd/Even*) */
282#define MDCDIV 0x00003F00 /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))] */
283
284#define SET_MDCDIV(x) (((x)&0x3F)<< 8) /* Set MDC Clock Divisor */
285
286/* EMAC_SYSTAT Masks */
287
288#define PHYINT 0x00000001 /* PHY_INT Interrupt Status */
289#define MMCINT 0x00000002 /* MMC Counter Interrupt Status */
290#define RXFSINT 0x00000004 /* RX Frame-Status Interrupt Status */
291#define TXFSINT 0x00000008 /* TX Frame-Status Interrupt Status */
292#define WAKEDET 0x00000010 /* Wake-Up Detected Status */
293#define RXDMAERR 0x00000020 /* RX DMA Direction Error Status */
294#define TXDMAERR 0x00000040 /* TX DMA Direction Error Status */
295#define STMDONE 0x00000080 /* Station Mgt. Transfer Done Interrupt Status */
296
297/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
298
299#define RX_FRLEN 0x000007FF /* Frame Length In Bytes */
300#define RX_COMP 0x00001000 /* RX Frame Complete */
301#define RX_OK 0x00002000 /* RX Frame Received With No Errors */
302#define RX_LONG 0x00004000 /* RX Frame Too Long Error */
303#define RX_ALIGN 0x00008000 /* RX Frame Alignment Error */
304#define RX_CRC 0x00010000 /* RX Frame CRC Error */
305#define RX_LEN 0x00020000 /* RX Frame Length Error */
306#define RX_FRAG 0x00040000 /* RX Frame Fragment Error */
307#define RX_ADDR 0x00080000 /* RX Frame Address Filter Failed Error */
308#define RX_DMAO 0x00100000 /* RX Frame DMA Overrun Error */
309#define RX_PHY 0x00200000 /* RX Frame PHY Error */
310#define RX_LATE 0x00400000 /* RX Frame Late Collision Error */
311#define RX_RANGE 0x00800000 /* RX Frame Length Field Out of Range Error */
312#define RX_MULTI 0x01000000 /* RX Multicast Frame Indicator */
313#define RX_BROAD 0x02000000 /* RX Broadcast Frame Indicator */
314#define RX_CTL 0x04000000 /* RX Control Frame Indicator */
315#define RX_UCTL 0x08000000 /* Unsupported RX Control Frame Indicator */
316#define RX_TYPE 0x10000000 /* RX Typed Frame Indicator */
317#define RX_VLAN1 0x20000000 /* RX VLAN1 Frame Indicator */
318#define RX_VLAN2 0x40000000 /* RX VLAN2 Frame Indicator */
319#define RX_ACCEPT 0x80000000 /* RX Frame Accepted Indicator */
320
321/* EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks */
322
323#define TX_COMP 0x00000001 /* TX Frame Complete */
324#define TX_OK 0x00000002 /* TX Frame Sent With No Errors */
325#define TX_ECOLL 0x00000004 /* TX Frame Excessive Collision Error */
326#define TX_LATE 0x00000008 /* TX Frame Late Collision Error */
327#define TX_DMAU 0x00000010 /* TX Frame DMA Underrun Error (STAT) */
328#define TX_MACE 0x00000010 /* Internal MAC Error Detected (STKY and IRQE) */
329#define TX_EDEFER 0x00000020 /* TX Frame Excessive Deferral Error */
330#define TX_BROAD 0x00000040 /* TX Broadcast Frame Indicator */
331#define TX_MULTI 0x00000080 /* TX Multicast Frame Indicator */
332#define TX_CCNT 0x00000F00 /* TX Frame Collision Count */
333#define TX_DEFER 0x00001000 /* TX Frame Deferred Indicator */
334#define TX_CRS 0x00002000 /* TX Frame Carrier Sense Not Asserted Error */
335#define TX_LOSS 0x00004000 /* TX Frame Carrier Lost During TX Error */
336#define TX_RETRY 0x00008000 /* TX Frame Successful After Retry */
337#define TX_FRLEN 0x07FF0000 /* TX Frame Length (Bytes) */
338
339/* EMAC_MMC_CTL Masks */
340#define RSTC 0x00000001 /* Reset All Counters */
341#define CROLL 0x00000002 /* Counter Roll-Over Enable */
342#define CCOR 0x00000004 /* Counter Clear-On-Read Mode Enable */
343#define MMCE 0x00000008 /* Enable MMC Counter Operation */
344
345/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
346#define RX_OK_CNT 0x00000001 /* RX Frames Received With No Errors */
347#define RX_FCS_CNT 0x00000002 /* RX Frames W/Frame Check Sequence Errors */
348#define RX_ALIGN_CNT 0x00000004 /* RX Frames With Alignment Errors */
349#define RX_OCTET_CNT 0x00000008 /* RX Octets Received OK */
350#define RX_LOST_CNT 0x00000010 /* RX Frames Lost Due To Internal MAC RX Error */
351#define RX_UNI_CNT 0x00000020 /* Unicast RX Frames Received OK */
352#define RX_MULTI_CNT 0x00000040 /* Multicast RX Frames Received OK */
353#define RX_BROAD_CNT 0x00000080 /* Broadcast RX Frames Received OK */
354#define RX_IRL_CNT 0x00000100 /* RX Frames With In-Range Length Errors */
355#define RX_ORL_CNT 0x00000200 /* RX Frames With Out-Of-Range Length Errors */
356#define RX_LONG_CNT 0x00000400 /* RX Frames With Frame Too Long Errors */
357#define RX_MACCTL_CNT 0x00000800 /* MAC Control RX Frames Received */
358#define RX_OPCODE_CTL 0x00001000 /* Unsupported Op-Code RX Frames Received */
359#define RX_PAUSE_CNT 0x00002000 /* PAUSEMAC Control RX Frames Received */
360#define RX_ALLF_CNT 0x00004000 /* All RX Frames Received */
361#define RX_ALLO_CNT 0x00008000 /* All RX Octets Received */
362#define RX_TYPED_CNT 0x00010000 /* Typed RX Frames Received */
363#define RX_SHORT_CNT 0x00020000 /* RX Frame Fragments (< 64 Bytes) Received */
364#define RX_EQ64_CNT 0x00040000 /* 64-Byte RX Frames Received */
365#define RX_LT128_CNT 0x00080000 /* 65-127-Byte RX Frames Received */
366#define RX_LT256_CNT 0x00100000 /* 128-255-Byte RX Frames Received */
367#define RX_LT512_CNT 0x00200000 /* 256-511-Byte RX Frames Received */
368#define RX_LT1024_CNT 0x00400000 /* 512-1023-Byte RX Frames Received */
369#define RX_GE1024_CNT 0x00800000 /* 1024-Max-Byte RX Frames Received */
370
371/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks */
372
373#define TX_OK_CNT 0x00000001 /* TX Frames Sent OK */
374#define TX_SCOLL_CNT 0x00000002 /* TX Frames With Single Collisions */
375#define TX_MCOLL_CNT 0x00000004 /* TX Frames With Multiple Collisions */
376#define TX_OCTET_CNT 0x00000008 /* TX Octets Sent OK */
377#define TX_DEFER_CNT 0x00000010 /* TX Frames With Deferred Transmission */
378#define TX_LATE_CNT 0x00000020 /* TX Frames With Late Collisions */
379#define TX_ABORTC_CNT 0x00000040 /* TX Frames Aborted Due To Excess Collisions */
380#define TX_LOST_CNT 0x00000080 /* TX Frames Lost Due To Internal MAC TX Error */
381#define TX_CRS_CNT 0x00000100 /* TX Frames With Carrier Sense Errors */
382#define TX_UNI_CNT 0x00000200 /* Unicast TX Frames Sent */
383#define TX_MULTI_CNT 0x00000400 /* Multicast TX Frames Sent */
384#define TX_BROAD_CNT 0x00000800 /* Broadcast TX Frames Sent */
385#define TX_EXDEF_CTL 0x00001000 /* TX Frames With Excessive Deferral */
386#define TX_MACCTL_CNT 0x00002000 /* MAC Control TX Frames Sent */
387#define TX_ALLF_CNT 0x00004000 /* All TX Frames Sent */
388#define TX_ALLO_CNT 0x00008000 /* All TX Octets Sent */
389#define TX_EQ64_CNT 0x00010000 /* 64-Byte TX Frames Sent */
390#define TX_LT128_CNT 0x00020000 /* 65-127-Byte TX Frames Sent */
391#define TX_LT256_CNT 0x00040000 /* 128-255-Byte TX Frames Sent */
392#define TX_LT512_CNT 0x00080000 /* 256-511-Byte TX Frames Sent */
393#define TX_LT1024_CNT 0x00100000 /* 512-1023-Byte TX Frames Sent */
394#define TX_GE1024_CNT 0x00200000 /* 1024-Max-Byte TX Frames Sent */
395#define TX_ABORT_CNT 0x00400000 /* TX Frames Aborted */
396
397/* SDH Registers */
398
399#define SDH_PWR_CTL 0xFFC03900 /* SDH Power Control */
400#define SDH_CLK_CTL 0xFFC03904 /* SDH Clock Control */
401#define SDH_ARGUMENT 0xFFC03908 /* SDH Argument */
402#define SDH_COMMAND 0xFFC0390C /* SDH Command */
403#define SDH_RESP_CMD 0xFFC03910 /* SDH Response Command */
404#define SDH_RESPONSE0 0xFFC03914 /* SDH Response0 */
405#define SDH_RESPONSE1 0xFFC03918 /* SDH Response1 */
406#define SDH_RESPONSE2 0xFFC0391C /* SDH Response2 */
407#define SDH_RESPONSE3 0xFFC03920 /* SDH Response3 */
408#define SDH_DATA_TIMER 0xFFC03924 /* SDH Data Timer */
409#define SDH_DATA_LGTH 0xFFC03928 /* SDH Data Length */
410#define SDH_DATA_CTL 0xFFC0392C /* SDH Data Control */
411#define SDH_DATA_CNT 0xFFC03930 /* SDH Data Counter */
412#define SDH_STATUS 0xFFC03934 /* SDH Status */
413#define SDH_STATUS_CLR 0xFFC03938 /* SDH Status Clear */
414#define SDH_MASK0 0xFFC0393C /* SDH Interrupt0 Mask */
415#define SDH_MASK1 0xFFC03940 /* SDH Interrupt1 Mask */
416#define SDH_FIFO_CNT 0xFFC03948 /* SDH FIFO Counter */
417#define SDH_FIFO 0xFFC03980 /* SDH Data FIFO */
418#define SDH_E_STATUS 0xFFC039C0 /* SDH Exception Status */
419#define SDH_E_MASK 0xFFC039C4 /* SDH Exception Mask */
420#define SDH_CFG 0xFFC039C8 /* SDH Configuration */
421#define SDH_RD_WAIT_EN 0xFFC039CC /* SDH Read Wait Enable */
422#define SDH_PID0 0xFFC039D0 /* SDH Peripheral Identification0 */
423#define SDH_PID1 0xFFC039D4 /* SDH Peripheral Identification1 */
424#define SDH_PID2 0xFFC039D8 /* SDH Peripheral Identification2 */
425#define SDH_PID3 0xFFC039DC /* SDH Peripheral Identification3 */
426#define SDH_PID4 0xFFC039E0 /* SDH Peripheral Identification4 */
427#define SDH_PID5 0xFFC039E4 /* SDH Peripheral Identification5 */
428#define SDH_PID6 0xFFC039E8 /* SDH Peripheral Identification6 */
429#define SDH_PID7 0xFFC039EC /* SDH Peripheral Identification7 */
430
431/* Removable Storage Interface Registers */
432
433#define RSI_PWR_CONTROL 0xFFC03800 /* RSI Power Control Register */
434#define RSI_CLK_CONTROL 0xFFC03804 /* RSI Clock Control Register */
435#define RSI_ARGUMENT 0xFFC03808 /* RSI Argument Register */
436#define RSI_COMMAND 0xFFC0380C /* RSI Command Register */
437#define RSI_RESP_CMD 0xFFC03810 /* RSI Response Command Register */
438#define RSI_RESPONSE0 0xFFC03814 /* RSI Response Register */
439#define RSI_RESPONSE1 0xFFC03818 /* RSI Response Register */
440#define RSI_RESPONSE2 0xFFC0381C /* RSI Response Register */
441#define RSI_RESPONSE3 0xFFC03820 /* RSI Response Register */
442#define RSI_DATA_TIMER 0xFFC03824 /* RSI Data Timer Register */
443#define RSI_DATA_LGTH 0xFFC03828 /* RSI Data Length Register */
444#define RSI_DATA_CONTROL 0xFFC0382C /* RSI Data Control Register */
445#define RSI_DATA_CNT 0xFFC03830 /* RSI Data Counter Register */
446#define RSI_STATUS 0xFFC03834 /* RSI Status Register */
447#define RSI_STATUSCL 0xFFC03838 /* RSI Status Clear Register */
448#define RSI_MASK0 0xFFC0383C /* RSI Interrupt 0 Mask Register */
449#define RSI_MASK1 0xFFC03840 /* RSI Interrupt 1 Mask Register */
450#define RSI_FIFO_CNT 0xFFC03848 /* RSI FIFO Counter Register */
451#define RSI_CEATA_CONTROL 0xFFC0384C /* RSI CEATA Register */
452#define RSI_FIFO 0xFFC03880 /* RSI Data FIFO Register */
453#define RSI_ESTAT 0xFFC038C0 /* RSI Exception Status Register */
454#define RSI_EMASK 0xFFC038C4 /* RSI Exception Mask Register */
455#define RSI_CONFIG 0xFFC038C8 /* RSI Configuration Register */
456#define RSI_RD_WAIT_EN 0xFFC038CC /* RSI Read Wait Enable Register */
457#define RSI_PID0 0xFFC03FE0 /* RSI Peripheral ID Register 0 */
458#define RSI_PID1 0xFFC03FE4 /* RSI Peripheral ID Register 1 */
459#define RSI_PID2 0xFFC03FE8 /* RSI Peripheral ID Register 2 */
460#define RSI_PID3 0xFFC03FEC /* RSI Peripheral ID Register 3 */
461#define RSI_PID4 0xFFC03FF0 /* RSI Peripheral ID Register 4 */
462#define RSI_PID5 0xFFC03FF4 /* RSI Peripheral ID Register 5 */
463#define RSI_PID6 0xFFC03FF8 /* RSI Peripheral ID Register 6 */
464#define RSI_PID7 0xFFC03FFC /* RSI Peripheral ID Register 7 */
465 12
466/* PTP TSYNC Registers */ 13/* PTP TSYNC Registers */
467 14
@@ -489,141 +36,6 @@
489#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */ 36#define EMAC_PTP_PPS_STARTHI 0xFFC030F4 /* PPS Start Time High */
490#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */ 37#define EMAC_PTP_PPS_PERIOD 0xFFC030F8 /* PPS Count Register */
491 38
492/* ********************************************************** */
493/* SINGLE BIT MACRO PAIRS (bit mask and negated one) */
494/* and MULTI BIT READ MACROS */
495/* ********************************************************** */
496
497/* Bit masks for SDH_COMMAND */
498
499#define CMD_IDX 0x3f /* Command Index */
500#define CMD_RSP 0x40 /* Response */
501#define CMD_L_RSP 0x80 /* Long Response */
502#define CMD_INT_E 0x100 /* Command Interrupt */
503#define CMD_PEND_E 0x200 /* Command Pending */
504#define CMD_E 0x400 /* Command Enable */
505
506/* Bit masks for SDH_PWR_CTL */
507
508#define PWR_ON 0x3 /* Power On */
509#if 0
510#define TBD 0x3c /* TBD */
511#endif
512#define SD_CMD_OD 0x40 /* Open Drain Output */
513#define ROD_CTL 0x80 /* Rod Control */
514
515/* Bit masks for SDH_CLK_CTL */
516
517#define CLKDIV 0xff /* MC_CLK Divisor */
518#define CLK_E 0x100 /* MC_CLK Bus Clock Enable */
519#define PWR_SV_E 0x200 /* Power Save Enable */
520#define CLKDIV_BYPASS 0x400 /* Bypass Divisor */
521#define WIDE_BUS 0x800 /* Wide Bus Mode Enable */
522
523/* Bit masks for SDH_RESP_CMD */
524
525#define RESP_CMD 0x3f /* Response Command */
526
527/* Bit masks for SDH_DATA_CTL */
528
529#define DTX_E 0x1 /* Data Transfer Enable */
530#define DTX_DIR 0x2 /* Data Transfer Direction */
531#define DTX_MODE 0x4 /* Data Transfer Mode */
532#define DTX_DMA_E 0x8 /* Data Transfer DMA Enable */
533#define DTX_BLK_LGTH 0xf0 /* Data Transfer Block Length */
534
535/* Bit masks for SDH_STATUS */
536
537#define CMD_CRC_FAIL 0x1 /* CMD CRC Fail */
538#define DAT_CRC_FAIL 0x2 /* Data CRC Fail */
539#define CMD_TIME_OUT 0x4 /* CMD Time Out */
540#define DAT_TIME_OUT 0x8 /* Data Time Out */
541#define TX_UNDERRUN 0x10 /* Transmit Underrun */
542#define RX_OVERRUN 0x20 /* Receive Overrun */
543#define CMD_RESP_END 0x40 /* CMD Response End */
544#define CMD_SENT 0x80 /* CMD Sent */
545#define DAT_END 0x100 /* Data End */
546#define START_BIT_ERR 0x200 /* Start Bit Error */
547#define DAT_BLK_END 0x400 /* Data Block End */
548#define CMD_ACT 0x800 /* CMD Active */
549#define TX_ACT 0x1000 /* Transmit Active */
550#define RX_ACT 0x2000 /* Receive Active */
551#define TX_FIFO_STAT 0x4000 /* Transmit FIFO Status */
552#define RX_FIFO_STAT 0x8000 /* Receive FIFO Status */
553#define TX_FIFO_FULL 0x10000 /* Transmit FIFO Full */
554#define RX_FIFO_FULL 0x20000 /* Receive FIFO Full */
555#define TX_FIFO_ZERO 0x40000 /* Transmit FIFO Empty */
556#define RX_DAT_ZERO 0x80000 /* Receive FIFO Empty */
557#define TX_DAT_RDY 0x100000 /* Transmit Data Available */
558#define RX_FIFO_RDY 0x200000 /* Receive Data Available */
559
560/* Bit masks for SDH_STATUS_CLR */
561
562#define CMD_CRC_FAIL_STAT 0x1 /* CMD CRC Fail Status */
563#define DAT_CRC_FAIL_STAT 0x2 /* Data CRC Fail Status */
564#define CMD_TIMEOUT_STAT 0x4 /* CMD Time Out Status */
565#define DAT_TIMEOUT_STAT 0x8 /* Data Time Out status */
566#define TX_UNDERRUN_STAT 0x10 /* Transmit Underrun Status */
567#define RX_OVERRUN_STAT 0x20 /* Receive Overrun Status */
568#define CMD_RESP_END_STAT 0x40 /* CMD Response End Status */
569#define CMD_SENT_STAT 0x80 /* CMD Sent Status */
570#define DAT_END_STAT 0x100 /* Data End Status */
571#define START_BIT_ERR_STAT 0x200 /* Start Bit Error Status */
572#define DAT_BLK_END_STAT 0x400 /* Data Block End Status */
573
574/* Bit masks for SDH_MASK0 */
575
576#define CMD_CRC_FAIL_MASK 0x1 /* CMD CRC Fail Mask */
577#define DAT_CRC_FAIL_MASK 0x2 /* Data CRC Fail Mask */
578#define CMD_TIMEOUT_MASK 0x4 /* CMD Time Out Mask */
579#define DAT_TIMEOUT_MASK 0x8 /* Data Time Out Mask */
580#define TX_UNDERRUN_MASK 0x10 /* Transmit Underrun Mask */
581#define RX_OVERRUN_MASK 0x20 /* Receive Overrun Mask */
582#define CMD_RESP_END_MASK 0x40 /* CMD Response End Mask */
583#define CMD_SENT_MASK 0x80 /* CMD Sent Mask */
584#define DAT_END_MASK 0x100 /* Data End Mask */
585#define START_BIT_ERR_MASK 0x200 /* Start Bit Error Mask */
586#define DAT_BLK_END_MASK 0x400 /* Data Block End Mask */
587#define CMD_ACT_MASK 0x800 /* CMD Active Mask */
588#define TX_ACT_MASK 0x1000 /* Transmit Active Mask */
589#define RX_ACT_MASK 0x2000 /* Receive Active Mask */
590#define TX_FIFO_STAT_MASK 0x4000 /* Transmit FIFO Status Mask */
591#define RX_FIFO_STAT_MASK 0x8000 /* Receive FIFO Status Mask */
592#define TX_FIFO_FULL_MASK 0x10000 /* Transmit FIFO Full Mask */
593#define RX_FIFO_FULL_MASK 0x20000 /* Receive FIFO Full Mask */
594#define TX_FIFO_ZERO_MASK 0x40000 /* Transmit FIFO Empty Mask */
595#define RX_DAT_ZERO_MASK 0x80000 /* Receive FIFO Empty Mask */
596#define TX_DAT_RDY_MASK 0x100000 /* Transmit Data Available Mask */
597#define RX_FIFO_RDY_MASK 0x200000 /* Receive Data Available Mask */
598
599/* Bit masks for SDH_FIFO_CNT */
600
601#define FIFO_COUNT 0x7fff /* FIFO Count */
602
603/* Bit masks for SDH_E_STATUS */
604
605#define SDIO_INT_DET 0x2 /* SDIO Int Detected */
606#define SD_CARD_DET 0x10 /* SD Card Detect */
607
608/* Bit masks for SDH_E_MASK */
609
610#define SDIO_MSK 0x2 /* Mask SDIO Int Detected */
611#define SCD_MSK 0x40 /* Mask Card Detect */
612
613/* Bit masks for SDH_CFG */
614
615#define CLKS_EN 0x1 /* Clocks Enable */
616#define SD4E 0x4 /* SDIO 4-Bit Enable */
617#define MWE 0x8 /* Moving Window Enable */
618#define SD_RST 0x10 /* SDMMC Reset */
619#define PUP_SDDAT 0x20 /* Pull-up SD_DAT */
620#define PUP_SDDAT3 0x40 /* Pull-up SD_DAT3 */
621#define PD_SDDAT3 0x80 /* Pull-down SD_DAT3 */
622
623/* Bit masks for SDH_RD_WAIT_EN */
624
625#define RWR 0x1 /* Read Wait Request */
626
627/* Bit masks for EMAC_PTP_CTL */ 39/* Bit masks for EMAC_PTP_CTL */
628 40
629#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */ 41#define PTP_EN 0x1 /* Enable the PTP_TSYNC module */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-30 18:33:09 -0500