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authorPaul Mundt <lethal@linux-sh.org>2006-09-27 05:22:53 -0400
committerPaul Mundt <lethal@linux-sh.org>2006-09-27 05:22:53 -0400
commit315bb96824149614efe4844ded077a13fc908880 (patch)
tree3a8db24ec8554d8e56b1460d85cc81b34299b0d7
parenta6a31139897a5e539efe7ad3b7bd351fa9673ce8 (diff)
sh: CPU flags in AT_HWCAP in ELF auxvt.
Encode processor flags in AT_HWCAP in the ELF auxiliary vector. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c8
-rw-r--r--include/asm-sh/cpu-features.h15
-rw-r--r--include/asm-sh/elf.h10
-rw-r--r--include/asm-sh/processor.h12
4 files changed, 27 insertions, 18 deletions
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6e8a2b5268e8..0e65aa6ddcaa 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -76,6 +76,7 @@ int __init detect_cpu_and_cache_system(void)
76 cpu_data->type = CPU_SH73180; 76 cpu_data->type = CPU_SH73180;
77 cpu_data->icache.ways = 4; 77 cpu_data->icache.ways = 4;
78 cpu_data->dcache.ways = 4; 78 cpu_data->dcache.ways = 4;
79 cpu_data->flags |= CPU_HAS_LLSC;
79 break; 80 break;
80 case 0x2001: 81 case 0x2001:
81 case 0x2004: 82 case 0x2004:
@@ -83,7 +84,7 @@ int __init detect_cpu_and_cache_system(void)
83 cpu_data->icache.ways = 4; 84 cpu_data->icache.ways = 4;
84 cpu_data->dcache.ways = 4; 85 cpu_data->dcache.ways = 4;
85 86
86 cpu_data->flags |= CPU_HAS_FPU; 87 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_LLSC;
87 break; 88 break;
88 case 0x2006: 89 case 0x2006:
89 case 0x200A: 90 case 0x200A:
@@ -95,13 +96,15 @@ int __init detect_cpu_and_cache_system(void)
95 cpu_data->icache.ways = 4; 96 cpu_data->icache.ways = 4;
96 cpu_data->dcache.ways = 4; 97 cpu_data->dcache.ways = 4;
97 98
98 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER; 99 cpu_data->flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
100 CPU_HAS_LLSC;
99 break; 101 break;
100 case 0x3000: 102 case 0x3000:
101 case 0x3003: 103 case 0x3003:
102 cpu_data->type = CPU_SH7343; 104 cpu_data->type = CPU_SH7343;
103 cpu_data->icache.ways = 4; 105 cpu_data->icache.ways = 4;
104 cpu_data->dcache.ways = 4; 106 cpu_data->dcache.ways = 4;
107 cpu_data->flags |= CPU_HAS_LLSC;
105 break; 108 break;
106 case 0x8000: 109 case 0x8000:
107 cpu_data->type = CPU_ST40RA; 110 cpu_data->type = CPU_ST40RA;
@@ -180,4 +183,3 @@ int __init detect_cpu_and_cache_system(void)
180 183
181 return 0; 184 return 0;
182} 185}
183
diff --git a/include/asm-sh/cpu-features.h b/include/asm-sh/cpu-features.h
new file mode 100644
index 000000000000..e398947ec01d
--- /dev/null
+++ b/include/asm-sh/cpu-features.h
@@ -0,0 +1,15 @@
1#ifndef __ASM_SH_CPU_FEATURES_H
2#define __ASM_SH_CPU_FEATURES_H
3
4/*
5 * Processor flags
6 */
7#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
8#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
9#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
10#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
11#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
12#define CPU_HAS_PTEA 0x0020 /* PTEA register */
13#define CPU_HAS_LLSC 0x0040 /* movli.l/movco.l */
14
15#endif /* __ASM_SH_CPU_FEATURES_H */
diff --git a/include/asm-sh/elf.h b/include/asm-sh/elf.h
index 1b63dfeea4f2..cc8e5e767345 100644
--- a/include/asm-sh/elf.h
+++ b/include/asm-sh/elf.h
@@ -1,6 +1,11 @@
1#ifndef __ASM_SH_ELF_H 1#ifndef __ASM_SH_ELF_H
2#define __ASM_SH_ELF_H 2#define __ASM_SH_ELF_H
3 3
4#include <asm/processor.h>
5#include <asm/auxvec.h>
6#include <asm/ptrace.h>
7#include <asm/user.h>
8
4/* SH relocation types */ 9/* SH relocation types */
5#define R_SH_NONE 0 10#define R_SH_NONE 0
6#define R_SH_DIR32 1 11#define R_SH_DIR32 1
@@ -46,9 +51,6 @@
46 * ELF register definitions.. 51 * ELF register definitions..
47 */ 52 */
48 53
49#include <asm/ptrace.h>
50#include <asm/user.h>
51
52typedef unsigned long elf_greg_t; 54typedef unsigned long elf_greg_t;
53 55
54#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t)) 56#define ELF_NGREG (sizeof (struct pt_regs) / sizeof(elf_greg_t))
@@ -91,7 +93,7 @@ typedef struct user_fpu_struct elf_fpregset_t;
91 instruction set this CPU supports. This could be done in user space, 93 instruction set this CPU supports. This could be done in user space,
92 but it's not easy, and we've already done it here. */ 94 but it's not easy, and we've already done it here. */
93 95
94#define ELF_HWCAP (0) 96#define ELF_HWCAP (boot_cpu_data.flags)
95 97
96/* This yields a string that ld.so will use to load implementation 98/* This yields a string that ld.so will use to load implementation
97 specific libraries for optimization. This is more specific in 99 specific libraries for optimization. This is more specific in
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 3b3ef4f2bf31..bdd472705546 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -14,6 +14,7 @@
14#include <asm/types.h> 14#include <asm/types.h>
15#include <asm/cache.h> 15#include <asm/cache.h>
16#include <asm/ptrace.h> 16#include <asm/ptrace.h>
17#include <asm/cpu-features.h>
17 18
18/* 19/*
19 * Default implementation of macro that returns current 20 * Default implementation of macro that returns current
@@ -127,17 +128,6 @@ union sh_fpu_union {
127 struct sh_fpu_soft_struct soft; 128 struct sh_fpu_soft_struct soft;
128}; 129};
129 130
130/*
131 * Processor flags
132 */
133
134#define CPU_HAS_FPU 0x0001 /* Hardware FPU support */
135#define CPU_HAS_P2_FLUSH_BUG 0x0002 /* Need to flush the cache in P2 area */
136#define CPU_HAS_MMU_PAGE_ASSOC 0x0004 /* SH3: TLB way selection bit support */
137#define CPU_HAS_DSP 0x0008 /* SH-DSP: DSP support */
138#define CPU_HAS_PERF_COUNTER 0x0010 /* Hardware performance counters */
139#define CPU_HAS_PTEA 0x0020 /* PTEA register */
140
141struct thread_struct { 131struct thread_struct {
142 unsigned long sp; 132 unsigned long sp;
143 unsigned long pc; 133 unsigned long pc;