drm/radeon: add rv740 drm support.

This adds drm support for the RV740 family of chips to the r600 support code.

Signed-off-by: Dave Airlie <airlied@redhat.com>

3 files changed, 41 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/r600_cp.c b/drivers/gpu/drm/radeon/r600_cp.c
index bc9d09dfa8e7..aa4eee4b7f3a 100644
--- a/drivers/gpu/drm/radeon/r600_cp.c
+++ b/drivers/gpu/drm/radeon/r600_cp.c
@@ -489,15 +489,16 @@ static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
                         RADEON_WRITE(R600_CP_ME_RAM_DATA, RV770_cp_microcode[i]);
                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
 
-        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730)) {
+        } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV730) ||
+                   ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)) {
                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
-                DRM_INFO("Loading RV730 PFP Microcode\n");
+                DRM_INFO("Loading RV730/RV740 PFP Microcode\n");
                 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
                         RADEON_WRITE(R600_CP_PFP_UCODE_DATA, RV730_pfp_microcode[i]);
                 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
 
                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
-                DRM_INFO("Loading RV730 CP Microcode\n");
+                DRM_INFO("Loading RV730/RV740 CP Microcode\n");
                 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
                         RADEON_WRITE(R600_CP_ME_RAM_DATA, RV730_cp_microcode[i]);
                 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
@@ -1324,6 +1325,10 @@ static void r700_gfx_init(struct drm_device *dev,
                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+                if (dev_priv->r600_sx_max_export_pos_size > 16) {
+                        dev_priv->r600_sx_max_export_pos_size -= 16;
+                        dev_priv->r600_sx_max_export_smx_size += 16;
+                }
                 break;
         case CHIP_RV710:
                 dev_priv->r600_max_pipes = 2;
@@ -1345,6 +1350,31 @@ static void r700_gfx_init(struct drm_device *dev,
                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
                 break;
+        case CHIP_RV740:
+                dev_priv->r600_max_pipes = 4;
+                dev_priv->r600_max_tile_pipes = 4;
+                dev_priv->r600_max_simds = 8;
+                dev_priv->r600_max_backends = 4;
+                dev_priv->r600_max_gprs = 256;
+                dev_priv->r600_max_threads = 248;
+                dev_priv->r600_max_stack_entries = 512;
+                dev_priv->r600_max_hw_contexts = 8;
+                dev_priv->r600_max_gs_threads = 16 * 2;
+                dev_priv->r600_sx_max_export_size = 256;
+                dev_priv->r600_sx_max_export_pos_size = 32;
+                dev_priv->r600_sx_max_export_smx_size = 224;
+                dev_priv->r600_sq_num_cf_insts = 2;
+
+                dev_priv->r700_sx_num_of_sets = 7;
+                dev_priv->r700_sc_prim_fifo_size = 0x100;
+                dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
+                dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
+
+                if (dev_priv->r600_sx_max_export_pos_size > 16) {
+                        dev_priv->r600_sx_max_export_pos_size -= 16;
+                        dev_priv->r600_sx_max_export_smx_size += 16;
+                }
+                break;
         default:
                 break;
         }
@@ -1493,6 +1523,7 @@ static void r700_gfx_init(struct drm_device *dev,
                 break;
         case CHIP_RV730:
         case CHIP_RV710:
+        case CHIP_RV740:
         default:
                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
                 break;
@@ -1569,6 +1600,7 @@ static void r700_gfx_init(struct drm_device *dev,
         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
         case CHIP_RV770:
         case CHIP_RV730:
+        case CHIP_RV740:
                 gs_prim_buffer_depth = 384;
                 break;
         case CHIP_RV710:
diff --git a/drivers/gpu/drm/radeon/radeon_drv.h b/drivers/gpu/drm/radeon/radeon_drv.h
index 8071d965f142..e266e5f8dc26 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.h
+++ b/drivers/gpu/drm/radeon/radeon_drv.h
@@ -146,6 +146,7 @@ enum radeon_family {
         CHIP_RV770,
         CHIP_RV730,
         CHIP_RV710,
+        CHIP_RV740,
         CHIP_LAST,
 };
 
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 8b4c80cdd277..c7a1a8dc5ea4 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -254,6 +254,11 @@
         {0x1002, 0x940A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x940B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x940F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R600|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x94A0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x94A1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x94B1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x94B3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x94B5, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV740|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x9441, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x9442, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV770|RADEON_NEW_MEMMAP}, \