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authorIngo Molnar <mingo@elte.hu>2008-07-09 02:02:54 -0400
committerIngo Molnar <mingo@elte.hu>2008-07-09 02:18:41 -0400
commit26e9e57b106445bbd8c965985e4e8af5293ae005 (patch)
treeeb8102e8ac05e5a31ad5c1ef2a8e254a3f3c312a
parente407dffd17dcb592e1605a2b3dbbb81f9f3cbc21 (diff)
x86, uv: build fix #2 for "x86, uv: update x86 mmr list for SGI uv"
fix: In file included from arch/x86/kernel/tlb_uv.c:14: include/asm/uv/uv_mmrs.h:986: error: redefinition of ‘union uvh_rh_gam_cfg_overlay_config_mmr_u’ include/asm/uv/uv_mmrs.h:988: error: redefinition of ‘struct uvh_rh_gam_cfg_overlay_config_mmr_s’ include/asm/uv/uv_mmrs.h:1064: error: redefinition of ‘union uvh_rh_gam_mmioh_overlay_config_mmr_u’ include/asm/uv/uv_mmrs.h:1066: error: redefinition of ‘struct uvh_rh_gam_mmioh_overlay_config_mmr_s’ caused by another duplicate section (cut & paste error) in commit 5d061e397db1 "x86, uv: update x86 mmr list for SGI uv". Signed-off-by: Ingo Molnar <mingo@elte.hu>
-rw-r--r--include/asm-x86/uv/uv_mmrs.h26
1 files changed, 0 insertions, 26 deletions
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h
index a8a1ad5c764f..151fd7fcb809 100644
--- a/include/asm-x86/uv/uv_mmrs.h
+++ b/include/asm-x86/uv/uv_mmrs.h
@@ -1028,32 +1028,6 @@ union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1028}; 1028};
1029 1029
1030/* ========================================================================= */ 1030/* ========================================================================= */
1031/* UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR */
1032/* ========================================================================= */
1033#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR 0x1600030UL
1034
1035#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_SHFT 30
1036#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_BASE_MASK 0x00003fffc0000000UL
1037#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_SHFT 46
1038#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_M_IO_MASK 0x000fc00000000000UL
1039#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_SHFT 52
1040#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_N_IO_MASK 0x00f0000000000000UL
1041#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_SHFT 63
1042#define UVH_RH_GAM_MMIOH_OVERLAY_CONFIG_MMR_ENABLE_MASK 0x8000000000000000UL
1043
1044union uvh_rh_gam_mmioh_overlay_config_mmr_u {
1045 unsigned long v;
1046 struct uvh_rh_gam_mmioh_overlay_config_mmr_s {
1047 unsigned long rsvd_0_29: 30; /* */
1048 unsigned long base : 16; /* RW */
1049 unsigned long m_io : 6; /* RW */
1050 unsigned long n_io : 4; /* RW */
1051 unsigned long rsvd_56_62: 7; /* */
1052 unsigned long enable : 1; /* RW */
1053 } s;
1054};
1055
1056/* ========================================================================= */
1057/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */ 1031/* UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR */
1058/* ========================================================================= */ 1032/* ========================================================================= */
1059#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL 1033#define UVH_RH_GAM_MMR_OVERLAY_CONFIG_MMR 0x1600028UL