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authorDavid Brownell <david-b@pacbell.net>2005-11-23 18:45:37 -0500
committerLinus Torvalds <torvalds@g5.osdl.org>2005-11-24 02:04:28 -0500
commit188075211cc75a31190de4a19a084e3d83ee1c89 (patch)
tree71649a9b269580f460ad76de4b061741c4a22e23
parentabcc94480634f6fe9fc29b821261e8162c87ddd2 (diff)
[PATCH] USB: EHCI updates split init/reinit logic for resume
Moving the PCI-specific parts of the EHCI driver into their own file created a few issues ... notably on resume paths which (like swsusp) require re-initializing the controller. This patch: - Splits the EHCI startup code into run-once HCD setup code and separate "init the hardware" reinit code. (That reinit code is a superset of the "early usb handoff" code.) - Then it makes the PCI init code run both, and the resume code only run the reinit code. - It also removes needless pci wrappers around EHCI start/stop methods. - Removes a byteswap issue that would be seen on big-endian hardware. The HCD glue still doesn't actually provide a good way to do all this run-one init stuff in one place though. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
-rw-r--r--drivers/usb/host/ehci-hcd.c157
-rw-r--r--drivers/usb/host/ehci-pci.c166
2 files changed, 162 insertions, 161 deletions
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index f15144e96e14..29f52a44b928 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -411,50 +411,39 @@ static void ehci_stop (struct usb_hcd *hcd)
411 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status)); 411 dbg_status (ehci, "ehci_stop completed", readl (&ehci->regs->status));
412} 412}
413 413
414static int ehci_run (struct usb_hcd *hcd) 414/* one-time init, only for memory state */
415static int ehci_init(struct usb_hcd *hcd)
415{ 416{
416 struct ehci_hcd *ehci = hcd_to_ehci (hcd); 417 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
417 u32 temp; 418 u32 temp;
418 int retval; 419 int retval;
419 u32 hcc_params; 420 u32 hcc_params;
420 int first; 421
421 422 spin_lock_init(&ehci->lock);
422 /* skip some things on restart paths */ 423
423 first = (ehci->watchdog.data == 0); 424 init_timer(&ehci->watchdog);
424 if (first) { 425 ehci->watchdog.function = ehci_watchdog;
425 init_timer (&ehci->watchdog); 426 ehci->watchdog.data = (unsigned long) ehci;
426 ehci->watchdog.function = ehci_watchdog;
427 ehci->watchdog.data = (unsigned long) ehci;
428 }
429 427
430 /* 428 /*
431 * hw default: 1K periodic list heads, one per frame. 429 * hw default: 1K periodic list heads, one per frame.
432 * periodic_size can shrink by USBCMD update if hcc_params allows. 430 * periodic_size can shrink by USBCMD update if hcc_params allows.
433 */ 431 */
434 ehci->periodic_size = DEFAULT_I_TDPS; 432 ehci->periodic_size = DEFAULT_I_TDPS;
435 if (first && (retval = ehci_mem_init (ehci, GFP_KERNEL)) < 0) 433 if ((retval = ehci_mem_init(ehci, GFP_KERNEL)) < 0)
436 return retval; 434 return retval;
437 435
438 /* controllers may cache some of the periodic schedule ... */ 436 /* controllers may cache some of the periodic schedule ... */
439 hcc_params = readl (&ehci->caps->hcc_params); 437 hcc_params = readl(&ehci->caps->hcc_params);
440 if (HCC_ISOC_CACHE (hcc_params)) // full frame cache 438 if (HCC_ISOC_CACHE(hcc_params)) // full frame cache
441 ehci->i_thresh = 8; 439 ehci->i_thresh = 8;
442 else // N microframes cached 440 else // N microframes cached
443 ehci->i_thresh = 2 + HCC_ISOC_THRES (hcc_params); 441 ehci->i_thresh = 2 + HCC_ISOC_THRES(hcc_params);
444 442
445 ehci->reclaim = NULL; 443 ehci->reclaim = NULL;
446 ehci->reclaim_ready = 0; 444 ehci->reclaim_ready = 0;
447 ehci->next_uframe = -1; 445 ehci->next_uframe = -1;
448 446
449 /* controller state: unknown --> reset */
450
451 /* EHCI spec section 4.1 */
452 if ((retval = ehci_reset (ehci)) != 0) {
453 ehci_mem_cleanup (ehci);
454 return retval;
455 }
456 writel (ehci->periodic_dma, &ehci->regs->frame_list);
457
458 /* 447 /*
459 * dedicate a qh for the async ring head, since we couldn't unlink 448 * dedicate a qh for the async ring head, since we couldn't unlink
460 * a 'real' qh without stopping the async schedule [4.8]. use it 449 * a 'real' qh without stopping the async schedule [4.8]. use it
@@ -462,37 +451,13 @@ static int ehci_run (struct usb_hcd *hcd)
462 * its dummy is used in hw_alt_next of many tds, to prevent the qh 451 * its dummy is used in hw_alt_next of many tds, to prevent the qh
463 * from automatically advancing to the next td after short reads. 452 * from automatically advancing to the next td after short reads.
464 */ 453 */
465 if (first) { 454 ehci->async->qh_next.qh = NULL;
466 ehci->async->qh_next.qh = NULL; 455 ehci->async->hw_next = QH_NEXT(ehci->async->qh_dma);
467 ehci->async->hw_next = QH_NEXT (ehci->async->qh_dma); 456 ehci->async->hw_info1 = cpu_to_le32(QH_HEAD);
468 ehci->async->hw_info1 = cpu_to_le32 (QH_HEAD); 457 ehci->async->hw_token = cpu_to_le32(QTD_STS_HALT);
469 ehci->async->hw_token = cpu_to_le32 (QTD_STS_HALT); 458 ehci->async->hw_qtd_next = EHCI_LIST_END;
470 ehci->async->hw_qtd_next = EHCI_LIST_END; 459 ehci->async->qh_state = QH_STATE_LINKED;
471 ehci->async->qh_state = QH_STATE_LINKED; 460 ehci->async->hw_alt_next = QTD_NEXT(ehci->async->dummy->qtd_dma);
472 ehci->async->hw_alt_next = QTD_NEXT (ehci->async->dummy->qtd_dma);
473 }
474 writel ((u32)ehci->async->qh_dma, &ehci->regs->async_next);
475
476 /*
477 * hcc_params controls whether ehci->regs->segment must (!!!)
478 * be used; it constrains QH/ITD/SITD and QTD locations.
479 * pci_pool consistent memory always uses segment zero.
480 * streaming mappings for I/O buffers, like pci_map_single(),
481 * can return segments above 4GB, if the device allows.
482 *
483 * NOTE: the dma mask is visible through dma_supported(), so
484 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
485 * Scsi_Host.highmem_io, and so forth. It's readonly to all
486 * host side drivers though.
487 */
488 if (HCC_64BIT_ADDR (hcc_params)) {
489 writel (0, &ehci->regs->segment);
490#if 0
491// this is deeply broken on almost all architectures
492 if (!dma_set_mask (hcd->self.controller, DMA_64BIT_MASK))
493 ehci_info (ehci, "enabled 64bit DMA\n");
494#endif
495 }
496 461
497 /* clear interrupt enables, set irq latency */ 462 /* clear interrupt enables, set irq latency */
498 if (log2_irq_thresh < 0 || log2_irq_thresh > 6) 463 if (log2_irq_thresh < 0 || log2_irq_thresh > 6)
@@ -507,13 +472,13 @@ static int ehci_run (struct usb_hcd *hcd)
507 * make problems: throughput reduction (!), data errors... 472 * make problems: throughput reduction (!), data errors...
508 */ 473 */
509 if (park) { 474 if (park) {
510 park = min (park, (unsigned) 3); 475 park = min(park, (unsigned) 3);
511 temp |= CMD_PARK; 476 temp |= CMD_PARK;
512 temp |= park << 8; 477 temp |= park << 8;
513 } 478 }
514 ehci_info (ehci, "park %d\n", park); 479 ehci_dbg(ehci, "park %d\n", park);
515 } 480 }
516 if (HCC_PGM_FRAMELISTLEN (hcc_params)) { 481 if (HCC_PGM_FRAMELISTLEN(hcc_params)) {
517 /* periodic schedule size can be smaller than default */ 482 /* periodic schedule size can be smaller than default */
518 temp &= ~(3 << 2); 483 temp &= ~(3 << 2);
519 temp |= (EHCI_TUNE_FLS << 2); 484 temp |= (EHCI_TUNE_FLS << 2);
@@ -521,16 +486,63 @@ static int ehci_run (struct usb_hcd *hcd)
521 case 0: ehci->periodic_size = 1024; break; 486 case 0: ehci->periodic_size = 1024; break;
522 case 1: ehci->periodic_size = 512; break; 487 case 1: ehci->periodic_size = 512; break;
523 case 2: ehci->periodic_size = 256; break; 488 case 2: ehci->periodic_size = 256; break;
524 default: BUG (); 489 default: BUG();
525 } 490 }
526 } 491 }
492 ehci->command = temp;
493
494 ehci->reboot_notifier.notifier_call = ehci_reboot;
495 register_reboot_notifier(&ehci->reboot_notifier);
496
497 return 0;
498}
499
500/* start HC running; it's halted, ehci_init() has been run (once) */
501static int ehci_run (struct usb_hcd *hcd)
502{
503 struct ehci_hcd *ehci = hcd_to_ehci (hcd);
504 int retval;
505 u32 temp;
506 u32 hcc_params;
507
508 /* EHCI spec section 4.1 */
509 if ((retval = ehci_reset(ehci)) != 0) {
510 unregister_reboot_notifier(&ehci->reboot_notifier);
511 ehci_mem_cleanup(ehci);
512 return retval;
513 }
514 writel(ehci->periodic_dma, &ehci->regs->frame_list);
515 writel((u32)ehci->async->qh_dma, &ehci->regs->async_next);
516
517 /*
518 * hcc_params controls whether ehci->regs->segment must (!!!)
519 * be used; it constrains QH/ITD/SITD and QTD locations.
520 * pci_pool consistent memory always uses segment zero.
521 * streaming mappings for I/O buffers, like pci_map_single(),
522 * can return segments above 4GB, if the device allows.
523 *
524 * NOTE: the dma mask is visible through dma_supported(), so
525 * drivers can pass this info along ... like NETIF_F_HIGHDMA,
526 * Scsi_Host.highmem_io, and so forth. It's readonly to all
527 * host side drivers though.
528 */
529 hcc_params = readl(&ehci->caps->hcc_params);
530 if (HCC_64BIT_ADDR(hcc_params)) {
531 writel(0, &ehci->regs->segment);
532#if 0
533// this is deeply broken on almost all architectures
534 if (!dma_set_mask(hcd->self.controller, DMA_64BIT_MASK))
535 ehci_info(ehci, "enabled 64bit DMA\n");
536#endif
537 }
538
539
527 // Philips, Intel, and maybe others need CMD_RUN before the 540 // Philips, Intel, and maybe others need CMD_RUN before the
528 // root hub will detect new devices (why?); NEC doesn't 541 // root hub will detect new devices (why?); NEC doesn't
529 temp |= CMD_RUN; 542 ehci->command &= ~(CMD_LRESET|CMD_IAAD|CMD_PSE|CMD_ASE|CMD_RESET);
530 writel (temp, &ehci->regs->command); 543 ehci->command |= CMD_RUN;
531 dbg_cmd (ehci, "init", temp); 544 writel (ehci->command, &ehci->regs->command);
532 545 dbg_cmd (ehci, "init", ehci->command);
533 /* set async sleep time = 10 us ... ? */
534 546
535 /* 547 /*
536 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices 548 * Start, enabling full USB 2.0 functionality ... usb 1.1 devices
@@ -538,26 +550,23 @@ static int ehci_run (struct usb_hcd *hcd)
538 * involved with the root hub. (Except where one is integrated, 550 * involved with the root hub. (Except where one is integrated,
539 * and there's no companion controller unless maybe for USB OTG.) 551 * and there's no companion controller unless maybe for USB OTG.)
540 */ 552 */
541 if (first) {
542 ehci->reboot_notifier.notifier_call = ehci_reboot;
543 register_reboot_notifier (&ehci->reboot_notifier);
544 }
545
546 hcd->state = HC_STATE_RUNNING; 553 hcd->state = HC_STATE_RUNNING;
547 writel (FLAG_CF, &ehci->regs->configured_flag); 554 writel (FLAG_CF, &ehci->regs->configured_flag);
548 readl (&ehci->regs->command); /* unblock posted write */ 555 readl (&ehci->regs->command); /* unblock posted writes */
549 556
550 temp = HC_VERSION(readl (&ehci->caps->hc_capbase)); 557 temp = HC_VERSION(readl (&ehci->caps->hc_capbase));
551 ehci_info (ehci, 558 ehci_info (ehci,
552 "USB %x.%x %s, EHCI %x.%02x, driver %s\n", 559 "USB %x.%x started, EHCI %x.%02x, driver %s\n",
553 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f), 560 ((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
554 first ? "initialized" : "restarted",
555 temp >> 8, temp & 0xff, DRIVER_VERSION); 561 temp >> 8, temp & 0xff, DRIVER_VERSION);
556 562
557 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */ 563 writel (INTR_MASK, &ehci->regs->intr_enable); /* Turn On Interrupts */
558 564
559 if (first) 565 /* GRR this is run-once init(), being done every time the HC starts.
560 create_debug_files (ehci); 566 * So long as they're part of class devices, we can't do it init()
567 * since the class device isn't created that early.
568 */
569 create_debug_files(ehci);
561 570
562 return 0; 571 return 0;
563} 572}
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index b654e3f800b4..441c26064b44 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -58,15 +58,76 @@ static int bios_handoff(struct ehci_hcd *ehci, int where, u32 cap)
58 return 0; 58 return 0;
59} 59}
60 60
61/* called by khubd or root hub init threads */ 61/* called after powerup, by probe or system-pm "wakeup" */
62static int ehci_pci_reinit(struct ehci_hcd *ehci, struct pci_dev *pdev)
63{
64 u32 temp;
65 int retval;
66 unsigned count = 256/4;
67
68 /* optional debug port, normally in the first BAR */
69 temp = pci_find_capability(pdev, 0x0a);
70 if (temp) {
71 pci_read_config_dword(pdev, temp, &temp);
72 temp >>= 16;
73 if ((temp & (3 << 13)) == (1 << 13)) {
74 temp &= 0x1fff;
75 ehci->debug = ehci_to_hcd(ehci)->regs + temp;
76 temp = readl(&ehci->debug->control);
77 ehci_info(ehci, "debug port %d%s\n",
78 HCS_DEBUG_PORT(ehci->hcs_params),
79 (temp & DBGP_ENABLED)
80 ? " IN USE"
81 : "");
82 if (!(temp & DBGP_ENABLED))
83 ehci->debug = NULL;
84 }
85 }
86
87 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
88
89 /* EHCI 0.96 and later may have "extended capabilities" */
90 while (temp && count--) {
91 u32 cap;
92
93 pci_read_config_dword(pdev, temp, &cap);
94 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
95 switch (cap & 0xff) {
96 case 1: /* BIOS/SMM/... handoff */
97 if (bios_handoff(ehci, temp, cap) != 0)
98 return -EOPNOTSUPP;
99 break;
100 case 0: /* illegal reserved capability */
101 ehci_dbg(ehci, "illegal capability!\n");
102 cap = 0;
103 /* FALLTHROUGH */
104 default: /* unknown */
105 break;
106 }
107 temp = (cap >> 8) & 0xff;
108 }
109 if (!count) {
110 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
111 return -EIO;
112 }
113
114 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
115 retval = pci_set_mwi(pdev);
116 if (!retval)
117 ehci_dbg(ehci, "MWI active\n");
118
119 ehci_port_power(ehci, 0);
120
121 return 0;
122}
123
124/* called by khubd or root hub (re)init threads; leaves HC in halt state */
62static int ehci_pci_reset(struct usb_hcd *hcd) 125static int ehci_pci_reset(struct usb_hcd *hcd)
63{ 126{
64 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 127 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
65 struct pci_dev *pdev = to_pci_dev(hcd->self.controller); 128 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
66 u32 temp; 129 u32 temp;
67 unsigned count = 256/4; 130 int retval;
68
69 spin_lock_init (&ehci->lock);
70 131
71 ehci->caps = hcd->regs; 132 ehci->caps = hcd->regs;
72 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase)); 133 ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
@@ -76,6 +137,10 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
76 /* cache this readonly data; minimize chip reads */ 137 /* cache this readonly data; minimize chip reads */
77 ehci->hcs_params = readl(&ehci->caps->hcs_params); 138 ehci->hcs_params = readl(&ehci->caps->hcs_params);
78 139
140 retval = ehci_halt(ehci);
141 if (retval)
142 return retval;
143
79 /* NOTE: only the parts below this line are PCI-specific */ 144 /* NOTE: only the parts below this line are PCI-specific */
80 145
81 switch (pdev->vendor) { 146 switch (pdev->vendor) {
@@ -111,57 +176,9 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
111 break; 176 break;
112 } 177 }
113 178
114 /* optional debug port, normally in the first BAR */
115 temp = pci_find_capability(pdev, 0x0a);
116 if (temp) {
117 pci_read_config_dword(pdev, temp, &temp);
118 temp >>= 16;
119 if ((temp & (3 << 13)) == (1 << 13)) {
120 temp &= 0x1fff;
121 ehci->debug = hcd->regs + temp;
122 temp = readl(&ehci->debug->control);
123 ehci_info(ehci, "debug port %d%s\n",
124 HCS_DEBUG_PORT(ehci->hcs_params),
125 (temp & DBGP_ENABLED)
126 ? " IN USE"
127 : "");
128 if (!(temp & DBGP_ENABLED))
129 ehci->debug = NULL;
130 }
131 }
132
133 temp = HCC_EXT_CAPS(readl(&ehci->caps->hcc_params));
134
135 /* EHCI 0.96 and later may have "extended capabilities" */
136 while (temp && count--) {
137 u32 cap;
138
139 pci_read_config_dword(to_pci_dev(hcd->self.controller),
140 temp, &cap);
141 ehci_dbg(ehci, "capability %04x at %02x\n", cap, temp);
142 switch (cap & 0xff) {
143 case 1: /* BIOS/SMM/... handoff */
144 if (bios_handoff(ehci, temp, cap) != 0)
145 return -EOPNOTSUPP;
146 break;
147 case 0: /* illegal reserved capability */
148 ehci_warn(ehci, "illegal capability!\n");
149 cap = 0;
150 /* FALLTHROUGH */
151 default: /* unknown */
152 break;
153 }
154 temp = (cap >> 8) & 0xff;
155 }
156 if (!count) {
157 ehci_err(ehci, "bogus capabilities ... PCI problems!\n");
158 return -EIO;
159 }
160 if (ehci_is_TDI(ehci)) 179 if (ehci_is_TDI(ehci))
161 ehci_reset(ehci); 180 ehci_reset(ehci);
162 181
163 ehci_port_power(ehci, 0);
164
165 /* at least the Genesys GL880S needs fixup here */ 182 /* at least the Genesys GL880S needs fixup here */
166 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params); 183 temp = HCS_N_CC(ehci->hcs_params) * HCS_N_PCC(ehci->hcs_params);
167 temp &= 0x0f; 184 temp &= 0x0f;
@@ -184,39 +201,15 @@ static int ehci_pci_reset(struct usb_hcd *hcd)
184 } 201 }
185 } 202 }
186 203
187 /* force HC to halt state */
188 return ehci_halt(ehci);
189}
190
191static int ehci_pci_start(struct usb_hcd *hcd)
192{
193 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
194 int result = 0;
195 struct pci_dev *pdev;
196 u16 port_wake;
197
198 pdev = to_pci_dev(hcd->self.controller);
199
200 /* Serial Bus Release Number is at PCI 0x60 offset */ 204 /* Serial Bus Release Number is at PCI 0x60 offset */
201 pci_read_config_byte(pdev, 0x60, &ehci->sbrn); 205 pci_read_config_byte(pdev, 0x60, &ehci->sbrn);
202 206
203 /* port wake capability, reported by boot firmware */ 207 /* REVISIT: per-port wake capability (PCI 0x62) currently unused */
204 pci_read_config_word(pdev, 0x62, &port_wake);
205 hcd->can_wakeup = (port_wake & 1) != 0;
206
207 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
208 result = pci_set_mwi(pdev);
209 if (!result)
210 ehci_dbg(ehci, "MWI active\n");
211
212 return ehci_run(hcd);
213}
214 208
215/* always called by thread; normally rmmod */ 209 retval = ehci_pci_reinit(ehci, pdev);
216 210
217static void ehci_pci_stop(struct usb_hcd *hcd) 211 /* finish init */
218{ 212 return ehci_init(hcd);
219 ehci_stop(hcd);
220} 213}
221 214
222/*-------------------------------------------------------------------------*/ 215/*-------------------------------------------------------------------------*/
@@ -250,6 +243,7 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
250 struct ehci_hcd *ehci = hcd_to_ehci(hcd); 243 struct ehci_hcd *ehci = hcd_to_ehci(hcd);
251 unsigned port; 244 unsigned port;
252 struct usb_device *root = hcd->self.root_hub; 245 struct usb_device *root = hcd->self.root_hub;
246 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
253 int retval = -EINVAL; 247 int retval = -EINVAL;
254 248
255 // maybe restore FLADJ 249 // maybe restore FLADJ
@@ -258,7 +252,7 @@ static int ehci_pci_resume(struct usb_hcd *hcd)
258 msleep(100); 252 msleep(100);
259 253
260 /* If CF is clear, we lost PCI Vaux power and need to restart. */ 254 /* If CF is clear, we lost PCI Vaux power and need to restart. */
261 if (readl(&ehci->regs->configured_flag) != cpu_to_le32(FLAG_CF)) 255 if (readl(&ehci->regs->configured_flag) != FLAG_CF)
262 goto restart; 256 goto restart;
263 257
264 /* If any port is suspended (or owned by the companion), 258 /* If any port is suspended (or owned by the companion),
@@ -292,7 +286,7 @@ restart:
292 */ 286 */
293 (void) ehci_halt(ehci); 287 (void) ehci_halt(ehci);
294 (void) ehci_reset(ehci); 288 (void) ehci_reset(ehci);
295 (void) ehci_pci_reset(hcd); 289 (void) ehci_pci_reinit(ehci, pdev);
296 290
297 /* emptying the schedule aborts any urbs */ 291 /* emptying the schedule aborts any urbs */
298 spin_lock_irq(&ehci->lock); 292 spin_lock_irq(&ehci->lock);
@@ -304,9 +298,7 @@ restart:
304 /* restart; khubd will disconnect devices */ 298 /* restart; khubd will disconnect devices */
305 retval = ehci_run(hcd); 299 retval = ehci_run(hcd);
306 300
307 /* here we "know" root ports should always stay powered; 301 /* here we "know" root ports should always stay powered */
308 * but some controllers may lose all power.
309 */
310 ehci_port_power(ehci, 1); 302 ehci_port_power(ehci, 1);
311 303
312 return retval; 304 return retval;
@@ -328,12 +320,12 @@ static const struct hc_driver ehci_pci_hc_driver = {
328 * basic lifecycle operations 320 * basic lifecycle operations
329 */ 321 */
330 .reset = ehci_pci_reset, 322 .reset = ehci_pci_reset,
331 .start = ehci_pci_start, 323 .start = ehci_run,
332#ifdef CONFIG_PM 324#ifdef CONFIG_PM
333 .suspend = ehci_pci_suspend, 325 .suspend = ehci_pci_suspend,
334 .resume = ehci_pci_resume, 326 .resume = ehci_pci_resume,
335#endif 327#endif
336 .stop = ehci_pci_stop, 328 .stop = ehci_stop,
337 329
338 /* 330 /*
339 * managing i/o requests and associated device resources 331 * managing i/o requests and associated device resources