aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorAtsushi Nemoto <anemo@mba.ocn.ne.jp>2006-11-01 12:08:36 -0500
committerRalf Baechle <ralf@linux-mips.org>2006-11-29 20:14:46 -0500
commit1603b5aca4f15b34848fb5594d0c7b6333b99144 (patch)
tree79272aa41d6510b7256df62e287676885c3960cf
parentc87b6ebaea034c0e0ce86127870cf1511a307b64 (diff)
[MIPS] IRQ cleanups
This is a big irq cleanup patch. * Use set_irq_chip() to register irq_chip. * Initialize .mask, .unmask, .mask_ack field. Functions for these method are already exist in most case. * Do not initialize .startup, .shutdown, .enable, .disable fields if default routines provided by irq_chip_set_defaults() were suitable. * Remove redundant irq_desc initializations. * Remove unnecessary local_irq_save/local_irq_restore, spin_lock. With this cleanup, it would be easy to switch to slightly lightwait irq flow handlers (handle_level_irq(), etc.) instead of __do_IRQ(). Though whole this patch is quite large, changes in each irq_chip are not quite simple. Please review and test on your platform. Thanks. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat
-rw-r--r--arch/mips/au1000/common/irq.c63
-rw-r--r--arch/mips/ddb5xxx/ddb5477/irq_5477.c23
-rw-r--r--arch/mips/dec/ecc-berr.c6
-rw-r--r--arch/mips/dec/ioasic-irq.c72
-rw-r--r--arch/mips/dec/kn02-irq.c53
-rw-r--r--arch/mips/emma2rh/common/irq_emma2rh.c34
-rw-r--r--arch/mips/emma2rh/markeins/irq_markeins.c55
-rw-r--r--arch/mips/gt64120/ev64120/irq.c40
-rw-r--r--arch/mips/jazz/irq.c27
-rw-r--r--arch/mips/jmr3927/rbhma3100/irq.c32
-rw-r--r--arch/mips/kernel/i8259.c21
-rw-r--r--arch/mips/kernel/irq-msc01.c45
-rw-r--r--arch/mips/kernel/irq-mv6434x.c53
-rw-r--r--arch/mips/kernel/irq-rm7000.c53
-rw-r--r--arch/mips/kernel/irq-rm9000.c45
-rw-r--r--arch/mips/kernel/irq.c13
-rw-r--r--arch/mips/kernel/irq_cpu.c77
-rw-r--r--arch/mips/lasat/interrupt.c36
-rw-r--r--arch/mips/mips-boards/atlas/atlas_int.c28
-rw-r--r--arch/mips/momentum/ocelot_c/cpci-irq.c53
-rw-r--r--arch/mips/momentum/ocelot_c/uart-irq.c56
-rw-r--r--arch/mips/philips/pnx8550/common/int.c66
-rw-r--r--arch/mips/sgi-ip22/ip22-eisa.c33
-rw-r--r--arch/mips/sgi-ip22/ip22-int.c109
-rw-r--r--arch/mips/sgi-ip27/ip27-irq.c17
-rw-r--r--arch/mips/sgi-ip27/ip27-timer.c27
-rw-r--r--arch/mips/sgi-ip32/ip32-irq.c133
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c30
-rw-r--r--arch/mips/sibyte/sb1250/irq.c30
-rw-r--r--arch/mips/sni/irq.c40
-rw-r--r--arch/mips/tx4927/common/tx4927_irq.c162
-rw-r--r--arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c183
-rw-r--r--arch/mips/tx4938/common/irq.c113
-rw-r--r--arch/mips/tx4938/toshiba_rbtx4938/irq.c53
-rw-r--r--arch/mips/vr41xx/common/icu.c46
-rw-r--r--arch/mips/vr41xx/nec-cmbvr4133/irq.c20
-rw-r--r--include/asm-mips/dec/kn02.h2
37 files changed, 292 insertions, 1657 deletions
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
index 2abe132bb07d..9cf7b6715836 100644
--- a/arch/mips/au1000/common/irq.c
+++ b/arch/mips/au1000/common/irq.c
@@ -70,7 +70,6 @@ extern irq_cpustat_t irq_stat [NR_CPUS];
70extern void mips_timer_interrupt(void); 70extern void mips_timer_interrupt(void);
71 71
72static void setup_local_irq(unsigned int irq, int type, int int_req); 72static void setup_local_irq(unsigned int irq, int type, int int_req);
73static unsigned int startup_irq(unsigned int irq);
74static void end_irq(unsigned int irq_nr); 73static void end_irq(unsigned int irq_nr);
75static inline void mask_and_ack_level_irq(unsigned int irq_nr); 74static inline void mask_and_ack_level_irq(unsigned int irq_nr);
76static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr); 75static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
@@ -84,20 +83,6 @@ void (*board_init_irq)(void);
84static DEFINE_SPINLOCK(irq_lock); 83static DEFINE_SPINLOCK(irq_lock);
85 84
86 85
87static unsigned int startup_irq(unsigned int irq_nr)
88{
89 local_enable_irq(irq_nr);
90 return 0;
91}
92
93
94static void shutdown_irq(unsigned int irq_nr)
95{
96 local_disable_irq(irq_nr);
97 return;
98}
99
100
101inline void local_enable_irq(unsigned int irq_nr) 86inline void local_enable_irq(unsigned int irq_nr)
102{ 87{
103 if (irq_nr > AU1000_LAST_INTC0_INT) { 88 if (irq_nr > AU1000_LAST_INTC0_INT) {
@@ -249,41 +234,37 @@ void restore_local_and_enable(int controller, unsigned long mask)
249 234
250static struct irq_chip rise_edge_irq_type = { 235static struct irq_chip rise_edge_irq_type = {
251 .typename = "Au1000 Rise Edge", 236 .typename = "Au1000 Rise Edge",
252 .startup = startup_irq,
253 .shutdown = shutdown_irq,
254 .enable = local_enable_irq,
255 .disable = local_disable_irq,
256 .ack = mask_and_ack_rise_edge_irq, 237 .ack = mask_and_ack_rise_edge_irq,
238 .mask = local_disable_irq,
239 .mask_ack = mask_and_ack_rise_edge_irq,
240 .unmask = local_enable_irq,
257 .end = end_irq, 241 .end = end_irq,
258}; 242};
259 243
260static struct irq_chip fall_edge_irq_type = { 244static struct irq_chip fall_edge_irq_type = {
261 .typename = "Au1000 Fall Edge", 245 .typename = "Au1000 Fall Edge",
262 .startup = startup_irq,
263 .shutdown = shutdown_irq,
264 .enable = local_enable_irq,
265 .disable = local_disable_irq,
266 .ack = mask_and_ack_fall_edge_irq, 246 .ack = mask_and_ack_fall_edge_irq,
247 .mask = local_disable_irq,
248 .mask_ack = mask_and_ack_fall_edge_irq,
249 .unmask = local_enable_irq,
267 .end = end_irq, 250 .end = end_irq,
268}; 251};
269 252
270static struct irq_chip either_edge_irq_type = { 253static struct irq_chip either_edge_irq_type = {
271 .typename = "Au1000 Rise or Fall Edge", 254 .typename = "Au1000 Rise or Fall Edge",
272 .startup = startup_irq,
273 .shutdown = shutdown_irq,
274 .enable = local_enable_irq,
275 .disable = local_disable_irq,
276 .ack = mask_and_ack_either_edge_irq, 255 .ack = mask_and_ack_either_edge_irq,
256 .mask = local_disable_irq,
257 .mask_ack = mask_and_ack_either_edge_irq,
258 .unmask = local_enable_irq,
277 .end = end_irq, 259 .end = end_irq,
278}; 260};
279 261
280static struct irq_chip level_irq_type = { 262static struct irq_chip level_irq_type = {
281 .typename = "Au1000 Level", 263 .typename = "Au1000 Level",
282 .startup = startup_irq,
283 .shutdown = shutdown_irq,
284 .enable = local_enable_irq,
285 .disable = local_disable_irq,
286 .ack = mask_and_ack_level_irq, 264 .ack = mask_and_ack_level_irq,
265 .mask = local_disable_irq,
266 .mask_ack = mask_and_ack_level_irq,
267 .unmask = local_enable_irq,
287 .end = end_irq, 268 .end = end_irq,
288}; 269};
289 270
@@ -328,31 +309,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
328 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 309 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
329 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 310 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
330 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 311 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
331 irq_desc[irq_nr].chip = &rise_edge_irq_type; 312 set_irq_chip(irq_nr, &rise_edge_irq_type);
332 break; 313 break;
333 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 314 case INTC_INT_FALL_EDGE: /* 0:1:0 */
334 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 315 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
335 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 316 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
336 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 317 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
337 irq_desc[irq_nr].chip = &fall_edge_irq_type; 318 set_irq_chip(irq_nr, &fall_edge_irq_type);
338 break; 319 break;
339 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 320 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
340 au_writel(1<<(irq_nr-32), IC1_CFG2CLR); 321 au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
341 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 322 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
342 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 323 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
343 irq_desc[irq_nr].chip = &either_edge_irq_type; 324 set_irq_chip(irq_nr, &either_edge_irq_type);
344 break; 325 break;
345 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 326 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
346 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 327 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
347 au_writel(1<<(irq_nr-32), IC1_CFG1CLR); 328 au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
348 au_writel(1<<(irq_nr-32), IC1_CFG0SET); 329 au_writel(1<<(irq_nr-32), IC1_CFG0SET);
349 irq_desc[irq_nr].chip = &level_irq_type; 330 set_irq_chip(irq_nr, &level_irq_type);
350 break; 331 break;
351 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 332 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
352 au_writel(1<<(irq_nr-32), IC1_CFG2SET); 333 au_writel(1<<(irq_nr-32), IC1_CFG2SET);
353 au_writel(1<<(irq_nr-32), IC1_CFG1SET); 334 au_writel(1<<(irq_nr-32), IC1_CFG1SET);
354 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 335 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
355 irq_desc[irq_nr].chip = &level_irq_type; 336 set_irq_chip(irq_nr, &level_irq_type);
356 break; 337 break;
357 case INTC_INT_DISABLED: /* 0:0:0 */ 338 case INTC_INT_DISABLED: /* 0:0:0 */
358 au_writel(1<<(irq_nr-32), IC1_CFG0CLR); 339 au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
@@ -380,31 +361,31 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
380 au_writel(1<<irq_nr, IC0_CFG2CLR); 361 au_writel(1<<irq_nr, IC0_CFG2CLR);
381 au_writel(1<<irq_nr, IC0_CFG1CLR); 362 au_writel(1<<irq_nr, IC0_CFG1CLR);
382 au_writel(1<<irq_nr, IC0_CFG0SET); 363 au_writel(1<<irq_nr, IC0_CFG0SET);
383 irq_desc[irq_nr].chip = &rise_edge_irq_type; 364 set_irq_chip(irq_nr, &rise_edge_irq_type);
384 break; 365 break;
385 case INTC_INT_FALL_EDGE: /* 0:1:0 */ 366 case INTC_INT_FALL_EDGE: /* 0:1:0 */
386 au_writel(1<<irq_nr, IC0_CFG2CLR); 367 au_writel(1<<irq_nr, IC0_CFG2CLR);
387 au_writel(1<<irq_nr, IC0_CFG1SET); 368 au_writel(1<<irq_nr, IC0_CFG1SET);
388 au_writel(1<<irq_nr, IC0_CFG0CLR); 369 au_writel(1<<irq_nr, IC0_CFG0CLR);
389 irq_desc[irq_nr].chip = &fall_edge_irq_type; 370 set_irq_chip(irq_nr, &fall_edge_irq_type);
390 break; 371 break;
391 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */ 372 case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
392 au_writel(1<<irq_nr, IC0_CFG2CLR); 373 au_writel(1<<irq_nr, IC0_CFG2CLR);
393 au_writel(1<<irq_nr, IC0_CFG1SET); 374 au_writel(1<<irq_nr, IC0_CFG1SET);
394 au_writel(1<<irq_nr, IC0_CFG0SET); 375 au_writel(1<<irq_nr, IC0_CFG0SET);
395 irq_desc[irq_nr].chip = &either_edge_irq_type; 376 set_irq_chip(irq_nr, &either_edge_irq_type);
396 break; 377 break;
397 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */ 378 case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
398 au_writel(1<<irq_nr, IC0_CFG2SET); 379 au_writel(1<<irq_nr, IC0_CFG2SET);
399 au_writel(1<<irq_nr, IC0_CFG1CLR); 380 au_writel(1<<irq_nr, IC0_CFG1CLR);
400 au_writel(1<<irq_nr, IC0_CFG0SET); 381 au_writel(1<<irq_nr, IC0_CFG0SET);
401 irq_desc[irq_nr].chip = &level_irq_type; 382 set_irq_chip(irq_nr, &level_irq_type);
402 break; 383 break;
403 case INTC_INT_LOW_LEVEL: /* 1:1:0 */ 384 case INTC_INT_LOW_LEVEL: /* 1:1:0 */
404 au_writel(1<<irq_nr, IC0_CFG2SET); 385 au_writel(1<<irq_nr, IC0_CFG2SET);
405 au_writel(1<<irq_nr, IC0_CFG1SET); 386 au_writel(1<<irq_nr, IC0_CFG1SET);
406 au_writel(1<<irq_nr, IC0_CFG0CLR); 387 au_writel(1<<irq_nr, IC0_CFG0CLR);
407 irq_desc[irq_nr].chip = &level_irq_type; 388 set_irq_chip(irq_nr, &level_irq_type);
408 break; 389 break;
409 case INTC_INT_DISABLED: /* 0:0:0 */ 390 case INTC_INT_DISABLED: /* 0:0:0 */
410 au_writel(1<<irq_nr, IC0_CFG0CLR); 391 au_writel(1<<irq_nr, IC0_CFG0CLR);
diff --git a/arch/mips/ddb5xxx/ddb5477/irq_5477.c b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
index ba52705a2738..96249aa5df5d 100644
--- a/arch/mips/ddb5xxx/ddb5477/irq_5477.c
+++ b/arch/mips/ddb5xxx/ddb5477/irq_5477.c
@@ -53,14 +53,6 @@ vrc5477_irq_disable(unsigned int irq)
53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base); 53 ll_vrc5477_irq_disable(irq - vrc5477_irq_base);
54} 54}
55 55
56static unsigned int vrc5477_irq_startup(unsigned int irq)
57{
58 vrc5477_irq_enable(irq);
59 return 0;
60}
61
62#define vrc5477_irq_shutdown vrc5477_irq_disable
63
64static void 56static void
65vrc5477_irq_ack(unsigned int irq) 57vrc5477_irq_ack(unsigned int irq)
66{ 58{
@@ -91,11 +83,10 @@ vrc5477_irq_end(unsigned int irq)
91 83
92struct irq_chip vrc5477_irq_controller = { 84struct irq_chip vrc5477_irq_controller = {
93 .typename = "vrc5477_irq", 85 .typename = "vrc5477_irq",
94 .startup = vrc5477_irq_startup,
95 .shutdown = vrc5477_irq_shutdown,
96 .enable = vrc5477_irq_enable,
97 .disable = vrc5477_irq_disable,
98 .ack = vrc5477_irq_ack, 86 .ack = vrc5477_irq_ack,
87 .mask = vrc5477_irq_disable,
88 .mask_ack = vrc5477_irq_ack,
89 .unmask = vrc5477_irq_enable,
99 .end = vrc5477_irq_end 90 .end = vrc5477_irq_end
100}; 91};
101 92
@@ -103,12 +94,8 @@ void __init vrc5477_irq_init(u32 irq_base)
103{ 94{
104 u32 i; 95 u32 i;
105 96
106 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++) { 97 for (i= irq_base; i< irq_base+ NUM_5477_IRQ; i++)
107 irq_desc[i].status = IRQ_DISABLED; 98 set_irq_chip(i, &vrc5477_irq_controller);
108 irq_desc[i].action = NULL;
109 irq_desc[i].depth = 1;
110 irq_desc[i].chip = &vrc5477_irq_controller;
111 }
112 99
113 vrc5477_irq_base = irq_base; 100 vrc5477_irq_base = irq_base;
114} 101}
diff --git a/arch/mips/dec/ecc-berr.c b/arch/mips/dec/ecc-berr.c
index 3e374d05978f..c8430c07355e 100644
--- a/arch/mips/dec/ecc-berr.c
+++ b/arch/mips/dec/ecc-berr.c
@@ -18,7 +18,6 @@
18#include <linux/interrupt.h> 18#include <linux/interrupt.h>
19#include <linux/kernel.h> 19#include <linux/kernel.h>
20#include <linux/sched.h> 20#include <linux/sched.h>
21#include <linux/spinlock.h>
22#include <linux/types.h> 21#include <linux/types.h>
23 22
24#include <asm/addrspace.h> 23#include <asm/addrspace.h>
@@ -231,13 +230,10 @@ irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id)
231static inline void dec_kn02_be_init(void) 230static inline void dec_kn02_be_init(void)
232{ 231{
233 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR); 232 volatile u32 *csr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CSR);
234 unsigned long flags;
235 233
236 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR); 234 kn0x_erraddr = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_ERRADDR);
237 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN); 235 kn0x_chksyn = (void *)CKSEG1ADDR(KN02_SLOT_BASE + KN02_CHKSYN);
238 236
239 spin_lock_irqsave(&kn02_lock, flags);
240
241 /* Preset write-only bits of the Control Register cache. */ 237 /* Preset write-only bits of the Control Register cache. */
242 cached_kn02_csr = *csr | KN02_CSR_LEDS; 238 cached_kn02_csr = *csr | KN02_CSR_LEDS;
243 239
@@ -247,8 +243,6 @@ static inline void dec_kn02_be_init(void)
247 cached_kn02_csr |= KN02_CSR_CORRECT; 243 cached_kn02_csr |= KN02_CSR_CORRECT;
248 *csr = cached_kn02_csr; 244 *csr = cached_kn02_csr;
249 iob(); 245 iob();
250
251 spin_unlock_irqrestore(&kn02_lock, flags);
252} 246}
253 247
254static inline void dec_kn03_be_init(void) 248static inline void dec_kn03_be_init(void)
diff --git a/arch/mips/dec/ioasic-irq.c b/arch/mips/dec/ioasic-irq.c
index 41cd2a96148b..d0af08bdbb4e 100644
--- a/arch/mips/dec/ioasic-irq.c
+++ b/arch/mips/dec/ioasic-irq.c
@@ -13,7 +13,6 @@
13 13
14#include <linux/init.h> 14#include <linux/init.h>
15#include <linux/irq.h> 15#include <linux/irq.h>
16#include <linux/spinlock.h>
17#include <linux/types.h> 16#include <linux/types.h>
18 17
19#include <asm/dec/ioasic.h> 18#include <asm/dec/ioasic.h>
@@ -21,8 +20,6 @@
21#include <asm/dec/ioasic_ints.h> 20#include <asm/dec/ioasic_ints.h>
22 21
23 22
24static DEFINE_SPINLOCK(ioasic_lock);
25
26static int ioasic_irq_base; 23static int ioasic_irq_base;
27 24
28 25
@@ -52,65 +49,31 @@ static inline void clear_ioasic_irq(unsigned int irq)
52 ioasic_write(IO_REG_SIR, sir); 49 ioasic_write(IO_REG_SIR, sir);
53} 50}
54 51
55static inline void enable_ioasic_irq(unsigned int irq)
56{
57 unsigned long flags;
58
59 spin_lock_irqsave(&ioasic_lock, flags);
60 unmask_ioasic_irq(irq);
61 spin_unlock_irqrestore(&ioasic_lock, flags);
62}
63
64static inline void disable_ioasic_irq(unsigned int irq)
65{
66 unsigned long flags;
67
68 spin_lock_irqsave(&ioasic_lock, flags);
69 mask_ioasic_irq(irq);
70 spin_unlock_irqrestore(&ioasic_lock, flags);
71}
72
73
74static inline unsigned int startup_ioasic_irq(unsigned int irq)
75{
76 enable_ioasic_irq(irq);
77 return 0;
78}
79
80#define shutdown_ioasic_irq disable_ioasic_irq
81
82static inline void ack_ioasic_irq(unsigned int irq) 52static inline void ack_ioasic_irq(unsigned int irq)
83{ 53{
84 spin_lock(&ioasic_lock);
85 mask_ioasic_irq(irq); 54 mask_ioasic_irq(irq);
86 spin_unlock(&ioasic_lock);
87 fast_iob(); 55 fast_iob();
88} 56}
89 57
90static inline void end_ioasic_irq(unsigned int irq) 58static inline void end_ioasic_irq(unsigned int irq)
91{ 59{
92 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 60 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
93 enable_ioasic_irq(irq); 61 unmask_ioasic_irq(irq);
94} 62}
95 63
96static struct irq_chip ioasic_irq_type = { 64static struct irq_chip ioasic_irq_type = {
97 .typename = "IO-ASIC", 65 .typename = "IO-ASIC",
98 .startup = startup_ioasic_irq,
99 .shutdown = shutdown_ioasic_irq,
100 .enable = enable_ioasic_irq,
101 .disable = disable_ioasic_irq,
102 .ack = ack_ioasic_irq, 66 .ack = ack_ioasic_irq,
67 .mask = mask_ioasic_irq,
68 .mask_ack = ack_ioasic_irq,
69 .unmask = unmask_ioasic_irq,
103 .end = end_ioasic_irq, 70 .end = end_ioasic_irq,
104}; 71};
105 72
106 73
107#define startup_ioasic_dma_irq startup_ioasic_irq 74#define unmask_ioasic_dma_irq unmask_ioasic_irq
108
109#define shutdown_ioasic_dma_irq shutdown_ioasic_irq
110
111#define enable_ioasic_dma_irq enable_ioasic_irq
112 75
113#define disable_ioasic_dma_irq disable_ioasic_irq 76#define mask_ioasic_dma_irq mask_ioasic_irq
114 77
115#define ack_ioasic_dma_irq ack_ioasic_irq 78#define ack_ioasic_dma_irq ack_ioasic_irq
116 79
@@ -123,11 +86,10 @@ static inline void end_ioasic_dma_irq(unsigned int irq)
123 86
124static struct irq_chip ioasic_dma_irq_type = { 87static struct irq_chip ioasic_dma_irq_type = {
125 .typename = "IO-ASIC-DMA", 88 .typename = "IO-ASIC-DMA",
126 .startup = startup_ioasic_dma_irq,
127 .shutdown = shutdown_ioasic_dma_irq,
128 .enable = enable_ioasic_dma_irq,
129 .disable = disable_ioasic_dma_irq,
130 .ack = ack_ioasic_dma_irq, 89 .ack = ack_ioasic_dma_irq,
90 .mask = mask_ioasic_dma_irq,
91 .mask_ack = ack_ioasic_dma_irq,
92 .unmask = unmask_ioasic_dma_irq,
131 .end = end_ioasic_dma_irq, 93 .end = end_ioasic_dma_irq,
132}; 94};
133 95
@@ -140,18 +102,10 @@ void __init init_ioasic_irqs(int base)
140 ioasic_write(IO_REG_SIMR, 0); 102 ioasic_write(IO_REG_SIMR, 0);
141 fast_iob(); 103 fast_iob();
142 104
143 for (i = base; i < base + IO_INR_DMA; i++) { 105 for (i = base; i < base + IO_INR_DMA; i++)
144 irq_desc[i].status = IRQ_DISABLED; 106 set_irq_chip(i, &ioasic_irq_type);
145 irq_desc[i].action = 0; 107 for (; i < base + IO_IRQ_LINES; i++)
146 irq_desc[i].depth = 1; 108 set_irq_chip(i, &ioasic_dma_irq_type);
147 irq_desc[i].chip = &ioasic_irq_type;
148 }
149 for (; i < base + IO_IRQ_LINES; i++) {
150 irq_desc[i].status = IRQ_DISABLED;
151 irq_desc[i].action = 0;
152 irq_desc[i].depth = 1;
153 irq_desc[i].chip = &ioasic_dma_irq_type;
154 }
155 109
156 ioasic_irq_base = base; 110 ioasic_irq_base = base;
157} 111}
diff --git a/arch/mips/dec/kn02-irq.c b/arch/mips/dec/kn02-irq.c
index 04a367a60a57..c761d97787ec 100644
--- a/arch/mips/dec/kn02-irq.c
+++ b/arch/mips/dec/kn02-irq.c
@@ -14,7 +14,6 @@
14 14
15#include <linux/init.h> 15#include <linux/init.h>
16#include <linux/irq.h> 16#include <linux/irq.h>
17#include <linux/spinlock.h>
18#include <linux/types.h> 17#include <linux/types.h>
19 18
20#include <asm/dec/kn02.h> 19#include <asm/dec/kn02.h>
@@ -29,7 +28,6 @@
29 * There is no default value -- it has to be initialized. 28 * There is no default value -- it has to be initialized.
30 */ 29 */
31u32 cached_kn02_csr; 30u32 cached_kn02_csr;
32DEFINE_SPINLOCK(kn02_lock);
33 31
34 32
35static int kn02_irq_base; 33static int kn02_irq_base;
@@ -53,54 +51,24 @@ static inline void mask_kn02_irq(unsigned int irq)
53 *csr = cached_kn02_csr; 51 *csr = cached_kn02_csr;
54} 52}
55 53
56static inline void enable_kn02_irq(unsigned int irq)
57{
58 unsigned long flags;
59
60 spin_lock_irqsave(&kn02_lock, flags);
61 unmask_kn02_irq(irq);
62 spin_unlock_irqrestore(&kn02_lock, flags);
63}
64
65static inline void disable_kn02_irq(unsigned int irq)
66{
67 unsigned long flags;
68
69 spin_lock_irqsave(&kn02_lock, flags);
70 mask_kn02_irq(irq);
71 spin_unlock_irqrestore(&kn02_lock, flags);
72}
73
74
75static unsigned int startup_kn02_irq(unsigned int irq)
76{
77 enable_kn02_irq(irq);
78 return 0;
79}
80
81#define shutdown_kn02_irq disable_kn02_irq
82
83static void ack_kn02_irq(unsigned int irq) 54static void ack_kn02_irq(unsigned int irq)
84{ 55{
85 spin_lock(&kn02_lock);
86 mask_kn02_irq(irq); 56 mask_kn02_irq(irq);
87 spin_unlock(&kn02_lock);
88 iob(); 57 iob();
89} 58}
90 59
91static void end_kn02_irq(unsigned int irq) 60static void end_kn02_irq(unsigned int irq)
92{ 61{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 62 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
94 enable_kn02_irq(irq); 63 unmask_kn02_irq(irq);
95} 64}
96 65
97static struct irq_chip kn02_irq_type = { 66static struct irq_chip kn02_irq_type = {
98 .typename = "KN02-CSR", 67 .typename = "KN02-CSR",
99 .startup = startup_kn02_irq,
100 .shutdown = shutdown_kn02_irq,
101 .enable = enable_kn02_irq,
102 .disable = disable_kn02_irq,
103 .ack = ack_kn02_irq, 68 .ack = ack_kn02_irq,
69 .mask = mask_kn02_irq,
70 .mask_ack = ack_kn02_irq,
71 .unmask = unmask_kn02_irq,
104 .end = end_kn02_irq, 72 .end = end_kn02_irq,
105}; 73};
106 74
@@ -109,22 +77,15 @@ void __init init_kn02_irqs(int base)
109{ 77{
110 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE + 78 volatile u32 *csr = (volatile u32 *)CKSEG1ADDR(KN02_SLOT_BASE +
111 KN02_CSR); 79 KN02_CSR);
112 unsigned long flags;
113 int i; 80 int i;
114 81
115 /* Mask interrupts. */ 82 /* Mask interrupts. */
116 spin_lock_irqsave(&kn02_lock, flags);
117 cached_kn02_csr &= ~KN02_CSR_IOINTEN; 83 cached_kn02_csr &= ~KN02_CSR_IOINTEN;
118 *csr = cached_kn02_csr; 84 *csr = cached_kn02_csr;
119 iob(); 85 iob();
120 spin_unlock_irqrestore(&kn02_lock, flags); 86
121 87 for (i = base; i < base + KN02_IRQ_LINES; i++)
122 for (i = base; i < base + KN02_IRQ_LINES; i++) { 88 set_irq_chip(i, &kn02_irq_type);
123 irq_desc[i].status = IRQ_DISABLED;
124 irq_desc[i].action = 0;
125 irq_desc[i].depth = 1;
126 irq_desc[i].chip = &kn02_irq_type;
127 }
128 89
129 kn02_irq_base = base; 90 kn02_irq_base = base;
130} 91}
diff --git a/arch/mips/emma2rh/common/irq_emma2rh.c b/arch/mips/emma2rh/common/irq_emma2rh.c
index 197ed4c2ba04..bf1b83ba925e 100644
--- a/arch/mips/emma2rh/common/irq_emma2rh.c
+++ b/arch/mips/emma2rh/common/irq_emma2rh.c
@@ -56,22 +56,6 @@ static void emma2rh_irq_disable(unsigned int irq)
56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base); 56 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
57} 57}
58 58
59static unsigned int emma2rh_irq_startup(unsigned int irq)
60{
61 emma2rh_irq_enable(irq);
62 return 0;
63}
64
65#define emma2rh_irq_shutdown emma2rh_irq_disable
66
67static void emma2rh_irq_ack(unsigned int irq)
68{
69 /* disable interrupt - some handler will re-enable the irq
70 * and if the interrupt is leveled, we will have infinite loop
71 */
72 ll_emma2rh_irq_disable(irq - emma2rh_irq_base);
73}
74
75static void emma2rh_irq_end(unsigned int irq) 59static void emma2rh_irq_end(unsigned int irq)
76{ 60{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 61 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -80,25 +64,19 @@ static void emma2rh_irq_end(unsigned int irq)
80 64
81struct irq_chip emma2rh_irq_controller = { 65struct irq_chip emma2rh_irq_controller = {
82 .typename = "emma2rh_irq", 66 .typename = "emma2rh_irq",
83 .startup = emma2rh_irq_startup, 67 .ack = emma2rh_irq_disable,
84 .shutdown = emma2rh_irq_shutdown, 68 .mask = emma2rh_irq_disable,
85 .enable = emma2rh_irq_enable, 69 .mask_ack = emma2rh_irq_disable,
86 .disable = emma2rh_irq_disable, 70 .unmask = emma2rh_irq_enable,
87 .ack = emma2rh_irq_ack,
88 .end = emma2rh_irq_end, 71 .end = emma2rh_irq_end,
89 .set_affinity = NULL /* no affinity stuff for UP */
90}; 72};
91 73
92void emma2rh_irq_init(u32 irq_base) 74void emma2rh_irq_init(u32 irq_base)
93{ 75{
94 u32 i; 76 u32 i;
95 77
96 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++) { 78 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ; i++)
97 irq_desc[i].status = IRQ_DISABLED; 79 set_irq_chip(i, &emma2rh_irq_controller);
98 irq_desc[i].action = NULL;
99 irq_desc[i].depth = 1;
100 irq_desc[i].chip = &emma2rh_irq_controller;
101 }
102 80
103 emma2rh_irq_base = irq_base; 81 emma2rh_irq_base = irq_base;
104} 82}
diff --git a/arch/mips/emma2rh/markeins/irq_markeins.c b/arch/mips/emma2rh/markeins/irq_markeins.c
index 0b36eb001e62..8e5f08a4245d 100644
--- a/arch/mips/emma2rh/markeins/irq_markeins.c
+++ b/arch/mips/emma2rh/markeins/irq_markeins.c
@@ -48,19 +48,6 @@ static void emma2rh_sw_irq_disable(unsigned int irq)
48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base); 48 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
49} 49}
50 50
51static unsigned int emma2rh_sw_irq_startup(unsigned int irq)
52{
53 emma2rh_sw_irq_enable(irq);
54 return 0;
55}
56
57#define emma2rh_sw_irq_shutdown emma2rh_sw_irq_disable
58
59static void emma2rh_sw_irq_ack(unsigned int irq)
60{
61 ll_emma2rh_sw_irq_disable(irq - emma2rh_sw_irq_base);
62}
63
64static void emma2rh_sw_irq_end(unsigned int irq) 51static void emma2rh_sw_irq_end(unsigned int irq)
65{ 52{
66 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 53 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -69,25 +56,19 @@ static void emma2rh_sw_irq_end(unsigned int irq)
69 56
70struct irq_chip emma2rh_sw_irq_controller = { 57struct irq_chip emma2rh_sw_irq_controller = {
71 .typename = "emma2rh_sw_irq", 58 .typename = "emma2rh_sw_irq",
72 .startup = emma2rh_sw_irq_startup, 59 .ack = emma2rh_sw_irq_disable,
73 .shutdown = emma2rh_sw_irq_shutdown, 60 .mask = emma2rh_sw_irq_disable,
74 .enable = emma2rh_sw_irq_enable, 61 .mask_ack = emma2rh_sw_irq_disable,
75 .disable = emma2rh_sw_irq_disable, 62 .unmask = emma2rh_sw_irq_enable,
76 .ack = emma2rh_sw_irq_ack,
77 .end = emma2rh_sw_irq_end, 63 .end = emma2rh_sw_irq_end,
78 .set_affinity = NULL,
79}; 64};
80 65
81void emma2rh_sw_irq_init(u32 irq_base) 66void emma2rh_sw_irq_init(u32 irq_base)
82{ 67{
83 u32 i; 68 u32 i;
84 69
85 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++) { 70 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_SW; i++)
86 irq_desc[i].status = IRQ_DISABLED; 71 set_irq_chip(i, &emma2rh_sw_irq_controller);
87 irq_desc[i].action = NULL;
88 irq_desc[i].depth = 2;
89 irq_desc[i].chip = &emma2rh_sw_irq_controller;
90 }
91 72
92 emma2rh_sw_irq_base = irq_base; 73 emma2rh_sw_irq_base = irq_base;
93} 74}
@@ -126,14 +107,6 @@ static void emma2rh_gpio_irq_disable(unsigned int irq)
126 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base); 107 ll_emma2rh_gpio_irq_disable(irq - emma2rh_gpio_irq_base);
127} 108}
128 109
129static unsigned int emma2rh_gpio_irq_startup(unsigned int irq)
130{
131 emma2rh_gpio_irq_enable(irq);
132 return 0;
133}
134
135#define emma2rh_gpio_irq_shutdown emma2rh_gpio_irq_disable
136
137static void emma2rh_gpio_irq_ack(unsigned int irq) 110static void emma2rh_gpio_irq_ack(unsigned int irq)
138{ 111{
139 irq -= emma2rh_gpio_irq_base; 112 irq -= emma2rh_gpio_irq_base;
@@ -149,25 +122,19 @@ static void emma2rh_gpio_irq_end(unsigned int irq)
149 122
150struct irq_chip emma2rh_gpio_irq_controller = { 123struct irq_chip emma2rh_gpio_irq_controller = {
151 .typename = "emma2rh_gpio_irq", 124 .typename = "emma2rh_gpio_irq",
152 .startup = emma2rh_gpio_irq_startup,
153 .shutdown = emma2rh_gpio_irq_shutdown,
154 .enable = emma2rh_gpio_irq_enable,
155 .disable = emma2rh_gpio_irq_disable,
156 .ack = emma2rh_gpio_irq_ack, 125 .ack = emma2rh_gpio_irq_ack,
126 .mask = emma2rh_gpio_irq_disable,
127 .mask_ack = emma2rh_gpio_irq_ack,
128 .unmask = emma2rh_gpio_irq_enable,
157 .end = emma2rh_gpio_irq_end, 129 .end = emma2rh_gpio_irq_end,
158 .set_affinity = NULL,
159}; 130};
160 131
161void emma2rh_gpio_irq_init(u32 irq_base) 132void emma2rh_gpio_irq_init(u32 irq_base)
162{ 133{
163 u32 i; 134 u32 i;
164 135
165 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++) { 136 for (i = irq_base; i < irq_base + NUM_EMMA2RH_IRQ_GPIO; i++)
166 irq_desc[i].status = IRQ_DISABLED; 137 set_irq_chip(i, &emma2rh_gpio_irq_controller);
167 irq_desc[i].action = NULL;
168 irq_desc[i].depth = 2;
169 irq_desc[i].chip = &emma2rh_gpio_irq_controller;
170 }
171 138
172 emma2rh_gpio_irq_base = irq_base; 139 emma2rh_gpio_irq_base = irq_base;
173} 140}
diff --git a/arch/mips/gt64120/ev64120/irq.c b/arch/mips/gt64120/ev64120/irq.c
index ed4d82b9a24a..b3e5796c81d7 100644
--- a/arch/mips/gt64120/ev64120/irq.c
+++ b/arch/mips/gt64120/ev64120/irq.c
@@ -66,38 +66,21 @@ asmlinkage void plat_irq_dispatch(void)
66 66
67static void disable_ev64120_irq(unsigned int irq_nr) 67static void disable_ev64120_irq(unsigned int irq_nr)
68{ 68{
69 unsigned long flags;
70
71 local_irq_save(flags);
72 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2 69 if (irq_nr >= 8) { // All PCI interrupts are on line 5 or 2
73 clear_c0_status(9 << 10); 70 clear_c0_status(9 << 10);
74 } else { 71 } else {
75 clear_c0_status(1 << (irq_nr + 8)); 72 clear_c0_status(1 << (irq_nr + 8));
76 } 73 }
77 local_irq_restore(flags);
78} 74}
79 75
80static void enable_ev64120_irq(unsigned int irq_nr) 76static void enable_ev64120_irq(unsigned int irq_nr)
81{ 77{
82 unsigned long flags;
83
84 local_irq_save(flags);
85 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2 78 if (irq_nr >= 8) // All PCI interrupts are on line 5 or 2
86 set_c0_status(9 << 10); 79 set_c0_status(9 << 10);
87 else 80 else
88 set_c0_status(1 << (irq_nr + 8)); 81 set_c0_status(1 << (irq_nr + 8));
89 local_irq_restore(flags);
90}
91
92static unsigned int startup_ev64120_irq(unsigned int irq)
93{
94 enable_ev64120_irq(irq);
95 return 0; /* Never anything pending */
96} 82}
97 83
98#define shutdown_ev64120_irq disable_ev64120_irq
99#define mask_and_ack_ev64120_irq disable_ev64120_irq
100
101static void end_ev64120_irq(unsigned int irq) 84static void end_ev64120_irq(unsigned int irq)
102{ 85{
103 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 86 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -106,13 +89,11 @@ static void end_ev64120_irq(unsigned int irq)
106 89
107static struct irq_chip ev64120_irq_type = { 90static struct irq_chip ev64120_irq_type = {
108 .typename = "EV64120", 91 .typename = "EV64120",
109 .startup = startup_ev64120_irq, 92 .ack = disable_ev64120_irq,
110 .shutdown = shutdown_ev64120_irq, 93 .mask = disable_ev64120_irq,
111 .enable = enable_ev64120_irq, 94 .mask_ack = disable_ev64120_irq,
112 .disable = disable_ev64120_irq, 95 .unmask = enable_ev64120_irq,
113 .ack = mask_and_ack_ev64120_irq,
114 .end = end_ev64120_irq, 96 .end = end_ev64120_irq,
115 .set_affinity = NULL
116}; 97};
117 98
118void gt64120_irq_setup(void) 99void gt64120_irq_setup(void)
@@ -122,8 +103,6 @@ void gt64120_irq_setup(void)
122 */ 103 */
123 clear_c0_status(ST0_IM); 104 clear_c0_status(ST0_IM);
124 105
125 local_irq_disable();
126
127 /* 106 /*
128 * Enable timer. Other interrupts will be enabled as they are 107 * Enable timer. Other interrupts will be enabled as they are
129 * registered. 108 * registered.
@@ -133,16 +112,5 @@ void gt64120_irq_setup(void)
133 112
134void __init arch_init_irq(void) 113void __init arch_init_irq(void)
135{ 114{
136 int i;
137
138 /* Let's initialize our IRQ descriptors */
139 for (i = 0; i < NR_IRQS; i++) {
140 irq_desc[i].status = 0;
141 irq_desc[i].chip = &no_irq_chip;
142 irq_desc[i].action = NULL;
143 irq_desc[i].depth = 0;
144 spin_lock_init(&irq_desc[i].lock);
145 }
146
147 gt64120_irq_setup(); 115 gt64120_irq_setup();
148} 116}
diff --git a/arch/mips/jazz/irq.c b/arch/mips/jazz/irq.c
index d5bd6b3a0933..4bbb6cb08d6e 100644
--- a/arch/mips/jazz/irq.c
+++ b/arch/mips/jazz/irq.c
@@ -28,14 +28,6 @@ static void enable_r4030_irq(unsigned int irq)
28 spin_unlock_irqrestore(&r4030_lock, flags); 28 spin_unlock_irqrestore(&r4030_lock, flags);
29} 29}
30 30
31static unsigned int startup_r4030_irq(unsigned int irq)
32{
33 enable_r4030_irq(irq);
34 return 0; /* never anything pending */
35}
36
37#define shutdown_r4030_irq disable_r4030_irq
38
39void disable_r4030_irq(unsigned int irq) 31void disable_r4030_irq(unsigned int irq)
40{ 32{
41 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ)); 33 unsigned int mask = ~(1 << (irq - JAZZ_PARALLEL_IRQ));
@@ -47,8 +39,6 @@ void disable_r4030_irq(unsigned int irq)
47 spin_unlock_irqrestore(&r4030_lock, flags); 39 spin_unlock_irqrestore(&r4030_lock, flags);
48} 40}
49 41
50#define mask_and_ack_r4030_irq disable_r4030_irq
51
52static void end_r4030_irq(unsigned int irq) 42static void end_r4030_irq(unsigned int irq)
53{ 43{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 44 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +47,10 @@ static void end_r4030_irq(unsigned int irq)
57 47
58static struct irq_chip r4030_irq_type = { 48static struct irq_chip r4030_irq_type = {
59 .typename = "R4030", 49 .typename = "R4030",
60 .startup = startup_r4030_irq, 50 .ack = disable_r4030_irq,
61 .shutdown = shutdown_r4030_irq, 51 .mask = disable_r4030_irq,
62 .enable = enable_r4030_irq, 52 .mask_ack = disable_r4030_irq,
63 .disable = disable_r4030_irq, 53 .unmask = enable_r4030_irq,
64 .ack = mask_and_ack_r4030_irq,
65 .end = end_r4030_irq, 54 .end = end_r4030_irq,
66}; 55};
67 56
@@ -69,12 +58,8 @@ void __init init_r4030_ints(void)
69{ 58{
70 int i; 59 int i;
71 60
72 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++) { 61 for (i = JAZZ_PARALLEL_IRQ; i <= JAZZ_TIMER_IRQ; i++)
73 irq_desc[i].status = IRQ_DISABLED; 62 set_irq_chip(i, &r4030_irq_type);
74 irq_desc[i].action = 0;
75 irq_desc[i].depth = 1;
76 irq_desc[i].chip = &r4030_irq_type;
77 }
78 63
79 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0); 64 r4030_write_reg16(JAZZ_IO_IRQ_ENABLE, 0);
80 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */ 65 r4030_read_reg16(JAZZ_IO_IRQ_SOURCE); /* clear pending IRQs */
diff --git a/arch/mips/jmr3927/rbhma3100/irq.c b/arch/mips/jmr3927/rbhma3100/irq.c
index de4a238c28be..3da49c5aaf49 100644
--- a/arch/mips/jmr3927/rbhma3100/irq.c
+++ b/arch/mips/jmr3927/rbhma3100/irq.c
@@ -90,17 +90,6 @@ static unsigned char irc_level[TX3927_NUM_IR] = {
90static void jmr3927_irq_disable(unsigned int irq_nr); 90static void jmr3927_irq_disable(unsigned int irq_nr);
91static void jmr3927_irq_enable(unsigned int irq_nr); 91static void jmr3927_irq_enable(unsigned int irq_nr);
92 92
93static DEFINE_SPINLOCK(jmr3927_irq_lock);
94
95static unsigned int jmr3927_irq_startup(unsigned int irq)
96{
97 jmr3927_irq_enable(irq);
98
99 return 0;
100}
101
102#define jmr3927_irq_shutdown jmr3927_irq_disable
103
104static void jmr3927_irq_ack(unsigned int irq) 93static void jmr3927_irq_ack(unsigned int irq)
105{ 94{
106 if (irq == JMR3927_IRQ_IRC_TMR0) 95 if (irq == JMR3927_IRQ_IRC_TMR0)
@@ -118,9 +107,7 @@ static void jmr3927_irq_end(unsigned int irq)
118static void jmr3927_irq_disable(unsigned int irq_nr) 107static void jmr3927_irq_disable(unsigned int irq_nr)
119{ 108{
120 struct tb_irq_space* sp; 109 struct tb_irq_space* sp;
121 unsigned long flags;
122 110
123 spin_lock_irqsave(&jmr3927_irq_lock, flags);
124 for (sp = tb_irq_spaces; sp; sp = sp->next) { 111 for (sp = tb_irq_spaces; sp; sp = sp->next) {
125 if (sp->start_irqno <= irq_nr && 112 if (sp->start_irqno <= irq_nr &&
126 irq_nr < sp->start_irqno + sp->nr_irqs) { 113 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -130,15 +117,12 @@ static void jmr3927_irq_disable(unsigned int irq_nr)
130 break; 117 break;
131 } 118 }
132 } 119 }
133 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
134} 120}
135 121
136static void jmr3927_irq_enable(unsigned int irq_nr) 122static void jmr3927_irq_enable(unsigned int irq_nr)
137{ 123{
138 struct tb_irq_space* sp; 124 struct tb_irq_space* sp;
139 unsigned long flags;
140 125
141 spin_lock_irqsave(&jmr3927_irq_lock, flags);
142 for (sp = tb_irq_spaces; sp; sp = sp->next) { 126 for (sp = tb_irq_spaces; sp; sp = sp->next) {
143 if (sp->start_irqno <= irq_nr && 127 if (sp->start_irqno <= irq_nr &&
144 irq_nr < sp->start_irqno + sp->nr_irqs) { 128 irq_nr < sp->start_irqno + sp->nr_irqs) {
@@ -148,7 +132,6 @@ static void jmr3927_irq_enable(unsigned int irq_nr)
148 break; 132 break;
149 } 133 }
150 } 134 }
151 spin_unlock_irqrestore(&jmr3927_irq_lock, flags);
152} 135}
153 136
154/* 137/*
@@ -457,11 +440,10 @@ void __init arch_init_irq(void)
457 440
458static struct irq_chip jmr3927_irq_controller = { 441static struct irq_chip jmr3927_irq_controller = {
459 .typename = "jmr3927_irq", 442 .typename = "jmr3927_irq",
460 .startup = jmr3927_irq_startup,
461 .shutdown = jmr3927_irq_shutdown,
462 .enable = jmr3927_irq_enable,
463 .disable = jmr3927_irq_disable,
464 .ack = jmr3927_irq_ack, 443 .ack = jmr3927_irq_ack,
444 .mask = jmr3927_irq_disable,
445 .mask_ack = jmr3927_irq_ack,
446 .unmask = jmr3927_irq_enable,
465 .end = jmr3927_irq_end, 447 .end = jmr3927_irq_end,
466}; 448};
467 449
@@ -469,12 +451,8 @@ void jmr3927_irq_init(u32 irq_base)
469{ 451{
470 u32 i; 452 u32 i;
471 453
472 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++) { 454 for (i= irq_base; i< irq_base + JMR3927_NR_IRQ_IRC + JMR3927_NR_IRQ_IOC; i++)
473 irq_desc[i].status = IRQ_DISABLED; 455 set_irq_chip(i, &jmr3927_irq_controller);
474 irq_desc[i].action = NULL;
475 irq_desc[i].depth = 1;
476 irq_desc[i].chip = &jmr3927_irq_controller;
477 }
478 456
479 jmr3927_irq_base = irq_base; 457 jmr3927_irq_base = irq_base;
480} 458}
diff --git a/arch/mips/kernel/i8259.c b/arch/mips/kernel/i8259.c
index 48e3418c217b..2526c0ca4d81 100644
--- a/arch/mips/kernel/i8259.c
+++ b/arch/mips/kernel/i8259.c
@@ -40,21 +40,10 @@ static void end_8259A_irq (unsigned int irq)
40 enable_8259A_irq(irq); 40 enable_8259A_irq(irq);
41} 41}
42 42
43#define shutdown_8259A_irq disable_8259A_irq
44
45void mask_and_ack_8259A(unsigned int); 43void mask_and_ack_8259A(unsigned int);
46 44
47static unsigned int startup_8259A_irq(unsigned int irq)
48{
49 enable_8259A_irq(irq);
50
51 return 0; /* never anything pending */
52}
53
54static struct irq_chip i8259A_irq_type = { 45static struct irq_chip i8259A_irq_type = {
55 .typename = "XT-PIC", 46 .typename = "XT-PIC",
56 .startup = startup_8259A_irq,
57 .shutdown = shutdown_8259A_irq,
58 .enable = enable_8259A_irq, 47 .enable = enable_8259A_irq,
59 .disable = disable_8259A_irq, 48 .disable = disable_8259A_irq,
60 .ack = mask_and_ack_8259A, 49 .ack = mask_and_ack_8259A,
@@ -120,7 +109,7 @@ int i8259A_irq_pending(unsigned int irq)
120void make_8259A_irq(unsigned int irq) 109void make_8259A_irq(unsigned int irq)
121{ 110{
122 disable_irq_nosync(irq); 111 disable_irq_nosync(irq);
123 irq_desc[irq].chip = &i8259A_irq_type; 112 set_irq_chip(irq, &i8259A_irq_type);
124 enable_irq(irq); 113 enable_irq(irq);
125} 114}
126 115
@@ -323,12 +312,8 @@ void __init init_i8259_irqs (void)
323 312
324 init_8259A(0); 313 init_8259A(0);
325 314
326 for (i = 0; i < 16; i++) { 315 for (i = 0; i < 16; i++)
327 irq_desc[i].status = IRQ_DISABLED; 316 set_irq_chip(i, &i8259A_irq_type);
328 irq_desc[i].action = NULL;
329 irq_desc[i].depth = 1;
330 irq_desc[i].chip = &i8259A_irq_type;
331 }
332 317
333 setup_irq(2, &irq2); 318 setup_irq(2, &irq2);
334} 319}
diff --git a/arch/mips/kernel/irq-msc01.c b/arch/mips/kernel/irq-msc01.c
index 650a80ca3741..e1880b27381b 100644
--- a/arch/mips/kernel/irq-msc01.c
+++ b/arch/mips/kernel/irq-msc01.c
@@ -45,31 +45,6 @@ static inline void unmask_msc_irq(unsigned int irq)
45} 45}
46 46
47/* 47/*
48 * Enables the IRQ on SOC-it
49 */
50static void enable_msc_irq(unsigned int irq)
51{
52 unmask_msc_irq(irq);
53}
54
55/*
56 * Initialize the IRQ on SOC-it
57 */
58static unsigned int startup_msc_irq(unsigned int irq)
59{
60 unmask_msc_irq(irq);
61 return 0;
62}
63
64/*
65 * Disables the IRQ on SOC-it
66 */
67static void disable_msc_irq(unsigned int irq)
68{
69 mask_msc_irq(irq);
70}
71
72/*
73 * Masks and ACKs an IRQ 48 * Masks and ACKs an IRQ
74 */ 49 */
75static void level_mask_and_ack_msc_irq(unsigned int irq) 50static void level_mask_and_ack_msc_irq(unsigned int irq)
@@ -136,25 +111,21 @@ msc_bind_eic_interrupt (unsigned int irq, unsigned int set)
136 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF)); 111 (irq<<MSC01_IC_RAMW_ADDR_SHF) | (set<<MSC01_IC_RAMW_DATA_SHF));
137} 112}
138 113
139#define shutdown_msc_irq disable_msc_irq
140
141struct irq_chip msc_levelirq_type = { 114struct irq_chip msc_levelirq_type = {
142 .typename = "SOC-it-Level", 115 .typename = "SOC-it-Level",
143 .startup = startup_msc_irq,
144 .shutdown = shutdown_msc_irq,
145 .enable = enable_msc_irq,
146 .disable = disable_msc_irq,
147 .ack = level_mask_and_ack_msc_irq, 116 .ack = level_mask_and_ack_msc_irq,
117 .mask = mask_msc_irq,
118 .mask_ack = level_mask_and_ack_msc_irq,
119 .unmask = unmask_msc_irq,
148 .end = end_msc_irq, 120 .end = end_msc_irq,
149}; 121};
150 122
151struct irq_chip msc_edgeirq_type = { 123struct irq_chip msc_edgeirq_type = {
152 .typename = "SOC-it-Edge", 124 .typename = "SOC-it-Edge",
153 .startup =startup_msc_irq,
154 .shutdown = shutdown_msc_irq,
155 .enable = enable_msc_irq,
156 .disable = disable_msc_irq,
157 .ack = edge_mask_and_ack_msc_irq, 125 .ack = edge_mask_and_ack_msc_irq,
126 .mask = mask_msc_irq,
127 .mask_ack = edge_mask_and_ack_msc_irq,
128 .unmask = unmask_msc_irq,
158 .end = end_msc_irq, 129 .end = end_msc_irq,
159}; 130};
160 131
@@ -175,14 +146,14 @@ void __init init_msc_irqs(unsigned int base, msc_irqmap_t *imp, int nirq)
175 146
176 switch (imp->im_type) { 147 switch (imp->im_type) {
177 case MSC01_IRQ_EDGE: 148 case MSC01_IRQ_EDGE:
178 irq_desc[base+n].chip = &msc_edgeirq_type; 149 set_irq_chip(base+n, &msc_edgeirq_type);
179 if (cpu_has_veic) 150 if (cpu_has_veic)
180 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT); 151 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT);
181 else 152 else
182 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl); 153 MSCIC_WRITE(MSC01_IC_SUP+n*8, MSC01_IC_SUP_EDGE_BIT | imp->im_lvl);
183 break; 154 break;
184 case MSC01_IRQ_LEVEL: 155 case MSC01_IRQ_LEVEL:
185 irq_desc[base+n].chip = &msc_levelirq_type; 156 set_irq_chip(base+n, &msc_levelirq_type);
186 if (cpu_has_veic) 157 if (cpu_has_veic)
187 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0); 158 MSCIC_WRITE(MSC01_IC_SUP+n*8, 0);
188 else 159 else
diff --git a/arch/mips/kernel/irq-mv6434x.c b/arch/mips/kernel/irq-mv6434x.c
index 37d106202b83..5012b9df1b5a 100644
--- a/arch/mips/kernel/irq-mv6434x.c
+++ b/arch/mips/kernel/irq-mv6434x.c
@@ -67,39 +67,6 @@ static inline void unmask_mv64340_irq(unsigned int irq)
67} 67}
68 68
69/* 69/*
70 * Enables the IRQ on Marvell Chip
71 */
72static void enable_mv64340_irq(unsigned int irq)
73{
74 unmask_mv64340_irq(irq);
75}
76
77/*
78 * Initialize the IRQ on Marvell Chip
79 */
80static unsigned int startup_mv64340_irq(unsigned int irq)
81{
82 unmask_mv64340_irq(irq);
83 return 0;
84}
85
86/*
87 * Disables the IRQ on Marvell Chip
88 */
89static void disable_mv64340_irq(unsigned int irq)
90{
91 mask_mv64340_irq(irq);
92}
93
94/*
95 * Masks and ACKs an IRQ
96 */
97static void mask_and_ack_mv64340_irq(unsigned int irq)
98{
99 mask_mv64340_irq(irq);
100}
101
102/*
103 * End IRQ processing 70 * End IRQ processing
104 */ 71 */
105static void end_mv64340_irq(unsigned int irq) 72static void end_mv64340_irq(unsigned int irq)
@@ -133,15 +100,12 @@ void ll_mv64340_irq(void)
133 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32); 100 do_IRQ(ls1bit32(irq_src_high) + irq_base + 32);
134} 101}
135 102
136#define shutdown_mv64340_irq disable_mv64340_irq
137
138struct irq_chip mv64340_irq_type = { 103struct irq_chip mv64340_irq_type = {
139 .typename = "MV-64340", 104 .typename = "MV-64340",
140 .startup = startup_mv64340_irq, 105 .ack = mask_mv64340_irq,
141 .shutdown = shutdown_mv64340_irq, 106 .mask = mask_mv64340_irq,
142 .enable = enable_mv64340_irq, 107 .mask_ack = mask_mv64340_irq,
143 .disable = disable_mv64340_irq, 108 .unmask = unmask_mv64340_irq,
144 .ack = mask_and_ack_mv64340_irq,
145 .end = end_mv64340_irq, 109 .end = end_mv64340_irq,
146}; 110};
147 111
@@ -149,13 +113,8 @@ void __init mv64340_irq_init(unsigned int base)
149{ 113{
150 int i; 114 int i;
151 115
152 /* Reset irq handlers pointers to NULL */ 116 for (i = base; i < base + 64; i++)
153 for (i = base; i < base + 64; i++) { 117 set_irq_chip(i, &mv64340_irq_type);
154 irq_desc[i].status = IRQ_DISABLED;
155 irq_desc[i].action = 0;
156 irq_desc[i].depth = 2;
157 irq_desc[i].chip = &mv64340_irq_type;
158 }
159 118
160 irq_base = base; 119 irq_base = base;
161} 120}
diff --git a/arch/mips/kernel/irq-rm7000.c b/arch/mips/kernel/irq-rm7000.c
index 6b54c7109e2e..6a297e3b8899 100644
--- a/arch/mips/kernel/irq-rm7000.c
+++ b/arch/mips/kernel/irq-rm7000.c
@@ -29,42 +29,6 @@ static inline void mask_rm7k_irq(unsigned int irq)
29 clear_c0_intcontrol(0x100 << (irq - irq_base)); 29 clear_c0_intcontrol(0x100 << (irq - irq_base));
30} 30}
31 31
32static inline void rm7k_cpu_irq_enable(unsigned int irq)
33{
34 unsigned long flags;
35
36 local_irq_save(flags);
37 unmask_rm7k_irq(irq);
38 local_irq_restore(flags);
39}
40
41static void rm7k_cpu_irq_disable(unsigned int irq)
42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 mask_rm7k_irq(irq);
47 local_irq_restore(flags);
48}
49
50static unsigned int rm7k_cpu_irq_startup(unsigned int irq)
51{
52 rm7k_cpu_irq_enable(irq);
53
54 return 0;
55}
56
57#define rm7k_cpu_irq_shutdown rm7k_cpu_irq_disable
58
59/*
60 * While we ack the interrupt interrupts are disabled and thus we don't need
61 * to deal with concurrency issues. Same for rm7k_cpu_irq_end.
62 */
63static void rm7k_cpu_irq_ack(unsigned int irq)
64{
65 mask_rm7k_irq(irq);
66}
67
68static void rm7k_cpu_irq_end(unsigned int irq) 32static void rm7k_cpu_irq_end(unsigned int irq)
69{ 33{
70 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 34 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -73,11 +37,10 @@ static void rm7k_cpu_irq_end(unsigned int irq)
73 37
74static struct irq_chip rm7k_irq_controller = { 38static struct irq_chip rm7k_irq_controller = {
75 .typename = "RM7000", 39 .typename = "RM7000",
76 .startup = rm7k_cpu_irq_startup, 40 .ack = mask_rm7k_irq,
77 .shutdown = rm7k_cpu_irq_shutdown, 41 .mask = mask_rm7k_irq,
78 .enable = rm7k_cpu_irq_enable, 42 .mask_ack = mask_rm7k_irq,
79 .disable = rm7k_cpu_irq_disable, 43 .unmask = unmask_rm7k_irq,
80 .ack = rm7k_cpu_irq_ack,
81 .end = rm7k_cpu_irq_end, 44 .end = rm7k_cpu_irq_end,
82}; 45};
83 46
@@ -87,12 +50,8 @@ void __init rm7k_cpu_irq_init(int base)
87 50
88 clear_c0_intcontrol(0x00000f00); /* Mask all */ 51 clear_c0_intcontrol(0x00000f00); /* Mask all */
89 52
90 for (i = base; i < base + 4; i++) { 53 for (i = base; i < base + 4; i++)
91 irq_desc[i].status = IRQ_DISABLED; 54 set_irq_chip(i, &rm7k_irq_controller);
92 irq_desc[i].action = NULL;
93 irq_desc[i].depth = 1;
94 irq_desc[i].chip = &rm7k_irq_controller;
95 }
96 55
97 irq_base = base; 56 irq_base = base;
98} 57}
diff --git a/arch/mips/kernel/irq-rm9000.c b/arch/mips/kernel/irq-rm9000.c
index 62f011ba97a2..977538445cf3 100644
--- a/arch/mips/kernel/irq-rm9000.c
+++ b/arch/mips/kernel/irq-rm9000.c
@@ -48,15 +48,6 @@ static void rm9k_cpu_irq_disable(unsigned int irq)
48 local_irq_restore(flags); 48 local_irq_restore(flags);
49} 49}
50 50
51static unsigned int rm9k_cpu_irq_startup(unsigned int irq)
52{
53 rm9k_cpu_irq_enable(irq);
54
55 return 0;
56}
57
58#define rm9k_cpu_irq_shutdown rm9k_cpu_irq_disable
59
60/* 51/*
61 * Performance counter interrupts are global on all processors. 52 * Performance counter interrupts are global on all processors.
62 */ 53 */
@@ -89,16 +80,6 @@ static void rm9k_perfcounter_irq_shutdown(unsigned int irq)
89 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1); 80 on_each_cpu(local_rm9k_perfcounter_irq_shutdown, (void *) irq, 0, 1);
90} 81}
91 82
92
93/*
94 * While we ack the interrupt interrupts are disabled and thus we don't need
95 * to deal with concurrency issues. Same for rm9k_cpu_irq_end.
96 */
97static void rm9k_cpu_irq_ack(unsigned int irq)
98{
99 mask_rm9k_irq(irq);
100}
101
102static void rm9k_cpu_irq_end(unsigned int irq) 83static void rm9k_cpu_irq_end(unsigned int irq)
103{ 84{
104 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 85 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -107,11 +88,10 @@ static void rm9k_cpu_irq_end(unsigned int irq)
107 88
108static struct irq_chip rm9k_irq_controller = { 89static struct irq_chip rm9k_irq_controller = {
109 .typename = "RM9000", 90 .typename = "RM9000",
110 .startup = rm9k_cpu_irq_startup, 91 .ack = mask_rm9k_irq,
111 .shutdown = rm9k_cpu_irq_shutdown, 92 .mask = mask_rm9k_irq,
112 .enable = rm9k_cpu_irq_enable, 93 .mask_ack = mask_rm9k_irq,
113 .disable = rm9k_cpu_irq_disable, 94 .unmask = unmask_rm9k_irq,
114 .ack = rm9k_cpu_irq_ack,
115 .end = rm9k_cpu_irq_end, 95 .end = rm9k_cpu_irq_end,
116}; 96};
117 97
@@ -119,9 +99,10 @@ static struct irq_chip rm9k_perfcounter_irq = {
119 .typename = "RM9000", 99 .typename = "RM9000",
120 .startup = rm9k_perfcounter_irq_startup, 100 .startup = rm9k_perfcounter_irq_startup,
121 .shutdown = rm9k_perfcounter_irq_shutdown, 101 .shutdown = rm9k_perfcounter_irq_shutdown,
122 .enable = rm9k_cpu_irq_enable, 102 .ack = mask_rm9k_irq,
123 .disable = rm9k_cpu_irq_disable, 103 .mask = mask_rm9k_irq,
124 .ack = rm9k_cpu_irq_ack, 104 .mask_ack = mask_rm9k_irq,
105 .unmask = unmask_rm9k_irq,
125 .end = rm9k_cpu_irq_end, 106 .end = rm9k_cpu_irq_end,
126}; 107};
127 108
@@ -135,15 +116,11 @@ void __init rm9k_cpu_irq_init(int base)
135 116
136 clear_c0_intcontrol(0x0000f000); /* Mask all */ 117 clear_c0_intcontrol(0x0000f000); /* Mask all */
137 118
138 for (i = base; i < base + 4; i++) { 119 for (i = base; i < base + 4; i++)
139 irq_desc[i].status = IRQ_DISABLED; 120 set_irq_chip(i, &rm9k_irq_controller);
140 irq_desc[i].action = NULL;
141 irq_desc[i].depth = 1;
142 irq_desc[i].chip = &rm9k_irq_controller;
143 }
144 121
145 rm9000_perfcount_irq = base + 1; 122 rm9000_perfcount_irq = base + 1;
146 irq_desc[rm9000_perfcount_irq].chip = &rm9k_perfcounter_irq; 123 set_irq_chip(rm9000_perfcount_irq, &rm9k_perfcounter_irq);
147 124
148 irq_base = base; 125 irq_base = base;
149} 126}
diff --git a/arch/mips/kernel/irq.c b/arch/mips/kernel/irq.c
index 9b0e49d63d7b..e997c9454f47 100644
--- a/arch/mips/kernel/irq.c
+++ b/arch/mips/kernel/irq.c
@@ -172,19 +172,6 @@ __setup("nokgdb", nokgdb);
172 172
173void __init init_IRQ(void) 173void __init init_IRQ(void)
174{ 174{
175 int i;
176
177 for (i = 0; i < NR_IRQS; i++) {
178 irq_desc[i].status = IRQ_DISABLED;
179 irq_desc[i].action = NULL;
180 irq_desc[i].depth = 1;
181 irq_desc[i].chip = &no_irq_chip;
182 spin_lock_init(&irq_desc[i].lock);
183#ifdef CONFIG_MIPS_MT_SMTC
184 irq_hwmask[i] = 0;
185#endif /* CONFIG_MIPS_MT_SMTC */
186 }
187
188 arch_init_irq(); 175 arch_init_irq();
189 176
190#ifdef CONFIG_KGDB 177#ifdef CONFIG_KGDB
diff --git a/arch/mips/kernel/irq_cpu.c b/arch/mips/kernel/irq_cpu.c
index 9bb21c7f2149..3b7cfa407e87 100644
--- a/arch/mips/kernel/irq_cpu.c
+++ b/arch/mips/kernel/irq_cpu.c
@@ -50,44 +50,6 @@ static inline void mask_mips_irq(unsigned int irq)
50 irq_disable_hazard(); 50 irq_disable_hazard();
51} 51}
52 52
53static inline void mips_cpu_irq_enable(unsigned int irq)
54{
55 unsigned long flags;
56
57 local_irq_save(flags);
58 unmask_mips_irq(irq);
59 back_to_back_c0_hazard();
60 local_irq_restore(flags);
61}
62
63static void mips_cpu_irq_disable(unsigned int irq)
64{
65 unsigned long flags;
66
67 local_irq_save(flags);
68 mask_mips_irq(irq);
69 back_to_back_c0_hazard();
70 local_irq_restore(flags);
71}
72
73static unsigned int mips_cpu_irq_startup(unsigned int irq)
74{
75 mips_cpu_irq_enable(irq);
76
77 return 0;
78}
79
80#define mips_cpu_irq_shutdown mips_cpu_irq_disable
81
82/*
83 * While we ack the interrupt interrupts are disabled and thus we don't need
84 * to deal with concurrency issues. Same for mips_cpu_irq_end.
85 */
86static void mips_cpu_irq_ack(unsigned int irq)
87{
88 mask_mips_irq(irq);
89}
90
91static void mips_cpu_irq_end(unsigned int irq) 53static void mips_cpu_irq_end(unsigned int irq)
92{ 54{
93 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 55 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -96,11 +58,10 @@ static void mips_cpu_irq_end(unsigned int irq)
96 58
97static struct irq_chip mips_cpu_irq_controller = { 59static struct irq_chip mips_cpu_irq_controller = {
98 .typename = "MIPS", 60 .typename = "MIPS",
99 .startup = mips_cpu_irq_startup, 61 .ack = mask_mips_irq,
100 .shutdown = mips_cpu_irq_shutdown, 62 .mask = mask_mips_irq,
101 .enable = mips_cpu_irq_enable, 63 .mask_ack = mask_mips_irq,
102 .disable = mips_cpu_irq_disable, 64 .unmask = unmask_mips_irq,
103 .ack = mips_cpu_irq_ack,
104 .end = mips_cpu_irq_end, 65 .end = mips_cpu_irq_end,
105}; 66};
106 67
@@ -110,8 +71,6 @@ static struct irq_chip mips_cpu_irq_controller = {
110 71
111#define unmask_mips_mt_irq unmask_mips_irq 72#define unmask_mips_mt_irq unmask_mips_irq
112#define mask_mips_mt_irq mask_mips_irq 73#define mask_mips_mt_irq mask_mips_irq
113#define mips_mt_cpu_irq_enable mips_cpu_irq_enable
114#define mips_mt_cpu_irq_disable mips_cpu_irq_disable
115 74
116static unsigned int mips_mt_cpu_irq_startup(unsigned int irq) 75static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
117{ 76{
@@ -119,13 +78,11 @@ static unsigned int mips_mt_cpu_irq_startup(unsigned int irq)
119 78
120 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base)); 79 clear_c0_cause(0x100 << (irq - mips_cpu_irq_base));
121 evpe(vpflags); 80 evpe(vpflags);
122 mips_mt_cpu_irq_enable(irq); 81 unmask_mips_mt_irq(irq);
123 82
124 return 0; 83 return 0;
125} 84}
126 85
127#define mips_mt_cpu_irq_shutdown mips_mt_cpu_irq_disable
128
129/* 86/*
130 * While we ack the interrupt interrupts are disabled and thus we don't need 87 * While we ack the interrupt interrupts are disabled and thus we don't need
131 * to deal with concurrency issues. Same for mips_cpu_irq_end. 88 * to deal with concurrency issues. Same for mips_cpu_irq_end.
@@ -143,10 +100,10 @@ static void mips_mt_cpu_irq_ack(unsigned int irq)
143static struct irq_chip mips_mt_cpu_irq_controller = { 100static struct irq_chip mips_mt_cpu_irq_controller = {
144 .typename = "MIPS", 101 .typename = "MIPS",
145 .startup = mips_mt_cpu_irq_startup, 102 .startup = mips_mt_cpu_irq_startup,
146 .shutdown = mips_mt_cpu_irq_shutdown,
147 .enable = mips_mt_cpu_irq_enable,
148 .disable = mips_mt_cpu_irq_disable,
149 .ack = mips_mt_cpu_irq_ack, 103 .ack = mips_mt_cpu_irq_ack,
104 .mask = mask_mips_mt_irq,
105 .mask_ack = mips_mt_cpu_irq_ack,
106 .unmask = unmask_mips_mt_irq,
150 .end = mips_mt_cpu_irq_end, 107 .end = mips_mt_cpu_irq_end,
151}; 108};
152 109
@@ -163,19 +120,11 @@ void __init mips_cpu_irq_init(int irq_base)
163 * leave them uninitialized for other processors. 120 * leave them uninitialized for other processors.
164 */ 121 */
165 if (cpu_has_mipsmt) 122 if (cpu_has_mipsmt)
166 for (i = irq_base; i < irq_base + 2; i++) { 123 for (i = irq_base; i < irq_base + 2; i++)
167 irq_desc[i].status = IRQ_DISABLED; 124 set_irq_chip(i, &mips_mt_cpu_irq_controller);
168 irq_desc[i].action = NULL; 125
169 irq_desc[i].depth = 1; 126 for (i = irq_base + 2; i < irq_base + 8; i++)
170 irq_desc[i].chip = &mips_mt_cpu_irq_controller; 127 set_irq_chip(i, &mips_cpu_irq_controller);
171 }
172
173 for (i = irq_base + 2; i < irq_base + 8; i++) {
174 irq_desc[i].status = IRQ_DISABLED;
175 irq_desc[i].action = NULL;
176 irq_desc[i].depth = 1;
177 irq_desc[i].chip = &mips_cpu_irq_controller;
178 }
179 128
180 mips_cpu_irq_base = irq_base; 129 mips_cpu_irq_base = irq_base;
181} 130}
diff --git a/arch/mips/lasat/interrupt.c b/arch/mips/lasat/interrupt.c
index a144a002dcc4..cac82afe5eb4 100644
--- a/arch/mips/lasat/interrupt.c
+++ b/arch/mips/lasat/interrupt.c
@@ -36,33 +36,14 @@ static volatile int lasat_int_mask_shift;
36 36
37void disable_lasat_irq(unsigned int irq_nr) 37void disable_lasat_irq(unsigned int irq_nr)
38{ 38{
39 unsigned long flags;
40
41 local_irq_save(flags);
42 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift; 39 *lasat_int_mask &= ~(1 << irq_nr) << lasat_int_mask_shift;
43 local_irq_restore(flags);
44} 40}
45 41
46void enable_lasat_irq(unsigned int irq_nr) 42void enable_lasat_irq(unsigned int irq_nr)
47{ 43{
48 unsigned long flags;
49
50 local_irq_save(flags);
51 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift; 44 *lasat_int_mask |= (1 << irq_nr) << lasat_int_mask_shift;
52 local_irq_restore(flags);
53} 45}
54 46
55static unsigned int startup_lasat_irq(unsigned int irq)
56{
57 enable_lasat_irq(irq);
58
59 return 0; /* never anything pending */
60}
61
62#define shutdown_lasat_irq disable_lasat_irq
63
64#define mask_and_ack_lasat_irq disable_lasat_irq
65
66static void end_lasat_irq(unsigned int irq) 47static void end_lasat_irq(unsigned int irq)
67{ 48{
68 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 49 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -71,11 +52,10 @@ static void end_lasat_irq(unsigned int irq)
71 52
72static struct irq_chip lasat_irq_type = { 53static struct irq_chip lasat_irq_type = {
73 .typename = "Lasat", 54 .typename = "Lasat",
74 .startup = startup_lasat_irq, 55 .ack = disable_lasat_irq,
75 .shutdown = shutdown_lasat_irq, 56 .mask = disable_lasat_irq,
76 .enable = enable_lasat_irq, 57 .mask_ack = disable_lasat_irq,
77 .disable = disable_lasat_irq, 58 .unmask = enable_lasat_irq,
78 .ack = mask_and_ack_lasat_irq,
79 .end = end_lasat_irq, 59 .end = end_lasat_irq,
80}; 60};
81 61
@@ -152,10 +132,6 @@ void __init arch_init_irq(void)
152 panic("arch_init_irq: mips_machtype incorrect"); 132 panic("arch_init_irq: mips_machtype incorrect");
153 } 133 }
154 134
155 for (i = 0; i <= LASATINT_END; i++) { 135 for (i = 0; i <= LASATINT_END; i++)
156 irq_desc[i].status = IRQ_DISABLED; 136 set_irq_chip(i, &lasat_irq_type);
157 irq_desc[i].action = 0;
158 irq_desc[i].depth = 1;
159 irq_desc[i].chip = &lasat_irq_type;
160 }
161} 137}
diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index be624b8c3b0e..7c710040d3f1 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -62,16 +62,6 @@ void enable_atlas_irq(unsigned int irq_nr)
62 iob(); 62 iob();
63} 63}
64 64
65static unsigned int startup_atlas_irq(unsigned int irq)
66{
67 enable_atlas_irq(irq);
68 return 0; /* never anything pending */
69}
70
71#define shutdown_atlas_irq disable_atlas_irq
72
73#define mask_and_ack_atlas_irq disable_atlas_irq
74
75static void end_atlas_irq(unsigned int irq) 65static void end_atlas_irq(unsigned int irq)
76{ 66{
77 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 67 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -80,11 +70,10 @@ static void end_atlas_irq(unsigned int irq)
80 70
81static struct irq_chip atlas_irq_type = { 71static struct irq_chip atlas_irq_type = {
82 .typename = "Atlas", 72 .typename = "Atlas",
83 .startup = startup_atlas_irq, 73 .ack = disable_atlas_irq,
84 .shutdown = shutdown_atlas_irq, 74 .mask = disable_atlas_irq,
85 .enable = enable_atlas_irq, 75 .mask_ack = disable_atlas_irq,
86 .disable = disable_atlas_irq, 76 .unmask = enable_atlas_irq,
87 .ack = mask_and_ack_atlas_irq,
88 .end = end_atlas_irq, 77 .end = end_atlas_irq,
89}; 78};
90 79
@@ -217,13 +206,8 @@ static inline void init_atlas_irqs (int base)
217 */ 206 */
218 atlas_hw0_icregs->intrsten = 0xffffffff; 207 atlas_hw0_icregs->intrsten = 0xffffffff;
219 208
220 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++) { 209 for (i = ATLAS_INT_BASE; i <= ATLAS_INT_END; i++)
221 irq_desc[i].status = IRQ_DISABLED; 210 set_irq_chip(i, &atlas_irq_type);
222 irq_desc[i].action = 0;
223 irq_desc[i].depth = 1;
224 irq_desc[i].chip = &atlas_irq_type;
225 spin_lock_init(&irq_desc[i].lock);
226 }
227} 211}
228 212
229static struct irqaction atlasirq = { 213static struct irqaction atlasirq = {
diff --git a/arch/mips/momentum/ocelot_c/cpci-irq.c b/arch/mips/momentum/ocelot_c/cpci-irq.c
index 47e3fa32b075..7723f0998944 100644
--- a/arch/mips/momentum/ocelot_c/cpci-irq.c
+++ b/arch/mips/momentum/ocelot_c/cpci-irq.c
@@ -66,39 +66,6 @@ static inline void unmask_cpci_irq(unsigned int irq)
66} 66}
67 67
68/* 68/*
69 * Enables the IRQ in the FPGA
70 */
71static void enable_cpci_irq(unsigned int irq)
72{
73 unmask_cpci_irq(irq);
74}
75
76/*
77 * Initialize the IRQ in the FPGA
78 */
79static unsigned int startup_cpci_irq(unsigned int irq)
80{
81 unmask_cpci_irq(irq);
82 return 0;
83}
84
85/*
86 * Disables the IRQ in the FPGA
87 */
88static void disable_cpci_irq(unsigned int irq)
89{
90 mask_cpci_irq(irq);
91}
92
93/*
94 * Masks and ACKs an IRQ
95 */
96static void mask_and_ack_cpci_irq(unsigned int irq)
97{
98 mask_cpci_irq(irq);
99}
100
101/*
102 * End IRQ processing 69 * End IRQ processing
103 */ 70 */
104static void end_cpci_irq(unsigned int irq) 71static void end_cpci_irq(unsigned int irq)
@@ -125,15 +92,12 @@ void ll_cpci_irq(void)
125 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE); 92 do_IRQ(ls1bit8(irq_src) + CPCI_IRQ_BASE);
126} 93}
127 94
128#define shutdown_cpci_irq disable_cpci_irq
129
130struct irq_chip cpci_irq_type = { 95struct irq_chip cpci_irq_type = {
131 .typename = "CPCI/FPGA", 96 .typename = "CPCI/FPGA",
132 .startup = startup_cpci_irq, 97 .ack = mask_cpci_irq,
133 .shutdown = shutdown_cpci_irq, 98 .mask = mask_cpci_irq,
134 .enable = enable_cpci_irq, 99 .mask_ack = mask_cpci_irq,
135 .disable = disable_cpci_irq, 100 .unmask = unmask_cpci_irq,
136 .ack = mask_and_ack_cpci_irq,
137 .end = end_cpci_irq, 101 .end = end_cpci_irq,
138}; 102};
139 103
@@ -141,11 +105,6 @@ void cpci_irq_init(void)
141{ 105{
142 int i; 106 int i;
143 107
144 /* Reset irq handlers pointers to NULL */ 108 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++)
145 for (i = CPCI_IRQ_BASE; i < (CPCI_IRQ_BASE + 8); i++) { 109 set_irq_chip(i, &cpci_irq_type);
146 irq_desc[i].status = IRQ_DISABLED;
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 2;
149 irq_desc[i].chip = &cpci_irq_type;
150 }
151} 110}
diff --git a/arch/mips/momentum/ocelot_c/uart-irq.c b/arch/mips/momentum/ocelot_c/uart-irq.c
index 510257dc205a..72faf81b36cc 100644
--- a/arch/mips/momentum/ocelot_c/uart-irq.c
+++ b/arch/mips/momentum/ocelot_c/uart-irq.c
@@ -60,39 +60,6 @@ static inline void unmask_uart_irq(unsigned int irq)
60} 60}
61 61
62/* 62/*
63 * Enables the IRQ in the FPGA
64 */
65static void enable_uart_irq(unsigned int irq)
66{
67 unmask_uart_irq(irq);
68}
69
70/*
71 * Initialize the IRQ in the FPGA
72 */
73static unsigned int startup_uart_irq(unsigned int irq)
74{
75 unmask_uart_irq(irq);
76 return 0;
77}
78
79/*
80 * Disables the IRQ in the FPGA
81 */
82static void disable_uart_irq(unsigned int irq)
83{
84 mask_uart_irq(irq);
85}
86
87/*
88 * Masks and ACKs an IRQ
89 */
90static void mask_and_ack_uart_irq(unsigned int irq)
91{
92 mask_uart_irq(irq);
93}
94
95/*
96 * End IRQ processing 63 * End IRQ processing
97 */ 64 */
98static void end_uart_irq(unsigned int irq) 65static void end_uart_irq(unsigned int irq)
@@ -118,28 +85,17 @@ void ll_uart_irq(void)
118 do_IRQ(ls1bit8(irq_src) + 74); 85 do_IRQ(ls1bit8(irq_src) + 74);
119} 86}
120 87
121#define shutdown_uart_irq disable_uart_irq
122
123struct irq_chip uart_irq_type = { 88struct irq_chip uart_irq_type = {
124 .typename = "UART/FPGA", 89 .typename = "UART/FPGA",
125 .startup = startup_uart_irq, 90 .ack = mask_uart_irq,
126 .shutdown = shutdown_uart_irq, 91 .mask = mask_uart_irq,
127 .enable = enable_uart_irq, 92 .mask_ack = mask_uart_irq,
128 .disable = disable_uart_irq, 93 .unmask = unmask_uart_irq,
129 .ack = mask_and_ack_uart_irq,
130 .end = end_uart_irq, 94 .end = end_uart_irq,
131}; 95};
132 96
133void uart_irq_init(void) 97void uart_irq_init(void)
134{ 98{
135 /* Reset irq handlers pointers to NULL */ 99 set_irq_chip(80, &uart_irq_type);
136 irq_desc[80].status = IRQ_DISABLED; 100 set_irq_chip(81, &uart_irq_type);
137 irq_desc[80].action = 0;
138 irq_desc[80].depth = 2;
139 irq_desc[80].chip = &uart_irq_type;
140
141 irq_desc[81].status = IRQ_DISABLED;
142 irq_desc[81].action = 0;
143 irq_desc[81].depth = 2;
144 irq_desc[81].chip = &uart_irq_type;
145} 101}
diff --git a/arch/mips/philips/pnx8550/common/int.c b/arch/mips/philips/pnx8550/common/int.c
index 710611615ca2..e4bf494dd435 100644
--- a/arch/mips/philips/pnx8550/common/int.c
+++ b/arch/mips/philips/pnx8550/common/int.c
@@ -38,8 +38,6 @@
38#include <int.h> 38#include <int.h>
39#include <uart.h> 39#include <uart.h>
40 40
41static DEFINE_SPINLOCK(irq_lock);
42
43/* default prio for interrupts */ 41/* default prio for interrupts */
44/* first one is a no-no so therefore always prio 0 (disabled) */ 42/* first one is a no-no so therefore always prio 0 (disabled) */
45static char gic_prio[PNX8550_INT_GIC_TOTINT] = { 43static char gic_prio[PNX8550_INT_GIC_TOTINT] = {
@@ -149,38 +147,6 @@ static inline void unmask_irq(unsigned int irq_nr)
149 } 147 }
150} 148}
151 149
152#define pnx8550_disable pnx8550_ack
153static void pnx8550_ack(unsigned int irq)
154{
155 unsigned long flags;
156
157 spin_lock_irqsave(&irq_lock, flags);
158 mask_irq(irq);
159 spin_unlock_irqrestore(&irq_lock, flags);
160}
161
162#define pnx8550_enable pnx8550_unmask
163static void pnx8550_unmask(unsigned int irq)
164{
165 unsigned long flags;
166
167 spin_lock_irqsave(&irq_lock, flags);
168 unmask_irq(irq);
169 spin_unlock_irqrestore(&irq_lock, flags);
170}
171
172static unsigned int startup_irq(unsigned int irq_nr)
173{
174 pnx8550_unmask(irq_nr);
175 return 0;
176}
177
178static void shutdown_irq(unsigned int irq_nr)
179{
180 pnx8550_ack(irq_nr);
181 return;
182}
183
184int pnx8550_set_gic_priority(int irq, int priority) 150int pnx8550_set_gic_priority(int irq, int priority)
185{ 151{
186 int gic_irq = irq-PNX8550_INT_GIC_MIN; 152 int gic_irq = irq-PNX8550_INT_GIC_MIN;
@@ -192,26 +158,19 @@ int pnx8550_set_gic_priority(int irq, int priority)
192 return prev_priority; 158 return prev_priority;
193} 159}
194 160
195static inline void mask_and_ack_level_irq(unsigned int irq)
196{
197 pnx8550_disable(irq);
198 return;
199}
200
201static void end_irq(unsigned int irq) 161static void end_irq(unsigned int irq)
202{ 162{
203 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) { 163 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
204 pnx8550_enable(irq); 164 unmask_irq(irq);
205 } 165 }
206} 166}
207 167
208static struct irq_chip level_irq_type = { 168static struct irq_chip level_irq_type = {
209 .typename = "PNX Level IRQ", 169 .typename = "PNX Level IRQ",
210 .startup = startup_irq, 170 .ack = mask_irq,
211 .shutdown = shutdown_irq, 171 .mask = mask_irq,
212 .enable = pnx8550_enable, 172 .mask_ack = mask_irq,
213 .disable = pnx8550_disable, 173 .unmask = unmask_irq,
214 .ack = mask_and_ack_level_irq,
215 .end = end_irq, 174 .end = end_irq,
216}; 175};
217 176
@@ -233,8 +192,8 @@ void __init arch_init_irq(void)
233 int configPR; 192 int configPR;
234 193
235 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) { 194 for (i = 0; i < PNX8550_INT_CP0_TOTINT; i++) {
236 irq_desc[i].chip = &level_irq_type; 195 set_irq_chip(i, &level_irq_type);
237 pnx8550_ack(i); /* mask the irq just in case */ 196 mask_irq(i); /* mask the irq just in case */
238 } 197 }
239 198
240 /* init of GIC/IPC interrupts */ 199 /* init of GIC/IPC interrupts */
@@ -270,7 +229,7 @@ void __init arch_init_irq(void)
270 /* mask/priority is still 0 so we will not get any 229 /* mask/priority is still 0 so we will not get any
271 * interrupts until it is unmasked */ 230 * interrupts until it is unmasked */
272 231
273 irq_desc[i].chip = &level_irq_type; 232 set_irq_chip(i, &level_irq_type);
274 } 233 }
275 234
276 /* Priority level 0 */ 235 /* Priority level 0 */
@@ -279,20 +238,19 @@ void __init arch_init_irq(void)
279 /* Set int vector table address */ 238 /* Set int vector table address */
280 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0; 239 PNX8550_GIC_VECTOR_0 = PNX8550_GIC_VECTOR_1 = 0;
281 240
282 irq_desc[MIPS_CPU_GIC_IRQ].chip = &level_irq_type; 241 set_irq_chip(MIPS_CPU_GIC_IRQ, &level_irq_type);
283 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action); 242 setup_irq(MIPS_CPU_GIC_IRQ, &gic_action);
284 243
285 /* init of Timer interrupts */ 244 /* init of Timer interrupts */
286 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++) { 245 for (i = PNX8550_INT_TIMER_MIN; i <= PNX8550_INT_TIMER_MAX; i++)
287 irq_desc[i].chip = &level_irq_type; 246 set_irq_chip(i, &level_irq_type);
288 }
289 247
290 /* Stop Timer 1-3 */ 248 /* Stop Timer 1-3 */
291 configPR = read_c0_config7(); 249 configPR = read_c0_config7();
292 configPR |= 0x00000038; 250 configPR |= 0x00000038;
293 write_c0_config7(configPR); 251 write_c0_config7(configPR);
294 252
295 irq_desc[MIPS_CPU_TIMER_IRQ].chip = &level_irq_type; 253 set_irq_chip(MIPS_CPU_TIMER_IRQ, &level_irq_type);
296 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action); 254 setup_irq(MIPS_CPU_TIMER_IRQ, &timer_action);
297} 255}
298 256
diff --git a/arch/mips/sgi-ip22/ip22-eisa.c b/arch/mips/sgi-ip22/ip22-eisa.c
index 0d18ed47c47a..a1a9af6da7bf 100644
--- a/arch/mips/sgi-ip22/ip22-eisa.c
+++ b/arch/mips/sgi-ip22/ip22-eisa.c
@@ -95,16 +95,11 @@ static irqreturn_t ip22_eisa_intr(int irq, void *dev_id)
95 95
96static void enable_eisa1_irq(unsigned int irq) 96static void enable_eisa1_irq(unsigned int irq)
97{ 97{
98 unsigned long flags;
99 u8 mask; 98 u8 mask;
100 99
101 local_irq_save(flags);
102
103 mask = inb(EISA_INT1_MASK); 100 mask = inb(EISA_INT1_MASK);
104 mask &= ~((u8) (1 << irq)); 101 mask &= ~((u8) (1 << irq));
105 outb(mask, EISA_INT1_MASK); 102 outb(mask, EISA_INT1_MASK);
106
107 local_irq_restore(flags);
108} 103}
109 104
110static unsigned int startup_eisa1_irq(unsigned int irq) 105static unsigned int startup_eisa1_irq(unsigned int irq)
@@ -130,8 +125,6 @@ static void disable_eisa1_irq(unsigned int irq)
130 outb(mask, EISA_INT1_MASK); 125 outb(mask, EISA_INT1_MASK);
131} 126}
132 127
133#define shutdown_eisa1_irq disable_eisa1_irq
134
135static void mask_and_ack_eisa1_irq(unsigned int irq) 128static void mask_and_ack_eisa1_irq(unsigned int irq)
136{ 129{
137 disable_eisa1_irq(irq); 130 disable_eisa1_irq(irq);
@@ -148,25 +141,20 @@ static void end_eisa1_irq(unsigned int irq)
148static struct irq_chip ip22_eisa1_irq_type = { 141static struct irq_chip ip22_eisa1_irq_type = {
149 .typename = "IP22 EISA", 142 .typename = "IP22 EISA",
150 .startup = startup_eisa1_irq, 143 .startup = startup_eisa1_irq,
151 .shutdown = shutdown_eisa1_irq,
152 .enable = enable_eisa1_irq,
153 .disable = disable_eisa1_irq,
154 .ack = mask_and_ack_eisa1_irq, 144 .ack = mask_and_ack_eisa1_irq,
145 .mask = disable_eisa1_irq,
146 .mask_ack = mask_and_ack_eisa1_irq,
147 .unmask = enable_eisa1_irq,
155 .end = end_eisa1_irq, 148 .end = end_eisa1_irq,
156}; 149};
157 150
158static void enable_eisa2_irq(unsigned int irq) 151static void enable_eisa2_irq(unsigned int irq)
159{ 152{
160 unsigned long flags;
161 u8 mask; 153 u8 mask;
162 154
163 local_irq_save(flags);
164
165 mask = inb(EISA_INT2_MASK); 155 mask = inb(EISA_INT2_MASK);
166 mask &= ~((u8) (1 << (irq - 8))); 156 mask &= ~((u8) (1 << (irq - 8)));
167 outb(mask, EISA_INT2_MASK); 157 outb(mask, EISA_INT2_MASK);
168
169 local_irq_restore(flags);
170} 158}
171 159
172static unsigned int startup_eisa2_irq(unsigned int irq) 160static unsigned int startup_eisa2_irq(unsigned int irq)
@@ -192,8 +180,6 @@ static void disable_eisa2_irq(unsigned int irq)
192 outb(mask, EISA_INT2_MASK); 180 outb(mask, EISA_INT2_MASK);
193} 181}
194 182
195#define shutdown_eisa2_irq disable_eisa2_irq
196
197static void mask_and_ack_eisa2_irq(unsigned int irq) 183static void mask_and_ack_eisa2_irq(unsigned int irq)
198{ 184{
199 disable_eisa2_irq(irq); 185 disable_eisa2_irq(irq);
@@ -210,10 +196,10 @@ static void end_eisa2_irq(unsigned int irq)
210static struct irq_chip ip22_eisa2_irq_type = { 196static struct irq_chip ip22_eisa2_irq_type = {
211 .typename = "IP22 EISA", 197 .typename = "IP22 EISA",
212 .startup = startup_eisa2_irq, 198 .startup = startup_eisa2_irq,
213 .shutdown = shutdown_eisa2_irq,
214 .enable = enable_eisa2_irq,
215 .disable = disable_eisa2_irq,
216 .ack = mask_and_ack_eisa2_irq, 199 .ack = mask_and_ack_eisa2_irq,
200 .mask = disable_eisa2_irq,
201 .mask_ack = mask_and_ack_eisa2_irq,
202 .unmask = enable_eisa2_irq,
217 .end = end_eisa2_irq, 203 .end = end_eisa2_irq,
218}; 204};
219 205
@@ -275,13 +261,10 @@ int __init ip22_eisa_init(void)
275 outb(0, EISA_DMA2_WRITE_SINGLE); 261 outb(0, EISA_DMA2_WRITE_SINGLE);
276 262
277 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) { 263 for (i = SGINT_EISA; i < (SGINT_EISA + EISA_MAX_IRQ); i++) {
278 irq_desc[i].status = IRQ_DISABLED;
279 irq_desc[i].action = 0;
280 irq_desc[i].depth = 1;
281 if (i < (SGINT_EISA + 8)) 264 if (i < (SGINT_EISA + 8))
282 irq_desc[i].chip = &ip22_eisa1_irq_type; 265 set_irq_chip(i, &ip22_eisa1_irq_type);
283 else 266 else
284 irq_desc[i].chip = &ip22_eisa2_irq_type; 267 set_irq_chip(i, &ip22_eisa2_irq_type);
285 } 268 }
286 269
287 /* Cannot use request_irq because of kmalloc not being ready at such 270 /* Cannot use request_irq because of kmalloc not being ready at such
diff --git a/arch/mips/sgi-ip22/ip22-int.c b/arch/mips/sgi-ip22/ip22-int.c
index af518898eaa1..8e2074b4ce43 100644
--- a/arch/mips/sgi-ip22/ip22-int.c
+++ b/arch/mips/sgi-ip22/ip22-int.c
@@ -40,34 +40,17 @@ extern int ip22_eisa_init(void);
40 40
41static void enable_local0_irq(unsigned int irq) 41static void enable_local0_irq(unsigned int irq)
42{ 42{
43 unsigned long flags;
44
45 local_irq_save(flags);
46 /* don't allow mappable interrupt to be enabled from setup_irq, 43 /* don't allow mappable interrupt to be enabled from setup_irq,
47 * we have our own way to do so */ 44 * we have our own way to do so */
48 if (irq != SGI_MAP_0_IRQ) 45 if (irq != SGI_MAP_0_IRQ)
49 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0)); 46 sgint->imask0 |= (1 << (irq - SGINT_LOCAL0));
50 local_irq_restore(flags);
51}
52
53static unsigned int startup_local0_irq(unsigned int irq)
54{
55 enable_local0_irq(irq);
56 return 0; /* Never anything pending */
57} 47}
58 48
59static void disable_local0_irq(unsigned int irq) 49static void disable_local0_irq(unsigned int irq)
60{ 50{
61 unsigned long flags;
62
63 local_irq_save(flags);
64 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0)); 51 sgint->imask0 &= ~(1 << (irq - SGINT_LOCAL0));
65 local_irq_restore(flags);
66} 52}
67 53
68#define shutdown_local0_irq disable_local0_irq
69#define mask_and_ack_local0_irq disable_local0_irq
70
71static void end_local0_irq (unsigned int irq) 54static void end_local0_irq (unsigned int irq)
72{ 55{
73 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 56 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -76,44 +59,26 @@ static void end_local0_irq (unsigned int irq)
76 59
77static struct irq_chip ip22_local0_irq_type = { 60static struct irq_chip ip22_local0_irq_type = {
78 .typename = "IP22 local 0", 61 .typename = "IP22 local 0",
79 .startup = startup_local0_irq, 62 .ack = disable_local0_irq,
80 .shutdown = shutdown_local0_irq, 63 .mask = disable_local0_irq,
81 .enable = enable_local0_irq, 64 .mask_ack = disable_local0_irq,
82 .disable = disable_local0_irq, 65 .unmask = enable_local0_irq,
83 .ack = mask_and_ack_local0_irq,
84 .end = end_local0_irq, 66 .end = end_local0_irq,
85}; 67};
86 68
87static void enable_local1_irq(unsigned int irq) 69static void enable_local1_irq(unsigned int irq)
88{ 70{
89 unsigned long flags;
90
91 local_irq_save(flags);
92 /* don't allow mappable interrupt to be enabled from setup_irq, 71 /* don't allow mappable interrupt to be enabled from setup_irq,
93 * we have our own way to do so */ 72 * we have our own way to do so */
94 if (irq != SGI_MAP_1_IRQ) 73 if (irq != SGI_MAP_1_IRQ)
95 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1)); 74 sgint->imask1 |= (1 << (irq - SGINT_LOCAL1));
96 local_irq_restore(flags);
97}
98
99static unsigned int startup_local1_irq(unsigned int irq)
100{
101 enable_local1_irq(irq);
102 return 0; /* Never anything pending */
103} 75}
104 76
105void disable_local1_irq(unsigned int irq) 77void disable_local1_irq(unsigned int irq)
106{ 78{
107 unsigned long flags;
108
109 local_irq_save(flags);
110 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1)); 79 sgint->imask1 &= ~(1 << (irq - SGINT_LOCAL1));
111 local_irq_restore(flags);
112} 80}
113 81
114#define shutdown_local1_irq disable_local1_irq
115#define mask_and_ack_local1_irq disable_local1_irq
116
117static void end_local1_irq (unsigned int irq) 82static void end_local1_irq (unsigned int irq)
118{ 83{
119 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 84 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -122,44 +87,26 @@ static void end_local1_irq (unsigned int irq)
122 87
123static struct irq_chip ip22_local1_irq_type = { 88static struct irq_chip ip22_local1_irq_type = {
124 .typename = "IP22 local 1", 89 .typename = "IP22 local 1",
125 .startup = startup_local1_irq, 90 .ack = disable_local1_irq,
126 .shutdown = shutdown_local1_irq, 91 .mask = disable_local1_irq,
127 .enable = enable_local1_irq, 92 .mask_ack = disable_local1_irq,
128 .disable = disable_local1_irq, 93 .unmask = enable_local1_irq,
129 .ack = mask_and_ack_local1_irq,
130 .end = end_local1_irq, 94 .end = end_local1_irq,
131}; 95};
132 96
133static void enable_local2_irq(unsigned int irq) 97static void enable_local2_irq(unsigned int irq)
134{ 98{
135 unsigned long flags;
136
137 local_irq_save(flags);
138 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 99 sgint->imask0 |= (1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
139 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2)); 100 sgint->cmeimask0 |= (1 << (irq - SGINT_LOCAL2));
140 local_irq_restore(flags);
141}
142
143static unsigned int startup_local2_irq(unsigned int irq)
144{
145 enable_local2_irq(irq);
146 return 0; /* Never anything pending */
147} 101}
148 102
149void disable_local2_irq(unsigned int irq) 103void disable_local2_irq(unsigned int irq)
150{ 104{
151 unsigned long flags;
152
153 local_irq_save(flags);
154 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2)); 105 sgint->cmeimask0 &= ~(1 << (irq - SGINT_LOCAL2));
155 if (!sgint->cmeimask0) 106 if (!sgint->cmeimask0)
156 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0)); 107 sgint->imask0 &= ~(1 << (SGI_MAP_0_IRQ - SGINT_LOCAL0));
157 local_irq_restore(flags);
158} 108}
159 109
160#define shutdown_local2_irq disable_local2_irq
161#define mask_and_ack_local2_irq disable_local2_irq
162
163static void end_local2_irq (unsigned int irq) 110static void end_local2_irq (unsigned int irq)
164{ 111{
165 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 112 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -168,44 +115,26 @@ static void end_local2_irq (unsigned int irq)
168 115
169static struct irq_chip ip22_local2_irq_type = { 116static struct irq_chip ip22_local2_irq_type = {
170 .typename = "IP22 local 2", 117 .typename = "IP22 local 2",
171 .startup = startup_local2_irq, 118 .ack = disable_local2_irq,
172 .shutdown = shutdown_local2_irq, 119 .mask = disable_local2_irq,
173 .enable = enable_local2_irq, 120 .mask_ack = disable_local2_irq,
174 .disable = disable_local2_irq, 121 .unmask = enable_local2_irq,
175 .ack = mask_and_ack_local2_irq,
176 .end = end_local2_irq, 122 .end = end_local2_irq,
177}; 123};
178 124
179static void enable_local3_irq(unsigned int irq) 125static void enable_local3_irq(unsigned int irq)
180{ 126{
181 unsigned long flags;
182
183 local_irq_save(flags);
184 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 127 sgint->imask1 |= (1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
185 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3)); 128 sgint->cmeimask1 |= (1 << (irq - SGINT_LOCAL3));
186 local_irq_restore(flags);
187}
188
189static unsigned int startup_local3_irq(unsigned int irq)
190{
191 enable_local3_irq(irq);
192 return 0; /* Never anything pending */
193} 129}
194 130
195void disable_local3_irq(unsigned int irq) 131void disable_local3_irq(unsigned int irq)
196{ 132{
197 unsigned long flags;
198
199 local_irq_save(flags);
200 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3)); 133 sgint->cmeimask1 &= ~(1 << (irq - SGINT_LOCAL3));
201 if (!sgint->cmeimask1) 134 if (!sgint->cmeimask1)
202 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1)); 135 sgint->imask1 &= ~(1 << (SGI_MAP_1_IRQ - SGINT_LOCAL1));
203 local_irq_restore(flags);
204} 136}
205 137
206#define shutdown_local3_irq disable_local3_irq
207#define mask_and_ack_local3_irq disable_local3_irq
208
209static void end_local3_irq (unsigned int irq) 138static void end_local3_irq (unsigned int irq)
210{ 139{
211 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 140 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -214,11 +143,10 @@ static void end_local3_irq (unsigned int irq)
214 143
215static struct irq_chip ip22_local3_irq_type = { 144static struct irq_chip ip22_local3_irq_type = {
216 .typename = "IP22 local 3", 145 .typename = "IP22 local 3",
217 .startup = startup_local3_irq, 146 .ack = disable_local3_irq,
218 .shutdown = shutdown_local3_irq, 147 .mask = disable_local3_irq,
219 .enable = enable_local3_irq, 148 .mask_ack = disable_local3_irq,
220 .disable = disable_local3_irq, 149 .unmask = enable_local3_irq,
221 .ack = mask_and_ack_local3_irq,
222 .end = end_local3_irq, 150 .end = end_local3_irq,
223}; 151};
224 152
@@ -430,10 +358,7 @@ void __init arch_init_irq(void)
430 else 358 else
431 handler = &ip22_local3_irq_type; 359 handler = &ip22_local3_irq_type;
432 360
433 irq_desc[i].status = IRQ_DISABLED; 361 set_irq_chip(i, handler);
434 irq_desc[i].action = 0;
435 irq_desc[i].depth = 1;
436 irq_desc[i].chip = handler;
437 } 362 }
438 363
439 /* vector handler. this register the IRQ as non-sharable */ 364 /* vector handler. this register the IRQ as non-sharable */
diff --git a/arch/mips/sgi-ip27/ip27-irq.c b/arch/mips/sgi-ip27/ip27-irq.c
index 270ecd3e6b4a..824320281a3a 100644
--- a/arch/mips/sgi-ip27/ip27-irq.c
+++ b/arch/mips/sgi-ip27/ip27-irq.c
@@ -332,11 +332,6 @@ static inline void disable_bridge_irq(unsigned int irq)
332 intr_disconnect_level(cpu, swlevel); 332 intr_disconnect_level(cpu, swlevel);
333} 333}
334 334
335static void mask_and_ack_bridge_irq(unsigned int irq)
336{
337 disable_bridge_irq(irq);
338}
339
340static void end_bridge_irq(unsigned int irq) 335static void end_bridge_irq(unsigned int irq)
341{ 336{
342 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) && 337 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)) &&
@@ -348,18 +343,16 @@ static struct irq_chip bridge_irq_type = {
348 .typename = "bridge", 343 .typename = "bridge",
349 .startup = startup_bridge_irq, 344 .startup = startup_bridge_irq,
350 .shutdown = shutdown_bridge_irq, 345 .shutdown = shutdown_bridge_irq,
351 .enable = enable_bridge_irq, 346 .ack = disable_bridge_irq,
352 .disable = disable_bridge_irq, 347 .mask = disable_bridge_irq,
353 .ack = mask_and_ack_bridge_irq, 348 .mask_ack = disable_bridge_irq,
349 .unmask = enable_bridge_irq,
354 .end = end_bridge_irq, 350 .end = end_bridge_irq,
355}; 351};
356 352
357void __devinit register_bridge_irq(unsigned int irq) 353void __devinit register_bridge_irq(unsigned int irq)
358{ 354{
359 irq_desc[irq].status = IRQ_DISABLED; 355 set_irq_chip(irq, &bridge_irq_type);
360 irq_desc[irq].action = 0;
361 irq_desc[irq].depth = 1;
362 irq_desc[irq].chip = &bridge_irq_type;
363} 356}
364 357
365int __devinit request_bridge_irq(struct bridge_controller *bc) 358int __devinit request_bridge_irq(struct bridge_controller *bc)
diff --git a/arch/mips/sgi-ip27/ip27-timer.c b/arch/mips/sgi-ip27/ip27-timer.c
index 5e82a268e3c9..86ba7fc10c38 100644
--- a/arch/mips/sgi-ip27/ip27-timer.c
+++ b/arch/mips/sgi-ip27/ip27-timer.c
@@ -172,15 +172,6 @@ static __init unsigned long get_m48t35_time(void)
172 return mktime(year, month, date, hour, min, sec); 172 return mktime(year, month, date, hour, min, sec);
173} 173}
174 174
175static unsigned int startup_rt_irq(unsigned int irq)
176{
177 return 0;
178}
179
180static void shutdown_rt_irq(unsigned int irq)
181{
182}
183
184static void enable_rt_irq(unsigned int irq) 175static void enable_rt_irq(unsigned int irq)
185{ 176{
186} 177}
@@ -189,21 +180,16 @@ static void disable_rt_irq(unsigned int irq)
189{ 180{
190} 181}
191 182
192static void mask_and_ack_rt(unsigned int irq)
193{
194}
195
196static void end_rt_irq(unsigned int irq) 183static void end_rt_irq(unsigned int irq)
197{ 184{
198} 185}
199 186
200static struct irq_chip rt_irq_type = { 187static struct irq_chip rt_irq_type = {
201 .typename = "SN HUB RT timer", 188 .typename = "SN HUB RT timer",
202 .startup = startup_rt_irq, 189 .ack = disable_rt_irq,
203 .shutdown = shutdown_rt_irq, 190 .mask = disable_rt_irq,
204 .enable = enable_rt_irq, 191 .mask_ack = disable_rt_irq,
205 .disable = disable_rt_irq, 192 .unmask = enable_rt_irq,
206 .ack = mask_and_ack_rt,
207 .end = end_rt_irq, 193 .end = end_rt_irq,
208}; 194};
209 195
@@ -221,10 +207,7 @@ void __init plat_timer_setup(struct irqaction *irq)
221 if (irqno < 0) 207 if (irqno < 0)
222 panic("Can't allocate interrupt number for timer interrupt"); 208 panic("Can't allocate interrupt number for timer interrupt");
223 209
224 irq_desc[irqno].status = IRQ_DISABLED; 210 set_irq_chip(irqno, &rt_irq_type);
225 irq_desc[irqno].action = NULL;
226 irq_desc[irqno].depth = 1;
227 irq_desc[irqno].chip = &rt_irq_type;
228 211
229 /* over-write the handler, we use our own way */ 212 /* over-write the handler, we use our own way */
230 irq->handler = no_action; 213 irq->handler = no_action;
diff --git a/arch/mips/sgi-ip32/ip32-irq.c b/arch/mips/sgi-ip32/ip32-irq.c
index c9acadd0846b..ae063864c026 100644
--- a/arch/mips/sgi-ip32/ip32-irq.c
+++ b/arch/mips/sgi-ip32/ip32-irq.c
@@ -113,12 +113,6 @@ static void inline flush_mace_bus(void)
113 * is quite different anyway. 113 * is quite different anyway.
114 */ 114 */
115 115
116/*
117 * IRQ spinlock - Ralf says not to disable CPU interrupts,
118 * and I think he knows better.
119 */
120static DEFINE_SPINLOCK(ip32_irq_lock);
121
122/* Some initial interrupts to set up */ 116/* Some initial interrupts to set up */
123extern irqreturn_t crime_memerr_intr(int irq, void *dev_id); 117extern irqreturn_t crime_memerr_intr(int irq, void *dev_id);
124extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id); 118extern irqreturn_t crime_cpuerr_intr(int irq, void *dev_id);
@@ -138,12 +132,6 @@ static void enable_cpu_irq(unsigned int irq)
138 set_c0_status(STATUSF_IP7); 132 set_c0_status(STATUSF_IP7);
139} 133}
140 134
141static unsigned int startup_cpu_irq(unsigned int irq)
142{
143 enable_cpu_irq(irq);
144 return 0;
145}
146
147static void disable_cpu_irq(unsigned int irq) 135static void disable_cpu_irq(unsigned int irq)
148{ 136{
149 clear_c0_status(STATUSF_IP7); 137 clear_c0_status(STATUSF_IP7);
@@ -155,16 +143,12 @@ static void end_cpu_irq(unsigned int irq)
155 enable_cpu_irq (irq); 143 enable_cpu_irq (irq);
156} 144}
157 145
158#define shutdown_cpu_irq disable_cpu_irq
159#define mask_and_ack_cpu_irq disable_cpu_irq
160
161static struct irq_chip ip32_cpu_interrupt = { 146static struct irq_chip ip32_cpu_interrupt = {
162 .typename = "IP32 CPU", 147 .typename = "IP32 CPU",
163 .startup = startup_cpu_irq, 148 .ack = disable_cpu_irq,
164 .shutdown = shutdown_cpu_irq, 149 .mask = disable_cpu_irq,
165 .enable = enable_cpu_irq, 150 .mask_ack = disable_cpu_irq,
166 .disable = disable_cpu_irq, 151 .unmask = enable_cpu_irq,
167 .ack = mask_and_ack_cpu_irq,
168 .end = end_cpu_irq, 152 .end = end_cpu_irq,
169}; 153};
170 154
@@ -177,45 +161,27 @@ static uint64_t crime_mask;
177 161
178static void enable_crime_irq(unsigned int irq) 162static void enable_crime_irq(unsigned int irq)
179{ 163{
180 unsigned long flags;
181
182 spin_lock_irqsave(&ip32_irq_lock, flags);
183 crime_mask |= 1 << (irq - 1); 164 crime_mask |= 1 << (irq - 1);
184 crime->imask = crime_mask; 165 crime->imask = crime_mask;
185 spin_unlock_irqrestore(&ip32_irq_lock, flags);
186}
187
188static unsigned int startup_crime_irq(unsigned int irq)
189{
190 enable_crime_irq(irq);
191 return 0; /* This is probably not right; we could have pending irqs */
192} 166}
193 167
194static void disable_crime_irq(unsigned int irq) 168static void disable_crime_irq(unsigned int irq)
195{ 169{
196 unsigned long flags;
197
198 spin_lock_irqsave(&ip32_irq_lock, flags);
199 crime_mask &= ~(1 << (irq - 1)); 170 crime_mask &= ~(1 << (irq - 1));
200 crime->imask = crime_mask; 171 crime->imask = crime_mask;
201 flush_crime_bus(); 172 flush_crime_bus();
202 spin_unlock_irqrestore(&ip32_irq_lock, flags);
203} 173}
204 174
205static void mask_and_ack_crime_irq(unsigned int irq) 175static void mask_and_ack_crime_irq(unsigned int irq)
206{ 176{
207 unsigned long flags;
208
209 /* Edge triggered interrupts must be cleared. */ 177 /* Edge triggered interrupts must be cleared. */
210 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ) 178 if ((irq >= CRIME_GBE0_IRQ && irq <= CRIME_GBE3_IRQ)
211 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ) 179 || (irq >= CRIME_RE_EMPTY_E_IRQ && irq <= CRIME_RE_IDLE_E_IRQ)
212 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) { 180 || (irq >= CRIME_SOFT0_IRQ && irq <= CRIME_SOFT2_IRQ)) {
213 uint64_t crime_int; 181 uint64_t crime_int;
214 spin_lock_irqsave(&ip32_irq_lock, flags);
215 crime_int = crime->hard_int; 182 crime_int = crime->hard_int;
216 crime_int &= ~(1 << (irq - 1)); 183 crime_int &= ~(1 << (irq - 1));
217 crime->hard_int = crime_int; 184 crime->hard_int = crime_int;
218 spin_unlock_irqrestore(&ip32_irq_lock, flags);
219 } 185 }
220 disable_crime_irq(irq); 186 disable_crime_irq(irq);
221} 187}
@@ -226,15 +192,12 @@ static void end_crime_irq(unsigned int irq)
226 enable_crime_irq(irq); 192 enable_crime_irq(irq);
227} 193}
228 194
229#define shutdown_crime_irq disable_crime_irq
230
231static struct irq_chip ip32_crime_interrupt = { 195static struct irq_chip ip32_crime_interrupt = {
232 .typename = "IP32 CRIME", 196 .typename = "IP32 CRIME",
233 .startup = startup_crime_irq,
234 .shutdown = shutdown_crime_irq,
235 .enable = enable_crime_irq,
236 .disable = disable_crime_irq,
237 .ack = mask_and_ack_crime_irq, 197 .ack = mask_and_ack_crime_irq,
198 .mask = disable_crime_irq,
199 .mask_ack = mask_and_ack_crime_irq,
200 .unmask = enable_crime_irq,
238 .end = end_crime_irq, 201 .end = end_crime_irq,
239}; 202};
240 203
@@ -248,34 +211,20 @@ static unsigned long macepci_mask;
248 211
249static void enable_macepci_irq(unsigned int irq) 212static void enable_macepci_irq(unsigned int irq)
250{ 213{
251 unsigned long flags;
252
253 spin_lock_irqsave(&ip32_irq_lock, flags);
254 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9); 214 macepci_mask |= MACEPCI_CONTROL_INT(irq - 9);
255 mace->pci.control = macepci_mask; 215 mace->pci.control = macepci_mask;
256 crime_mask |= 1 << (irq - 1); 216 crime_mask |= 1 << (irq - 1);
257 crime->imask = crime_mask; 217 crime->imask = crime_mask;
258 spin_unlock_irqrestore(&ip32_irq_lock, flags);
259}
260
261static unsigned int startup_macepci_irq(unsigned int irq)
262{
263 enable_macepci_irq (irq);
264 return 0;
265} 218}
266 219
267static void disable_macepci_irq(unsigned int irq) 220static void disable_macepci_irq(unsigned int irq)
268{ 221{
269 unsigned long flags;
270
271 spin_lock_irqsave(&ip32_irq_lock, flags);
272 crime_mask &= ~(1 << (irq - 1)); 222 crime_mask &= ~(1 << (irq - 1));
273 crime->imask = crime_mask; 223 crime->imask = crime_mask;
274 flush_crime_bus(); 224 flush_crime_bus();
275 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9); 225 macepci_mask &= ~MACEPCI_CONTROL_INT(irq - 9);
276 mace->pci.control = macepci_mask; 226 mace->pci.control = macepci_mask;
277 flush_mace_bus(); 227 flush_mace_bus();
278 spin_unlock_irqrestore(&ip32_irq_lock, flags);
279} 228}
280 229
281static void end_macepci_irq(unsigned int irq) 230static void end_macepci_irq(unsigned int irq)
@@ -284,16 +233,12 @@ static void end_macepci_irq(unsigned int irq)
284 enable_macepci_irq(irq); 233 enable_macepci_irq(irq);
285} 234}
286 235
287#define shutdown_macepci_irq disable_macepci_irq
288#define mask_and_ack_macepci_irq disable_macepci_irq
289
290static struct irq_chip ip32_macepci_interrupt = { 236static struct irq_chip ip32_macepci_interrupt = {
291 .typename = "IP32 MACE PCI", 237 .typename = "IP32 MACE PCI",
292 .startup = startup_macepci_irq, 238 .ack = disable_macepci_irq,
293 .shutdown = shutdown_macepci_irq, 239 .mask = disable_macepci_irq,
294 .enable = enable_macepci_irq, 240 .mask_ack = disable_macepci_irq,
295 .disable = disable_macepci_irq, 241 .unmask = enable_macepci_irq,
296 .ack = mask_and_ack_macepci_irq,
297 .end = end_macepci_irq, 242 .end = end_macepci_irq,
298}; 243};
299 244
@@ -339,7 +284,6 @@ static unsigned long maceisa_mask;
339static void enable_maceisa_irq (unsigned int irq) 284static void enable_maceisa_irq (unsigned int irq)
340{ 285{
341 unsigned int crime_int = 0; 286 unsigned int crime_int = 0;
342 unsigned long flags;
343 287
344 DBG ("maceisa enable: %u\n", irq); 288 DBG ("maceisa enable: %u\n", irq);
345 289
@@ -355,26 +299,16 @@ static void enable_maceisa_irq (unsigned int irq)
355 break; 299 break;
356 } 300 }
357 DBG ("crime_int %08x enabled\n", crime_int); 301 DBG ("crime_int %08x enabled\n", crime_int);
358 spin_lock_irqsave(&ip32_irq_lock, flags);
359 crime_mask |= crime_int; 302 crime_mask |= crime_int;
360 crime->imask = crime_mask; 303 crime->imask = crime_mask;
361 maceisa_mask |= 1 << (irq - 33); 304 maceisa_mask |= 1 << (irq - 33);
362 mace->perif.ctrl.imask = maceisa_mask; 305 mace->perif.ctrl.imask = maceisa_mask;
363 spin_unlock_irqrestore(&ip32_irq_lock, flags);
364}
365
366static unsigned int startup_maceisa_irq(unsigned int irq)
367{
368 enable_maceisa_irq(irq);
369 return 0;
370} 306}
371 307
372static void disable_maceisa_irq(unsigned int irq) 308static void disable_maceisa_irq(unsigned int irq)
373{ 309{
374 unsigned int crime_int = 0; 310 unsigned int crime_int = 0;
375 unsigned long flags;
376 311
377 spin_lock_irqsave(&ip32_irq_lock, flags);
378 maceisa_mask &= ~(1 << (irq - 33)); 312 maceisa_mask &= ~(1 << (irq - 33));
379 if(!(maceisa_mask & MACEISA_AUDIO_INT)) 313 if(!(maceisa_mask & MACEISA_AUDIO_INT))
380 crime_int |= MACE_AUDIO_INT; 314 crime_int |= MACE_AUDIO_INT;
@@ -387,23 +321,20 @@ static void disable_maceisa_irq(unsigned int irq)
387 flush_crime_bus(); 321 flush_crime_bus();
388 mace->perif.ctrl.imask = maceisa_mask; 322 mace->perif.ctrl.imask = maceisa_mask;
389 flush_mace_bus(); 323 flush_mace_bus();
390 spin_unlock_irqrestore(&ip32_irq_lock, flags);
391} 324}
392 325
393static void mask_and_ack_maceisa_irq(unsigned int irq) 326static void mask_and_ack_maceisa_irq(unsigned int irq)
394{ 327{
395 unsigned long mace_int, flags; 328 unsigned long mace_int;
396 329
397 switch (irq) { 330 switch (irq) {
398 case MACEISA_PARALLEL_IRQ: 331 case MACEISA_PARALLEL_IRQ:
399 case MACEISA_SERIAL1_TDMAPR_IRQ: 332 case MACEISA_SERIAL1_TDMAPR_IRQ:
400 case MACEISA_SERIAL2_TDMAPR_IRQ: 333 case MACEISA_SERIAL2_TDMAPR_IRQ:
401 /* edge triggered */ 334 /* edge triggered */
402 spin_lock_irqsave(&ip32_irq_lock, flags);
403 mace_int = mace->perif.ctrl.istat; 335 mace_int = mace->perif.ctrl.istat;
404 mace_int &= ~(1 << (irq - 33)); 336 mace_int &= ~(1 << (irq - 33));
405 mace->perif.ctrl.istat = mace_int; 337 mace->perif.ctrl.istat = mace_int;
406 spin_unlock_irqrestore(&ip32_irq_lock, flags);
407 break; 338 break;
408 } 339 }
409 disable_maceisa_irq(irq); 340 disable_maceisa_irq(irq);
@@ -415,15 +346,12 @@ static void end_maceisa_irq(unsigned irq)
415 enable_maceisa_irq(irq); 346 enable_maceisa_irq(irq);
416} 347}
417 348
418#define shutdown_maceisa_irq disable_maceisa_irq
419
420static struct irq_chip ip32_maceisa_interrupt = { 349static struct irq_chip ip32_maceisa_interrupt = {
421 .typename = "IP32 MACE ISA", 350 .typename = "IP32 MACE ISA",
422 .startup = startup_maceisa_irq,
423 .shutdown = shutdown_maceisa_irq,
424 .enable = enable_maceisa_irq,
425 .disable = disable_maceisa_irq,
426 .ack = mask_and_ack_maceisa_irq, 351 .ack = mask_and_ack_maceisa_irq,
352 .mask = disable_maceisa_irq,
353 .mask_ack = mask_and_ack_maceisa_irq,
354 .unmask = enable_maceisa_irq,
427 .end = end_maceisa_irq, 355 .end = end_maceisa_irq,
428}; 356};
429 357
@@ -433,29 +361,15 @@ static struct irq_chip ip32_maceisa_interrupt = {
433 361
434static void enable_mace_irq(unsigned int irq) 362static void enable_mace_irq(unsigned int irq)
435{ 363{
436 unsigned long flags;
437
438 spin_lock_irqsave(&ip32_irq_lock, flags);
439 crime_mask |= 1 << (irq - 1); 364 crime_mask |= 1 << (irq - 1);
440 crime->imask = crime_mask; 365 crime->imask = crime_mask;
441 spin_unlock_irqrestore(&ip32_irq_lock, flags);
442}
443
444static unsigned int startup_mace_irq(unsigned int irq)
445{
446 enable_mace_irq(irq);
447 return 0;
448} 366}
449 367
450static void disable_mace_irq(unsigned int irq) 368static void disable_mace_irq(unsigned int irq)
451{ 369{
452 unsigned long flags;
453
454 spin_lock_irqsave(&ip32_irq_lock, flags);
455 crime_mask &= ~(1 << (irq - 1)); 370 crime_mask &= ~(1 << (irq - 1));
456 crime->imask = crime_mask; 371 crime->imask = crime_mask;
457 flush_crime_bus(); 372 flush_crime_bus();
458 spin_unlock_irqrestore(&ip32_irq_lock, flags);
459} 373}
460 374
461static void end_mace_irq(unsigned int irq) 375static void end_mace_irq(unsigned int irq)
@@ -464,16 +378,12 @@ static void end_mace_irq(unsigned int irq)
464 enable_mace_irq(irq); 378 enable_mace_irq(irq);
465} 379}
466 380
467#define shutdown_mace_irq disable_mace_irq
468#define mask_and_ack_mace_irq disable_mace_irq
469
470static struct irq_chip ip32_mace_interrupt = { 381static struct irq_chip ip32_mace_interrupt = {
471 .typename = "IP32 MACE", 382 .typename = "IP32 MACE",
472 .startup = startup_mace_irq, 383 .ack = disable_mace_irq,
473 .shutdown = shutdown_mace_irq, 384 .mask = disable_mace_irq,
474 .enable = enable_mace_irq, 385 .mask_ack = disable_mace_irq,
475 .disable = disable_mace_irq, 386 .unmask = enable_mace_irq,
476 .ack = mask_and_ack_mace_irq,
477 .end = end_mace_irq, 387 .end = end_mace_irq,
478}; 388};
479 389
@@ -586,10 +496,7 @@ void __init arch_init_irq(void)
586 else 496 else
587 controller = &ip32_maceisa_interrupt; 497 controller = &ip32_maceisa_interrupt;
588 498
589 irq_desc[irq].status = IRQ_DISABLED; 499 set_irq_chip(irq, controller);
590 irq_desc[irq].action = 0;
591 irq_desc[irq].depth = 0;
592 irq_desc[irq].chip = controller;
593 } 500 }
594 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq); 501 setup_irq(CRIME_MEMERR_IRQ, &memerr_irq);
595 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq); 502 setup_irq(CRIME_CPUERR_IRQ, &cpuerr_irq);
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 8b1f41484923..2e8f6b2e2420 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -45,11 +45,9 @@
45 */ 45 */
46 46
47 47
48#define shutdown_bcm1480_irq disable_bcm1480_irq
49static void end_bcm1480_irq(unsigned int irq); 48static void end_bcm1480_irq(unsigned int irq);
50static void enable_bcm1480_irq(unsigned int irq); 49static void enable_bcm1480_irq(unsigned int irq);
51static void disable_bcm1480_irq(unsigned int irq); 50static void disable_bcm1480_irq(unsigned int irq);
52static unsigned int startup_bcm1480_irq(unsigned int irq);
53static void ack_bcm1480_irq(unsigned int irq); 51static void ack_bcm1480_irq(unsigned int irq);
54#ifdef CONFIG_SMP 52#ifdef CONFIG_SMP
55static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask); 53static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask);
@@ -85,11 +83,10 @@ extern char sb1250_duart_present[];
85 83
86static struct irq_chip bcm1480_irq_type = { 84static struct irq_chip bcm1480_irq_type = {
87 .typename = "BCM1480-IMR", 85 .typename = "BCM1480-IMR",
88 .startup = startup_bcm1480_irq,
89 .shutdown = shutdown_bcm1480_irq,
90 .enable = enable_bcm1480_irq,
91 .disable = disable_bcm1480_irq,
92 .ack = ack_bcm1480_irq, 86 .ack = ack_bcm1480_irq,
87 .mask = disable_bcm1480_irq,
88 .mask_ack = ack_bcm1480_irq,
89 .unmask = enable_bcm1480_irq,
93 .end = end_bcm1480_irq, 90 .end = end_bcm1480_irq,
94#ifdef CONFIG_SMP 91#ifdef CONFIG_SMP
95 .set_affinity = bcm1480_set_affinity 92 .set_affinity = bcm1480_set_affinity
@@ -188,14 +185,6 @@ static void bcm1480_set_affinity(unsigned int irq, cpumask_t mask)
188 185
189/*****************************************************************************/ 186/*****************************************************************************/
190 187
191static unsigned int startup_bcm1480_irq(unsigned int irq)
192{
193 bcm1480_unmask_irq(bcm1480_irq_owner[irq], irq);
194
195 return 0; /* never anything pending */
196}
197
198
199static void disable_bcm1480_irq(unsigned int irq) 188static void disable_bcm1480_irq(unsigned int irq)
200{ 189{
201 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq); 190 bcm1480_mask_irq(bcm1480_irq_owner[irq], irq);
@@ -270,16 +259,9 @@ void __init init_bcm1480_irqs(void)
270{ 259{
271 int i; 260 int i;
272 261
273 for (i = 0; i < NR_IRQS; i++) { 262 for (i = 0; i < BCM1480_NR_IRQS; i++) {
274 irq_desc[i].status = IRQ_DISABLED; 263 set_irq_chip(i, &bcm1480_irq_type);
275 irq_desc[i].action = 0; 264 bcm1480_irq_owner[i] = 0;
276 irq_desc[i].depth = 1;
277 if (i < BCM1480_NR_IRQS) {
278 irq_desc[i].chip = &bcm1480_irq_type;
279 bcm1480_irq_owner[i] = 0;
280 } else {
281 irq_desc[i].chip = &no_irq_chip;
282 }
283 } 265 }
284} 266}
285 267
diff --git a/arch/mips/sibyte/sb1250/irq.c b/arch/mips/sibyte/sb1250/irq.c
index d5d26770daf6..82ce7533053f 100644
--- a/arch/mips/sibyte/sb1250/irq.c
+++ b/arch/mips/sibyte/sb1250/irq.c
@@ -44,11 +44,9 @@
44 */ 44 */
45 45
46 46
47#define shutdown_sb1250_irq disable_sb1250_irq
48static void end_sb1250_irq(unsigned int irq); 47static void end_sb1250_irq(unsigned int irq);
49static void enable_sb1250_irq(unsigned int irq); 48static void enable_sb1250_irq(unsigned int irq);
50static void disable_sb1250_irq(unsigned int irq); 49static void disable_sb1250_irq(unsigned int irq);
51static unsigned int startup_sb1250_irq(unsigned int irq);
52static void ack_sb1250_irq(unsigned int irq); 50static void ack_sb1250_irq(unsigned int irq);
53#ifdef CONFIG_SMP 51#ifdef CONFIG_SMP
54static void sb1250_set_affinity(unsigned int irq, cpumask_t mask); 52static void sb1250_set_affinity(unsigned int irq, cpumask_t mask);
@@ -70,11 +68,10 @@ extern char sb1250_duart_present[];
70 68
71static struct irq_chip sb1250_irq_type = { 69static struct irq_chip sb1250_irq_type = {
72 .typename = "SB1250-IMR", 70 .typename = "SB1250-IMR",
73 .startup = startup_sb1250_irq,
74 .shutdown = shutdown_sb1250_irq,
75 .enable = enable_sb1250_irq,
76 .disable = disable_sb1250_irq,
77 .ack = ack_sb1250_irq, 71 .ack = ack_sb1250_irq,
72 .mask = disable_sb1250_irq,
73 .mask_ack = ack_sb1250_irq,
74 .unmask = enable_sb1250_irq,
78 .end = end_sb1250_irq, 75 .end = end_sb1250_irq,
79#ifdef CONFIG_SMP 76#ifdef CONFIG_SMP
80 .set_affinity = sb1250_set_affinity 77 .set_affinity = sb1250_set_affinity
@@ -163,14 +160,6 @@ static void sb1250_set_affinity(unsigned int irq, cpumask_t mask)
163 160
164/*****************************************************************************/ 161/*****************************************************************************/
165 162
166static unsigned int startup_sb1250_irq(unsigned int irq)
167{
168 sb1250_unmask_irq(sb1250_irq_owner[irq], irq);
169
170 return 0; /* never anything pending */
171}
172
173
174static void disable_sb1250_irq(unsigned int irq) 163static void disable_sb1250_irq(unsigned int irq)
175{ 164{
176 sb1250_mask_irq(sb1250_irq_owner[irq], irq); 165 sb1250_mask_irq(sb1250_irq_owner[irq], irq);
@@ -239,16 +228,9 @@ void __init init_sb1250_irqs(void)
239{ 228{
240 int i; 229 int i;
241 230
242 for (i = 0; i < NR_IRQS; i++) { 231 for (i = 0; i < SB1250_NR_IRQS; i++) {
243 irq_desc[i].status = IRQ_DISABLED; 232 set_irq_chip(i, &sb1250_irq_type);
244 irq_desc[i].action = 0; 233 sb1250_irq_owner[i] = 0;
245 irq_desc[i].depth = 1;
246 if (i < SB1250_NR_IRQS) {
247 irq_desc[i].chip = &sb1250_irq_type;
248 sb1250_irq_owner[i] = 0;
249 } else {
250 irq_desc[i].chip = &no_irq_chip;
251 }
252 } 234 }
253} 235}
254 236
diff --git a/arch/mips/sni/irq.c b/arch/mips/sni/irq.c
index 48fb74a7aaec..8511bcc6d99d 100644
--- a/arch/mips/sni/irq.c
+++ b/arch/mips/sni/irq.c
@@ -11,44 +11,25 @@
11#include <linux/interrupt.h> 11#include <linux/interrupt.h>
12#include <linux/irq.h> 12#include <linux/irq.h>
13#include <linux/kernel.h> 13#include <linux/kernel.h>
14#include <linux/spinlock.h>
15 14
16#include <asm/i8259.h> 15#include <asm/i8259.h>
17#include <asm/io.h> 16#include <asm/io.h>
18#include <asm/sni.h> 17#include <asm/sni.h>
19 18
20DEFINE_SPINLOCK(pciasic_lock);
21
22static void enable_pciasic_irq(unsigned int irq) 19static void enable_pciasic_irq(unsigned int irq)
23{ 20{
24 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2); 21 unsigned int mask = 1 << (irq - PCIMT_IRQ_INT2);
25 unsigned long flags;
26 22
27 spin_lock_irqsave(&pciasic_lock, flags);
28 *(volatile u8 *) PCIMT_IRQSEL |= mask; 23 *(volatile u8 *) PCIMT_IRQSEL |= mask;
29 spin_unlock_irqrestore(&pciasic_lock, flags);
30}
31
32static unsigned int startup_pciasic_irq(unsigned int irq)
33{
34 enable_pciasic_irq(irq);
35 return 0; /* never anything pending */
36} 24}
37 25
38#define shutdown_pciasic_irq disable_pciasic_irq
39
40void disable_pciasic_irq(unsigned int irq) 26void disable_pciasic_irq(unsigned int irq)
41{ 27{
42 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2)); 28 unsigned int mask = ~(1 << (irq - PCIMT_IRQ_INT2));
43 unsigned long flags;
44 29
45 spin_lock_irqsave(&pciasic_lock, flags);
46 *(volatile u8 *) PCIMT_IRQSEL &= mask; 30 *(volatile u8 *) PCIMT_IRQSEL &= mask;
47 spin_unlock_irqrestore(&pciasic_lock, flags);
48} 31}
49 32
50#define mask_and_ack_pciasic_irq disable_pciasic_irq
51
52static void end_pciasic_irq(unsigned int irq) 33static void end_pciasic_irq(unsigned int irq)
53{ 34{
54 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS))) 35 if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
@@ -57,11 +38,10 @@ static void end_pciasic_irq(unsigned int irq)
57 38
58static struct irq_chip pciasic_irq_type = { 39static struct irq_chip pciasic_irq_type = {
59 .typename = "ASIC-PCI", 40 .typename = "ASIC-PCI",
60 .startup = startup_pciasic_irq, 41 .ack = disable_pciasic_irq,
61 .shutdown = shutdown_pciasic_irq, 42 .mask = disable_pciasic_irq,
62 .enable = enable_pciasic_irq, 43 .mask_ack = disable_pciasic_irq,
63 .disable = disable_pciasic_irq, 44 .unmask = enable_pciasic_irq,
64 .ack = mask_and_ack_pciasic_irq,
65 .end = end_pciasic_irq, 45 .end = end_pciasic_irq,
66}; 46};
67 47
@@ -178,12 +158,8 @@ asmlinkage void plat_irq_dispatch(void)
178 158
179void __init init_pciasic(void) 159void __init init_pciasic(void)
180{ 160{
181 unsigned long flags;
182
183 spin_lock_irqsave(&pciasic_lock, flags);
184 * (volatile u8 *) PCIMT_IRQSEL = 161 * (volatile u8 *) PCIMT_IRQSEL =
185 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD; 162 IT_EISA | IT_INTA | IT_INTB | IT_INTC | IT_INTD;
186 spin_unlock_irqrestore(&pciasic_lock, flags);
187} 163}
188 164
189/* 165/*
@@ -199,12 +175,8 @@ void __init arch_init_irq(void)
199 init_pciasic(); 175 init_pciasic();
200 176
201 /* Actually we've got more interrupts to handle ... */ 177 /* Actually we've got more interrupts to handle ... */
202 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++) { 178 for (i = PCIMT_IRQ_INT2; i <= PCIMT_IRQ_ETHERNET; i++)
203 irq_desc[i].status = IRQ_DISABLED; 179 set_irq_chip(i, &pciasic_irq_type);
204 irq_desc[i].action = 0;
205 irq_desc[i].depth = 1;
206 irq_desc[i].chip = &pciasic_irq_type;
207 }
208 180
209 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4); 181 change_c0_status(ST0_IM, IE_IRQ1|IE_IRQ2|IE_IRQ3|IE_IRQ4);
210} 182}
diff --git a/arch/mips/tx4927/common/tx4927_irq.c b/arch/mips/tx4927/common/tx4927_irq.c
index 8266a88a3f88..2c57ced5c68c 100644
--- a/arch/mips/tx4927/common/tx4927_irq.c
+++ b/arch/mips/tx4927/common/tx4927_irq.c
@@ -64,19 +64,13 @@
64#define TX4927_IRQ_NEST4 ( 1 << 9 ) 64#define TX4927_IRQ_NEST4 ( 1 << 9 )
65 65
66#define TX4927_IRQ_CP0_INIT ( 1 << 10 ) 66#define TX4927_IRQ_CP0_INIT ( 1 << 10 )
67#define TX4927_IRQ_CP0_STARTUP ( 1 << 11 )
68#define TX4927_IRQ_CP0_SHUTDOWN ( 1 << 12 )
69#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 ) 67#define TX4927_IRQ_CP0_ENABLE ( 1 << 13 )
70#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 ) 68#define TX4927_IRQ_CP0_DISABLE ( 1 << 14 )
71#define TX4927_IRQ_CP0_MASK ( 1 << 15 )
72#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 ) 69#define TX4927_IRQ_CP0_ENDIRQ ( 1 << 16 )
73 70
74#define TX4927_IRQ_PIC_INIT ( 1 << 20 ) 71#define TX4927_IRQ_PIC_INIT ( 1 << 20 )
75#define TX4927_IRQ_PIC_STARTUP ( 1 << 21 )
76#define TX4927_IRQ_PIC_SHUTDOWN ( 1 << 22 )
77#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 ) 72#define TX4927_IRQ_PIC_ENABLE ( 1 << 23 )
78#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 ) 73#define TX4927_IRQ_PIC_DISABLE ( 1 << 24 )
79#define TX4927_IRQ_PIC_MASK ( 1 << 25 )
80#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 ) 74#define TX4927_IRQ_PIC_ENDIRQ ( 1 << 26 )
81 75
82#define TX4927_IRQ_ALL 0xffffffff 76#define TX4927_IRQ_ALL 0xffffffff
@@ -87,18 +81,12 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
87 | TX4927_IRQ_INFO 81 | TX4927_IRQ_INFO
88 | TX4927_IRQ_WARN | TX4927_IRQ_EROR 82 | TX4927_IRQ_WARN | TX4927_IRQ_EROR
89// | TX4927_IRQ_CP0_INIT 83// | TX4927_IRQ_CP0_INIT
90// | TX4927_IRQ_CP0_STARTUP
91// | TX4927_IRQ_CP0_SHUTDOWN
92// | TX4927_IRQ_CP0_ENABLE 84// | TX4927_IRQ_CP0_ENABLE
93// | TX4927_IRQ_CP0_DISABLE 85// | TX4927_IRQ_CP0_DISABLE
94// | TX4927_IRQ_CP0_MASK
95// | TX4927_IRQ_CP0_ENDIRQ 86// | TX4927_IRQ_CP0_ENDIRQ
96// | TX4927_IRQ_PIC_INIT 87// | TX4927_IRQ_PIC_INIT
97// | TX4927_IRQ_PIC_STARTUP
98// | TX4927_IRQ_PIC_SHUTDOWN
99// | TX4927_IRQ_PIC_ENABLE 88// | TX4927_IRQ_PIC_ENABLE
100// | TX4927_IRQ_PIC_DISABLE 89// | TX4927_IRQ_PIC_DISABLE
101// | TX4927_IRQ_PIC_MASK
102// | TX4927_IRQ_PIC_ENDIRQ 90// | TX4927_IRQ_PIC_ENDIRQ
103// | TX4927_IRQ_INIT 91// | TX4927_IRQ_INIT
104// | TX4927_IRQ_NEST1 92// | TX4927_IRQ_NEST1
@@ -124,49 +112,36 @@ static const u32 tx4927_irq_debug_flag = (TX4927_IRQ_NONE
124 * Forwad definitions for all pic's 112 * Forwad definitions for all pic's
125 */ 113 */
126 114
127static unsigned int tx4927_irq_cp0_startup(unsigned int irq);
128static void tx4927_irq_cp0_shutdown(unsigned int irq);
129static void tx4927_irq_cp0_enable(unsigned int irq); 115static void tx4927_irq_cp0_enable(unsigned int irq);
130static void tx4927_irq_cp0_disable(unsigned int irq); 116static void tx4927_irq_cp0_disable(unsigned int irq);
131static void tx4927_irq_cp0_mask_and_ack(unsigned int irq);
132static void tx4927_irq_cp0_end(unsigned int irq); 117static void tx4927_irq_cp0_end(unsigned int irq);
133 118
134static unsigned int tx4927_irq_pic_startup(unsigned int irq);
135static void tx4927_irq_pic_shutdown(unsigned int irq);
136static void tx4927_irq_pic_enable(unsigned int irq); 119static void tx4927_irq_pic_enable(unsigned int irq);
137static void tx4927_irq_pic_disable(unsigned int irq); 120static void tx4927_irq_pic_disable(unsigned int irq);
138static void tx4927_irq_pic_mask_and_ack(unsigned int irq);
139static void tx4927_irq_pic_end(unsigned int irq); 121static void tx4927_irq_pic_end(unsigned int irq);
140 122
141/* 123/*
142 * Kernel structs for all pic's 124 * Kernel structs for all pic's
143 */ 125 */
144 126
145static DEFINE_SPINLOCK(tx4927_cp0_lock);
146static DEFINE_SPINLOCK(tx4927_pic_lock);
147
148#define TX4927_CP0_NAME "TX4927-CP0" 127#define TX4927_CP0_NAME "TX4927-CP0"
149static struct irq_chip tx4927_irq_cp0_type = { 128static struct irq_chip tx4927_irq_cp0_type = {
150 .typename = TX4927_CP0_NAME, 129 .typename = TX4927_CP0_NAME,
151 .startup = tx4927_irq_cp0_startup, 130 .ack = tx4927_irq_cp0_disable,
152 .shutdown = tx4927_irq_cp0_shutdown, 131 .mask = tx4927_irq_cp0_disable,
153 .enable = tx4927_irq_cp0_enable, 132 .mask_ack = tx4927_irq_cp0_disable,
154 .disable = tx4927_irq_cp0_disable, 133 .unmask = tx4927_irq_cp0_enable,
155 .ack = tx4927_irq_cp0_mask_and_ack,
156 .end = tx4927_irq_cp0_end, 134 .end = tx4927_irq_cp0_end,
157 .set_affinity = NULL
158}; 135};
159 136
160#define TX4927_PIC_NAME "TX4927-PIC" 137#define TX4927_PIC_NAME "TX4927-PIC"
161static struct irq_chip tx4927_irq_pic_type = { 138static struct irq_chip tx4927_irq_pic_type = {
162 .typename = TX4927_PIC_NAME, 139 .typename = TX4927_PIC_NAME,
163 .startup = tx4927_irq_pic_startup, 140 .ack = tx4927_irq_pic_disable,
164 .shutdown = tx4927_irq_pic_shutdown, 141 .mask = tx4927_irq_pic_disable,
165 .enable = tx4927_irq_pic_enable, 142 .mask_ack = tx4927_irq_pic_disable,
166 .disable = tx4927_irq_pic_disable, 143 .unmask = tx4927_irq_pic_enable,
167 .ack = tx4927_irq_pic_mask_and_ack,
168 .end = tx4927_irq_pic_end, 144 .end = tx4927_irq_pic_end,
169 .set_affinity = NULL
170}; 145};
171 146
172#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL } 147#define TX4927_PIC_ACTION(s) { no_action, 0, CPU_MASK_NONE, s, NULL, NULL }
@@ -211,8 +186,6 @@ tx4927_irq_cp0_modify(unsigned cp0_reg, unsigned clr_bits, unsigned set_bits)
211 break; 186 break;
212 } 187 }
213 } 188 }
214
215 return;
216} 189}
217 190
218static void __init tx4927_irq_cp0_init(void) 191static void __init tx4927_irq_cp0_init(void)
@@ -222,71 +195,22 @@ static void __init tx4927_irq_cp0_init(void)
222 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n", 195 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_INIT, "beg=%d end=%d\n",
223 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END); 196 TX4927_IRQ_CP0_BEG, TX4927_IRQ_CP0_END);
224 197
225 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++) { 198 for (i = TX4927_IRQ_CP0_BEG; i <= TX4927_IRQ_CP0_END; i++)
226 irq_desc[i].status = IRQ_DISABLED; 199 set_irq_chip(i, &tx4927_irq_cp0_type);
227 irq_desc[i].action = 0;
228 irq_desc[i].depth = 1;
229 irq_desc[i].chip = &tx4927_irq_cp0_type;
230 }
231
232 return;
233}
234
235static unsigned int tx4927_irq_cp0_startup(unsigned int irq)
236{
237 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_STARTUP, "irq=%d \n", irq);
238
239 tx4927_irq_cp0_enable(irq);
240
241 return (0);
242}
243
244static void tx4927_irq_cp0_shutdown(unsigned int irq)
245{
246 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_SHUTDOWN, "irq=%d \n", irq);
247
248 tx4927_irq_cp0_disable(irq);
249
250 return;
251} 200}
252 201
253static void tx4927_irq_cp0_enable(unsigned int irq) 202static void tx4927_irq_cp0_enable(unsigned int irq)
254{ 203{
255 unsigned long flags;
256
257 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq); 204 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_ENABLE, "irq=%d \n", irq);
258 205
259 spin_lock_irqsave(&tx4927_cp0_lock, flags);
260
261 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq)); 206 tx4927_irq_cp0_modify(CCP0_STATUS, 0, tx4927_irq_cp0_mask(irq));
262
263 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
264
265 return;
266} 207}
267 208
268static void tx4927_irq_cp0_disable(unsigned int irq) 209static void tx4927_irq_cp0_disable(unsigned int irq)
269{ 210{
270 unsigned long flags;
271
272 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq); 211 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_DISABLE, "irq=%d \n", irq);
273 212
274 spin_lock_irqsave(&tx4927_cp0_lock, flags);
275
276 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0); 213 tx4927_irq_cp0_modify(CCP0_STATUS, tx4927_irq_cp0_mask(irq), 0);
277
278 spin_unlock_irqrestore(&tx4927_cp0_lock, flags);
279
280 return;
281}
282
283static void tx4927_irq_cp0_mask_and_ack(unsigned int irq)
284{
285 TX4927_IRQ_DPRINTK(TX4927_IRQ_CP0_MASK, "irq=%d \n", irq);
286
287 tx4927_irq_cp0_disable(irq);
288
289 return;
290} 214}
291 215
292static void tx4927_irq_cp0_end(unsigned int irq) 216static void tx4927_irq_cp0_end(unsigned int irq)
@@ -296,8 +220,6 @@ static void tx4927_irq_cp0_end(unsigned int irq)
296 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 220 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
297 tx4927_irq_cp0_enable(irq); 221 tx4927_irq_cp0_enable(irq);
298 } 222 }
299
300 return;
301} 223}
302 224
303/* 225/*
@@ -418,94 +340,38 @@ static void tx4927_irq_pic_modify(unsigned pic_reg, unsigned clr_bits,
418 val &= (~clr_bits); 340 val &= (~clr_bits);
419 val |= (set_bits); 341 val |= (set_bits);
420 TX4927_WR(pic_reg, val); 342 TX4927_WR(pic_reg, val);
421
422 return;
423} 343}
424 344
425static void __init tx4927_irq_pic_init(void) 345static void __init tx4927_irq_pic_init(void)
426{ 346{
427 unsigned long flags;
428 int i; 347 int i;
429 348
430 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n", 349 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_INIT, "beg=%d end=%d\n",
431 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END); 350 TX4927_IRQ_PIC_BEG, TX4927_IRQ_PIC_END);
432 351
433 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++) { 352 for (i = TX4927_IRQ_PIC_BEG; i <= TX4927_IRQ_PIC_END; i++)
434 irq_desc[i].status = IRQ_DISABLED; 353 set_irq_chip(i, &tx4927_irq_pic_type);
435 irq_desc[i].action = 0;
436 irq_desc[i].depth = 2;
437 irq_desc[i].chip = &tx4927_irq_pic_type;
438 }
439 354
440 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action); 355 setup_irq(TX4927_IRQ_NEST_PIC_ON_CP0, &tx4927_irq_pic_action);
441 356
442 spin_lock_irqsave(&tx4927_pic_lock, flags);
443
444 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 357 TX4927_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
445 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */ 358 TX4927_WR(0xff1ff600, TX4927_RD(0xff1ff600) | 0x1); /* irq enable */
446
447 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
448
449 return;
450}
451
452static unsigned int tx4927_irq_pic_startup(unsigned int irq)
453{
454 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_STARTUP, "irq=%d\n", irq);
455
456 tx4927_irq_pic_enable(irq);
457
458 return (0);
459}
460
461static void tx4927_irq_pic_shutdown(unsigned int irq)
462{
463 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_SHUTDOWN, "irq=%d\n", irq);
464
465 tx4927_irq_pic_disable(irq);
466
467 return;
468} 359}
469 360
470static void tx4927_irq_pic_enable(unsigned int irq) 361static void tx4927_irq_pic_enable(unsigned int irq)
471{ 362{
472 unsigned long flags;
473
474 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq); 363 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_ENABLE, "irq=%d\n", irq);
475 364
476 spin_lock_irqsave(&tx4927_pic_lock, flags);
477
478 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0, 365 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 0,
479 tx4927_irq_pic_mask(irq)); 366 tx4927_irq_pic_mask(irq));
480
481 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
482
483 return;
484} 367}
485 368
486static void tx4927_irq_pic_disable(unsigned int irq) 369static void tx4927_irq_pic_disable(unsigned int irq)
487{ 370{
488 unsigned long flags;
489
490 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq); 371 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_DISABLE, "irq=%d\n", irq);
491 372
492 spin_lock_irqsave(&tx4927_pic_lock, flags);
493
494 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq), 373 tx4927_irq_pic_modify(tx4927_irq_pic_addr(irq),
495 tx4927_irq_pic_mask(irq), 0); 374 tx4927_irq_pic_mask(irq), 0);
496
497 spin_unlock_irqrestore(&tx4927_pic_lock, flags);
498
499 return;
500}
501
502static void tx4927_irq_pic_mask_and_ack(unsigned int irq)
503{
504 TX4927_IRQ_DPRINTK(TX4927_IRQ_PIC_MASK, "irq=%d\n", irq);
505
506 tx4927_irq_pic_disable(irq);
507
508 return;
509} 375}
510 376
511static void tx4927_irq_pic_end(unsigned int irq) 377static void tx4927_irq_pic_end(unsigned int irq)
@@ -515,8 +381,6 @@ static void tx4927_irq_pic_end(unsigned int irq)
515 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 381 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
516 tx4927_irq_pic_enable(irq); 382 tx4927_irq_pic_enable(irq);
517 } 383 }
518
519 return;
520} 384}
521 385
522/* 386/*
@@ -533,8 +397,6 @@ void __init tx4927_irq_init(void)
533 tx4927_irq_pic_init(); 397 tx4927_irq_pic_init();
534 398
535 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n"); 399 TX4927_IRQ_DPRINTK(TX4927_IRQ_INIT, "+\n");
536
537 return;
538} 400}
539 401
540static int tx4927_irq_nested(void) 402static int tx4927_irq_nested(void)
diff --git a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
index 0c3c3f668230..1fdace89ae6d 100644
--- a/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
+++ b/arch/mips/tx4927/toshiba_rbtx4927/toshiba_rbtx4927_irq.c
@@ -151,16 +151,11 @@ JP7 is not bus master -- do NOT use -- only 4 pci bus master's allowed -- SouthB
151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 ) 151#define TOSHIBA_RBTX4927_IRQ_EROR ( 1 << 2 )
152 152
153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 ) 153#define TOSHIBA_RBTX4927_IRQ_IOC_INIT ( 1 << 10 )
154#define TOSHIBA_RBTX4927_IRQ_IOC_STARTUP ( 1 << 11 )
155#define TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN ( 1 << 12 )
156#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 ) 154#define TOSHIBA_RBTX4927_IRQ_IOC_ENABLE ( 1 << 13 )
157#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 ) 155#define TOSHIBA_RBTX4927_IRQ_IOC_DISABLE ( 1 << 14 )
158#define TOSHIBA_RBTX4927_IRQ_IOC_MASK ( 1 << 15 )
159#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 ) 156#define TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ ( 1 << 16 )
160 157
161#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 ) 158#define TOSHIBA_RBTX4927_IRQ_ISA_INIT ( 1 << 20 )
162#define TOSHIBA_RBTX4927_IRQ_ISA_STARTUP ( 1 << 21 )
163#define TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN ( 1 << 22 )
164#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 ) 159#define TOSHIBA_RBTX4927_IRQ_ISA_ENABLE ( 1 << 23 )
165#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 ) 160#define TOSHIBA_RBTX4927_IRQ_ISA_DISABLE ( 1 << 24 )
166#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 ) 161#define TOSHIBA_RBTX4927_IRQ_ISA_MASK ( 1 << 25 )
@@ -175,15 +170,10 @@ static const u32 toshiba_rbtx4927_irq_debug_flag =
175 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO | 170 (TOSHIBA_RBTX4927_IRQ_NONE | TOSHIBA_RBTX4927_IRQ_INFO |
176 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR 171 TOSHIBA_RBTX4927_IRQ_WARN | TOSHIBA_RBTX4927_IRQ_EROR
177// | TOSHIBA_RBTX4927_IRQ_IOC_INIT 172// | TOSHIBA_RBTX4927_IRQ_IOC_INIT
178// | TOSHIBA_RBTX4927_IRQ_IOC_STARTUP
179// | TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN
180// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE 173// | TOSHIBA_RBTX4927_IRQ_IOC_ENABLE
181// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE 174// | TOSHIBA_RBTX4927_IRQ_IOC_DISABLE
182// | TOSHIBA_RBTX4927_IRQ_IOC_MASK
183// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ 175// | TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ
184// | TOSHIBA_RBTX4927_IRQ_ISA_INIT 176// | TOSHIBA_RBTX4927_IRQ_ISA_INIT
185// | TOSHIBA_RBTX4927_IRQ_ISA_STARTUP
186// | TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN
187// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE 177// | TOSHIBA_RBTX4927_IRQ_ISA_ENABLE
188// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE 178// | TOSHIBA_RBTX4927_IRQ_ISA_DISABLE
189// | TOSHIBA_RBTX4927_IRQ_ISA_MASK 179// | TOSHIBA_RBTX4927_IRQ_ISA_MASK
@@ -231,35 +221,25 @@ extern void disable_8259A_irq(unsigned int irq);
231extern void mask_and_ack_8259A(unsigned int irq); 221extern void mask_and_ack_8259A(unsigned int irq);
232#endif 222#endif
233 223
234static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq);
235static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq);
236static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq); 224static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq);
237static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq); 225static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq);
238static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq);
239static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq); 226static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq);
240 227
241#ifdef CONFIG_TOSHIBA_FPCIB0 228#ifdef CONFIG_TOSHIBA_FPCIB0
242static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq);
243static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq);
244static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq); 229static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq);
245static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq); 230static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq);
246static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq); 231static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq);
247static void toshiba_rbtx4927_irq_isa_end(unsigned int irq); 232static void toshiba_rbtx4927_irq_isa_end(unsigned int irq);
248#endif 233#endif
249 234
250static DEFINE_SPINLOCK(toshiba_rbtx4927_ioc_lock);
251
252
253#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC" 235#define TOSHIBA_RBTX4927_IOC_NAME "RBTX4927-IOC"
254static struct irq_chip toshiba_rbtx4927_irq_ioc_type = { 236static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
255 .typename = TOSHIBA_RBTX4927_IOC_NAME, 237 .typename = TOSHIBA_RBTX4927_IOC_NAME,
256 .startup = toshiba_rbtx4927_irq_ioc_startup, 238 .ack = toshiba_rbtx4927_irq_ioc_disable,
257 .shutdown = toshiba_rbtx4927_irq_ioc_shutdown, 239 .mask = toshiba_rbtx4927_irq_ioc_disable,
258 .enable = toshiba_rbtx4927_irq_ioc_enable, 240 .mask_ack = toshiba_rbtx4927_irq_ioc_disable,
259 .disable = toshiba_rbtx4927_irq_ioc_disable, 241 .unmask = toshiba_rbtx4927_irq_ioc_enable,
260 .ack = toshiba_rbtx4927_irq_ioc_mask_and_ack,
261 .end = toshiba_rbtx4927_irq_ioc_end, 242 .end = toshiba_rbtx4927_irq_ioc_end,
262 .set_affinity = NULL
263}; 243};
264#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000 244#define TOSHIBA_RBTX4927_IOC_INTR_ENAB 0xbc002000
265#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006 245#define TOSHIBA_RBTX4927_IOC_INTR_STAT 0xbc002006
@@ -269,13 +249,11 @@ static struct irq_chip toshiba_rbtx4927_irq_ioc_type = {
269#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA" 249#define TOSHIBA_RBTX4927_ISA_NAME "RBTX4927-ISA"
270static struct irq_chip toshiba_rbtx4927_irq_isa_type = { 250static struct irq_chip toshiba_rbtx4927_irq_isa_type = {
271 .typename = TOSHIBA_RBTX4927_ISA_NAME, 251 .typename = TOSHIBA_RBTX4927_ISA_NAME,
272 .startup = toshiba_rbtx4927_irq_isa_startup,
273 .shutdown = toshiba_rbtx4927_irq_isa_shutdown,
274 .enable = toshiba_rbtx4927_irq_isa_enable,
275 .disable = toshiba_rbtx4927_irq_isa_disable,
276 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack, 252 .ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
253 .mask = toshiba_rbtx4927_irq_isa_disable,
254 .mask_ack = toshiba_rbtx4927_irq_isa_mask_and_ack,
255 .unmask = toshiba_rbtx4927_irq_isa_enable,
277 .end = toshiba_rbtx4927_irq_isa_end, 256 .end = toshiba_rbtx4927_irq_isa_end,
278 .set_affinity = NULL
279}; 257};
280#endif 258#endif
281 259
@@ -363,58 +341,15 @@ static void __init toshiba_rbtx4927_irq_ioc_init(void)
363 TOSHIBA_RBTX4927_IRQ_IOC_END); 341 TOSHIBA_RBTX4927_IRQ_IOC_END);
364 342
365 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG; 343 for (i = TOSHIBA_RBTX4927_IRQ_IOC_BEG;
366 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++) { 344 i <= TOSHIBA_RBTX4927_IRQ_IOC_END; i++)
367 irq_desc[i].status = IRQ_DISABLED; 345 set_irq_chip(i, &toshiba_rbtx4927_irq_ioc_type);
368 irq_desc[i].action = 0;
369 irq_desc[i].depth = 3;
370 irq_desc[i].chip = &toshiba_rbtx4927_irq_ioc_type;
371 }
372 346
373 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC, 347 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_IOC_ON_PIC,
374 &toshiba_rbtx4927_irq_ioc_action); 348 &toshiba_rbtx4927_irq_ioc_action);
375
376 return;
377} 349}
378 350
379static unsigned int toshiba_rbtx4927_irq_ioc_startup(unsigned int irq)
380{
381 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_STARTUP,
382 "irq=%d\n", irq);
383
384 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
385 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
386 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
387 "bad irq=%d\n", irq);
388 panic("\n");
389 }
390
391 toshiba_rbtx4927_irq_ioc_enable(irq);
392
393 return (0);
394}
395
396
397static void toshiba_rbtx4927_irq_ioc_shutdown(unsigned int irq)
398{
399 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_SHUTDOWN,
400 "irq=%d\n", irq);
401
402 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
403 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
404 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
405 "bad irq=%d\n", irq);
406 panic("\n");
407 }
408
409 toshiba_rbtx4927_irq_ioc_disable(irq);
410
411 return;
412}
413
414
415static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq) 351static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
416{ 352{
417 unsigned long flags;
418 volatile unsigned char v; 353 volatile unsigned char v;
419 354
420 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE, 355 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENABLE,
@@ -427,21 +362,14 @@ static void toshiba_rbtx4927_irq_ioc_enable(unsigned int irq)
427 panic("\n"); 362 panic("\n");
428 } 363 }
429 364
430 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
431
432 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 365 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
433 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 366 v |= (1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
434 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 367 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
435
436 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
437
438 return;
439} 368}
440 369
441 370
442static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq) 371static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
443{ 372{
444 unsigned long flags;
445 volatile unsigned char v; 373 volatile unsigned char v;
446 374
447 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE, 375 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_DISABLE,
@@ -454,36 +382,11 @@ static void toshiba_rbtx4927_irq_ioc_disable(unsigned int irq)
454 panic("\n"); 382 panic("\n");
455 } 383 }
456 384
457 spin_lock_irqsave(&toshiba_rbtx4927_ioc_lock, flags);
458
459 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB); 385 v = TX4927_RD08(TOSHIBA_RBTX4927_IOC_INTR_ENAB);
460 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG)); 386 v &= ~(1 << (irq - TOSHIBA_RBTX4927_IRQ_IOC_BEG));
461 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v); 387 TOSHIBA_RBTX4927_WR08(TOSHIBA_RBTX4927_IOC_INTR_ENAB, v);
462
463 spin_unlock_irqrestore(&toshiba_rbtx4927_ioc_lock, flags);
464
465 return;
466} 388}
467 389
468
469static void toshiba_rbtx4927_irq_ioc_mask_and_ack(unsigned int irq)
470{
471 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_MASK,
472 "irq=%d\n", irq);
473
474 if (irq < TOSHIBA_RBTX4927_IRQ_IOC_BEG
475 || irq > TOSHIBA_RBTX4927_IRQ_IOC_END) {
476 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
477 "bad irq=%d\n", irq);
478 panic("\n");
479 }
480
481 toshiba_rbtx4927_irq_ioc_disable(irq);
482
483 return;
484}
485
486
487static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq) 390static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
488{ 391{
489 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ, 392 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_IOC_ENDIRQ,
@@ -499,8 +402,6 @@ static void toshiba_rbtx4927_irq_ioc_end(unsigned int irq)
499 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 402 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
500 toshiba_rbtx4927_irq_ioc_enable(irq); 403 toshiba_rbtx4927_irq_ioc_enable(irq);
501 } 404 }
502
503 return;
504} 405}
505 406
506 407
@@ -520,13 +421,8 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
520 TOSHIBA_RBTX4927_IRQ_ISA_END); 421 TOSHIBA_RBTX4927_IRQ_ISA_END);
521 422
522 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG; 423 for (i = TOSHIBA_RBTX4927_IRQ_ISA_BEG;
523 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++) { 424 i <= TOSHIBA_RBTX4927_IRQ_ISA_END; i++)
524 irq_desc[i].status = IRQ_DISABLED; 425 set_irq_chip(i, &toshiba_rbtx4927_irq_isa_type);
525 irq_desc[i].action = 0;
526 irq_desc[i].depth =
527 ((i < TOSHIBA_RBTX4927_IRQ_ISA_MID) ? (4) : (5));
528 irq_desc[i].chip = &toshiba_rbtx4927_irq_isa_type;
529 }
530 426
531 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC, 427 setup_irq(TOSHIBA_RBTX4927_IRQ_NEST_ISA_ON_IOC,
532 &toshiba_rbtx4927_irq_isa_master); 428 &toshiba_rbtx4927_irq_isa_master);
@@ -536,48 +432,6 @@ static void __init toshiba_rbtx4927_irq_isa_init(void)
536 /* make sure we are looking at IRR (not ISR) */ 432 /* make sure we are looking at IRR (not ISR) */
537 outb(0x0A, 0x20); 433 outb(0x0A, 0x20);
538 outb(0x0A, 0xA0); 434 outb(0x0A, 0xA0);
539
540 return;
541}
542#endif
543
544
545#ifdef CONFIG_TOSHIBA_FPCIB0
546static unsigned int toshiba_rbtx4927_irq_isa_startup(unsigned int irq)
547{
548 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_STARTUP,
549 "irq=%d\n", irq);
550
551 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
552 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
553 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
554 "bad irq=%d\n", irq);
555 panic("\n");
556 }
557
558 toshiba_rbtx4927_irq_isa_enable(irq);
559
560 return (0);
561}
562#endif
563
564
565#ifdef CONFIG_TOSHIBA_FPCIB0
566static void toshiba_rbtx4927_irq_isa_shutdown(unsigned int irq)
567{
568 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_ISA_SHUTDOWN,
569 "irq=%d\n", irq);
570
571 if (irq < TOSHIBA_RBTX4927_IRQ_ISA_BEG
572 || irq > TOSHIBA_RBTX4927_IRQ_ISA_END) {
573 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_EROR,
574 "bad irq=%d\n", irq);
575 panic("\n");
576 }
577
578 toshiba_rbtx4927_irq_isa_disable(irq);
579
580 return;
581} 435}
582#endif 436#endif
583 437
@@ -596,8 +450,6 @@ static void toshiba_rbtx4927_irq_isa_enable(unsigned int irq)
596 } 450 }
597 451
598 enable_8259A_irq(irq); 452 enable_8259A_irq(irq);
599
600 return;
601} 453}
602#endif 454#endif
603 455
@@ -616,8 +468,6 @@ static void toshiba_rbtx4927_irq_isa_disable(unsigned int irq)
616 } 468 }
617 469
618 disable_8259A_irq(irq); 470 disable_8259A_irq(irq);
619
620 return;
621} 471}
622#endif 472#endif
623 473
@@ -636,8 +486,6 @@ static void toshiba_rbtx4927_irq_isa_mask_and_ack(unsigned int irq)
636 } 486 }
637 487
638 mask_and_ack_8259A(irq); 488 mask_and_ack_8259A(irq);
639
640 return;
641} 489}
642#endif 490#endif
643 491
@@ -658,8 +506,6 @@ static void toshiba_rbtx4927_irq_isa_end(unsigned int irq)
658 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) { 506 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) {
659 toshiba_rbtx4927_irq_isa_enable(irq); 507 toshiba_rbtx4927_irq_isa_enable(irq);
660 } 508 }
661
662 return;
663} 509}
664#endif 510#endif
665 511
@@ -668,8 +514,6 @@ void __init arch_init_irq(void)
668{ 514{
669 extern void tx4927_irq_init(void); 515 extern void tx4927_irq_init(void);
670 516
671 local_irq_disable();
672
673 tx4927_irq_init(); 517 tx4927_irq_init();
674 toshiba_rbtx4927_irq_ioc_init(); 518 toshiba_rbtx4927_irq_ioc_init();
675#ifdef CONFIG_TOSHIBA_FPCIB0 519#ifdef CONFIG_TOSHIBA_FPCIB0
@@ -681,8 +525,6 @@ void __init arch_init_irq(void)
681#endif 525#endif
682 526
683 wbflush(); 527 wbflush();
684
685 return;
686} 528}
687 529
688void toshiba_rbtx4927_irq_dump(char *key) 530void toshiba_rbtx4927_irq_dump(char *key)
@@ -715,7 +557,6 @@ void toshiba_rbtx4927_irq_dump(char *key)
715 } 557 }
716 } 558 }
717#endif 559#endif
718 return;
719} 560}
720 561
721void toshiba_rbtx4927_irq_dump_pics(char *s) 562void toshiba_rbtx4927_irq_dump_pics(char *s)
@@ -780,6 +621,4 @@ void toshiba_rbtx4927_irq_dump_pics(char *s)
780 level5_s); 621 level5_s);
781 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n", 622 TOSHIBA_RBTX4927_IRQ_DPRINTK(TOSHIBA_RBTX4927_IRQ_INFO, "[%s]\n",
782 s); 623 s);
783
784 return;
785} 624}
diff --git a/arch/mips/tx4938/common/irq.c b/arch/mips/tx4938/common/irq.c
index 77fe2454f5b9..19c9ee9e3d0c 100644
--- a/arch/mips/tx4938/common/irq.c
+++ b/arch/mips/tx4938/common/irq.c
@@ -37,48 +37,36 @@
37/* Forwad definitions for all pic's */ 37/* Forwad definitions for all pic's */
38/**********************************************************************************/ 38/**********************************************************************************/
39 39
40static unsigned int tx4938_irq_cp0_startup(unsigned int irq);
41static void tx4938_irq_cp0_shutdown(unsigned int irq);
42static void tx4938_irq_cp0_enable(unsigned int irq); 40static void tx4938_irq_cp0_enable(unsigned int irq);
43static void tx4938_irq_cp0_disable(unsigned int irq); 41static void tx4938_irq_cp0_disable(unsigned int irq);
44static void tx4938_irq_cp0_mask_and_ack(unsigned int irq);
45static void tx4938_irq_cp0_end(unsigned int irq); 42static void tx4938_irq_cp0_end(unsigned int irq);
46 43
47static unsigned int tx4938_irq_pic_startup(unsigned int irq);
48static void tx4938_irq_pic_shutdown(unsigned int irq);
49static void tx4938_irq_pic_enable(unsigned int irq); 44static void tx4938_irq_pic_enable(unsigned int irq);
50static void tx4938_irq_pic_disable(unsigned int irq); 45static void tx4938_irq_pic_disable(unsigned int irq);
51static void tx4938_irq_pic_mask_and_ack(unsigned int irq);
52static void tx4938_irq_pic_end(unsigned int irq); 46static void tx4938_irq_pic_end(unsigned int irq);
53 47
54/**********************************************************************************/ 48/**********************************************************************************/
55/* Kernel structs for all pic's */ 49/* Kernel structs for all pic's */
56/**********************************************************************************/ 50/**********************************************************************************/
57DEFINE_SPINLOCK(tx4938_cp0_lock);
58DEFINE_SPINLOCK(tx4938_pic_lock);
59 51
60#define TX4938_CP0_NAME "TX4938-CP0" 52#define TX4938_CP0_NAME "TX4938-CP0"
61static struct irq_chip tx4938_irq_cp0_type = { 53static struct irq_chip tx4938_irq_cp0_type = {
62 .typename = TX4938_CP0_NAME, 54 .typename = TX4938_CP0_NAME,
63 .startup = tx4938_irq_cp0_startup, 55 .ack = tx4938_irq_cp0_disable,
64 .shutdown = tx4938_irq_cp0_shutdown, 56 .mask = tx4938_irq_cp0_disable,
65 .enable = tx4938_irq_cp0_enable, 57 .mask_ack = tx4938_irq_cp0_disable,
66 .disable = tx4938_irq_cp0_disable, 58 .unmask = tx4938_irq_cp0_enable,
67 .ack = tx4938_irq_cp0_mask_and_ack,
68 .end = tx4938_irq_cp0_end, 59 .end = tx4938_irq_cp0_end,
69 .set_affinity = NULL
70}; 60};
71 61
72#define TX4938_PIC_NAME "TX4938-PIC" 62#define TX4938_PIC_NAME "TX4938-PIC"
73static struct irq_chip tx4938_irq_pic_type = { 63static struct irq_chip tx4938_irq_pic_type = {
74 .typename = TX4938_PIC_NAME, 64 .typename = TX4938_PIC_NAME,
75 .startup = tx4938_irq_pic_startup, 65 .ack = tx4938_irq_pic_disable,
76 .shutdown = tx4938_irq_pic_shutdown, 66 .mask = tx4938_irq_pic_disable,
77 .enable = tx4938_irq_pic_enable, 67 .mask_ack = tx4938_irq_pic_disable,
78 .disable = tx4938_irq_pic_disable, 68 .unmask = tx4938_irq_pic_enable,
79 .ack = tx4938_irq_pic_mask_and_ack,
80 .end = tx4938_irq_pic_end, 69 .end = tx4938_irq_pic_end,
81 .set_affinity = NULL
82}; 70};
83 71
84static struct irqaction tx4938_irq_pic_action = { 72static struct irqaction tx4938_irq_pic_action = {
@@ -99,56 +87,20 @@ tx4938_irq_cp0_init(void)
99{ 87{
100 int i; 88 int i;
101 89
102 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++) { 90 for (i = TX4938_IRQ_CP0_BEG; i <= TX4938_IRQ_CP0_END; i++)
103 irq_desc[i].status = IRQ_DISABLED; 91 set_irq_chip(i, &tx4938_irq_cp0_type);
104 irq_desc[i].action = 0;
105 irq_desc[i].depth = 1;
106 irq_desc[i].chip = &tx4938_irq_cp0_type;
107 }
108}
109
110static unsigned int
111tx4938_irq_cp0_startup(unsigned int irq)
112{
113 tx4938_irq_cp0_enable(irq);
114
115 return 0;
116}
117
118static void
119tx4938_irq_cp0_shutdown(unsigned int irq)
120{
121 tx4938_irq_cp0_disable(irq);
122} 92}
123 93
124static void 94static void
125tx4938_irq_cp0_enable(unsigned int irq) 95tx4938_irq_cp0_enable(unsigned int irq)
126{ 96{
127 unsigned long flags;
128
129 spin_lock_irqsave(&tx4938_cp0_lock, flags);
130
131 set_c0_status(tx4938_irq_cp0_mask(irq)); 97 set_c0_status(tx4938_irq_cp0_mask(irq));
132
133 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
134} 98}
135 99
136static void 100static void
137tx4938_irq_cp0_disable(unsigned int irq) 101tx4938_irq_cp0_disable(unsigned int irq)
138{ 102{
139 unsigned long flags;
140
141 spin_lock_irqsave(&tx4938_cp0_lock, flags);
142
143 clear_c0_status(tx4938_irq_cp0_mask(irq)); 103 clear_c0_status(tx4938_irq_cp0_mask(irq));
144
145 spin_unlock_irqrestore(&tx4938_cp0_lock, flags);
146}
147
148static void
149tx4938_irq_cp0_mask_and_ack(unsigned int irq)
150{
151 tx4938_irq_cp0_disable(irq);
152} 104}
153 105
154static void 106static void
@@ -290,70 +242,29 @@ tx4938_irq_pic_modify(unsigned pic_reg, unsigned clr_bits, unsigned set_bits)
290static void __init 242static void __init
291tx4938_irq_pic_init(void) 243tx4938_irq_pic_init(void)
292{ 244{
293 unsigned long flags;
294 int i; 245 int i;
295 246
296 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++) { 247 for (i = TX4938_IRQ_PIC_BEG; i <= TX4938_IRQ_PIC_END; i++)
297 irq_desc[i].status = IRQ_DISABLED; 248 set_irq_chip(i, &tx4938_irq_pic_type);
298 irq_desc[i].action = 0;
299 irq_desc[i].depth = 2;
300 irq_desc[i].chip = &tx4938_irq_pic_type;
301 }
302 249
303 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action); 250 setup_irq(TX4938_IRQ_NEST_PIC_ON_CP0, &tx4938_irq_pic_action);
304 251
305 spin_lock_irqsave(&tx4938_pic_lock, flags);
306
307 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */ 252 TX4938_WR(0xff1ff640, 0x6); /* irq level mask -- only accept hightest */
308 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */ 253 TX4938_WR(0xff1ff600, TX4938_RD(0xff1ff600) | 0x1); /* irq enable */
309
310 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
311}
312
313static unsigned int
314tx4938_irq_pic_startup(unsigned int irq)
315{
316 tx4938_irq_pic_enable(irq);
317
318 return 0;
319}
320
321static void
322tx4938_irq_pic_shutdown(unsigned int irq)
323{
324 tx4938_irq_pic_disable(irq);
325} 254}
326 255
327static void 256static void
328tx4938_irq_pic_enable(unsigned int irq) 257tx4938_irq_pic_enable(unsigned int irq)
329{ 258{
330 unsigned long flags;
331
332 spin_lock_irqsave(&tx4938_pic_lock, flags);
333
334 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0, 259 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 0,
335 tx4938_irq_pic_mask(irq)); 260 tx4938_irq_pic_mask(irq));
336
337 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
338} 261}
339 262
340static void 263static void
341tx4938_irq_pic_disable(unsigned int irq) 264tx4938_irq_pic_disable(unsigned int irq)
342{ 265{
343 unsigned long flags;
344
345 spin_lock_irqsave(&tx4938_pic_lock, flags);
346
347 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq), 266 tx4938_irq_pic_modify(tx4938_irq_pic_addr(irq),
348 tx4938_irq_pic_mask(irq), 0); 267 tx4938_irq_pic_mask(irq), 0);
349
350 spin_unlock_irqrestore(&tx4938_pic_lock, flags);
351}
352
353static void
354tx4938_irq_pic_mask_and_ack(unsigned int irq)
355{
356 tx4938_irq_pic_disable(irq);
357} 268}
358 269
359static void 270static void
diff --git a/arch/mips/tx4938/toshiba_rbtx4938/irq.c b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
index 102e473c10a2..2735ffe9ec28 100644
--- a/arch/mips/tx4938/toshiba_rbtx4938/irq.c
+++ b/arch/mips/tx4938/toshiba_rbtx4938/irq.c
@@ -87,25 +87,18 @@ IRQ Device
87#include <linux/bootmem.h> 87#include <linux/bootmem.h>
88#include <asm/tx4938/rbtx4938.h> 88#include <asm/tx4938/rbtx4938.h>
89 89
90static unsigned int toshiba_rbtx4938_irq_ioc_startup(unsigned int irq);
91static void toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq);
92static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq); 90static void toshiba_rbtx4938_irq_ioc_enable(unsigned int irq);
93static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq); 91static void toshiba_rbtx4938_irq_ioc_disable(unsigned int irq);
94static void toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq);
95static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq); 92static void toshiba_rbtx4938_irq_ioc_end(unsigned int irq);
96 93
97DEFINE_SPINLOCK(toshiba_rbtx4938_ioc_lock);
98
99#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC" 94#define TOSHIBA_RBTX4938_IOC_NAME "RBTX4938-IOC"
100static struct irq_chip toshiba_rbtx4938_irq_ioc_type = { 95static struct irq_chip toshiba_rbtx4938_irq_ioc_type = {
101 .typename = TOSHIBA_RBTX4938_IOC_NAME, 96 .typename = TOSHIBA_RBTX4938_IOC_NAME,
102 .startup = toshiba_rbtx4938_irq_ioc_startup, 97 .ack = toshiba_rbtx4938_irq_ioc_disable,
103 .shutdown = toshiba_rbtx4938_irq_ioc_shutdown, 98 .mask = toshiba_rbtx4938_irq_ioc_disable,
104 .enable = toshiba_rbtx4938_irq_ioc_enable, 99 .mask_ack = toshiba_rbtx4938_irq_ioc_disable,
105 .disable = toshiba_rbtx4938_irq_ioc_disable, 100 .unmask = toshiba_rbtx4938_irq_ioc_enable,
106 .ack = toshiba_rbtx4938_irq_ioc_mask_and_ack,
107 .end = toshiba_rbtx4938_irq_ioc_end, 101 .end = toshiba_rbtx4938_irq_ioc_end,
108 .set_affinity = NULL
109}; 102};
110 103
111#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000 104#define TOSHIBA_RBTX4938_IOC_INTR_ENAB 0xb7f02000
@@ -142,69 +135,35 @@ toshiba_rbtx4938_irq_ioc_init(void)
142 int i; 135 int i;
143 136
144 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG; 137 for (i = TOSHIBA_RBTX4938_IRQ_IOC_BEG;
145 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++) { 138 i <= TOSHIBA_RBTX4938_IRQ_IOC_END; i++)
146 irq_desc[i].status = IRQ_DISABLED; 139 set_irq_chip(i, &toshiba_rbtx4938_irq_ioc_type);
147 irq_desc[i].action = 0;
148 irq_desc[i].depth = 3;
149 irq_desc[i].chip = &toshiba_rbtx4938_irq_ioc_type;
150 }
151 140
152 setup_irq(RBTX4938_IRQ_IOCINT, 141 setup_irq(RBTX4938_IRQ_IOCINT,
153 &toshiba_rbtx4938_irq_ioc_action); 142 &toshiba_rbtx4938_irq_ioc_action);
154} 143}
155 144
156static unsigned int
157toshiba_rbtx4938_irq_ioc_startup(unsigned int irq)
158{
159 toshiba_rbtx4938_irq_ioc_enable(irq);
160
161 return 0;
162}
163
164static void
165toshiba_rbtx4938_irq_ioc_shutdown(unsigned int irq)
166{
167 toshiba_rbtx4938_irq_ioc_disable(irq);
168}
169
170static void 145static void
171toshiba_rbtx4938_irq_ioc_enable(unsigned int irq) 146toshiba_rbtx4938_irq_ioc_enable(unsigned int irq)
172{ 147{
173 unsigned long flags;
174 volatile unsigned char v; 148 volatile unsigned char v;
175 149
176 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
177
178 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 150 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
179 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 151 v |= (1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
180 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 152 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
181 mmiowb(); 153 mmiowb();
182 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 154 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
183
184 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
185} 155}
186 156
187static void 157static void
188toshiba_rbtx4938_irq_ioc_disable(unsigned int irq) 158toshiba_rbtx4938_irq_ioc_disable(unsigned int irq)
189{ 159{
190 unsigned long flags;
191 volatile unsigned char v; 160 volatile unsigned char v;
192 161
193 spin_lock_irqsave(&toshiba_rbtx4938_ioc_lock, flags);
194
195 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 162 v = TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
196 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG)); 163 v &= ~(1 << (irq - TOSHIBA_RBTX4938_IRQ_IOC_BEG));
197 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v); 164 TX4938_WR08(TOSHIBA_RBTX4938_IOC_INTR_ENAB, v);
198 mmiowb(); 165 mmiowb();
199 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB); 166 TX4938_RD08(TOSHIBA_RBTX4938_IOC_INTR_ENAB);
200
201 spin_unlock_irqrestore(&toshiba_rbtx4938_ioc_lock, flags);
202}
203
204static void
205toshiba_rbtx4938_irq_ioc_mask_and_ack(unsigned int irq)
206{
207 toshiba_rbtx4938_irq_ioc_disable(irq);
208} 167}
209 168
210static void 169static void
diff --git a/arch/mips/vr41xx/common/icu.c b/arch/mips/vr41xx/common/icu.c
index c215c0d39fae..33d70a6547ad 100644
--- a/arch/mips/vr41xx/common/icu.c
+++ b/arch/mips/vr41xx/common/icu.c
@@ -417,14 +417,7 @@ void vr41xx_disable_bcuint(void)
417 417
418EXPORT_SYMBOL(vr41xx_disable_bcuint); 418EXPORT_SYMBOL(vr41xx_disable_bcuint);
419 419
420static unsigned int startup_sysint1_irq(unsigned int irq) 420static void disable_sysint1_irq(unsigned int irq)
421{
422 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
423
424 return 0; /* never anything pending */
425}
426
427static void shutdown_sysint1_irq(unsigned int irq)
428{ 421{
429 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 422 icu1_clear(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
430} 423}
@@ -434,9 +427,6 @@ static void enable_sysint1_irq(unsigned int irq)
434 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq)); 427 icu1_set(MSYSINT1REG, 1 << SYSINT1_IRQ_TO_PIN(irq));
435} 428}
436 429
437#define disable_sysint1_irq shutdown_sysint1_irq
438#define ack_sysint1_irq shutdown_sysint1_irq
439
440static void end_sysint1_irq(unsigned int irq) 430static void end_sysint1_irq(unsigned int irq)
441{ 431{
442 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 432 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -445,22 +435,14 @@ static void end_sysint1_irq(unsigned int irq)
445 435
446static struct irq_chip sysint1_irq_type = { 436static struct irq_chip sysint1_irq_type = {
447 .typename = "SYSINT1", 437 .typename = "SYSINT1",
448 .startup = startup_sysint1_irq, 438 .ack = disable_sysint1_irq,
449 .shutdown = shutdown_sysint1_irq, 439 .mask = disable_sysint1_irq,
450 .enable = enable_sysint1_irq, 440 .mask_ack = disable_sysint1_irq,
451 .disable = disable_sysint1_irq, 441 .unmask = enable_sysint1_irq,
452 .ack = ack_sysint1_irq,
453 .end = end_sysint1_irq, 442 .end = end_sysint1_irq,
454}; 443};
455 444
456static unsigned int startup_sysint2_irq(unsigned int irq) 445static void disable_sysint2_irq(unsigned int irq)
457{
458 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
459
460 return 0; /* never anything pending */
461}
462
463static void shutdown_sysint2_irq(unsigned int irq)
464{ 446{
465 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 447 icu2_clear(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
466} 448}
@@ -470,9 +452,6 @@ static void enable_sysint2_irq(unsigned int irq)
470 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq)); 452 icu2_set(MSYSINT2REG, 1 << SYSINT2_IRQ_TO_PIN(irq));
471} 453}
472 454
473#define disable_sysint2_irq shutdown_sysint2_irq
474#define ack_sysint2_irq shutdown_sysint2_irq
475
476static void end_sysint2_irq(unsigned int irq) 455static void end_sysint2_irq(unsigned int irq)
477{ 456{
478 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS))) 457 if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
@@ -481,11 +460,10 @@ static void end_sysint2_irq(unsigned int irq)
481 460
482static struct irq_chip sysint2_irq_type = { 461static struct irq_chip sysint2_irq_type = {
483 .typename = "SYSINT2", 462 .typename = "SYSINT2",
484 .startup = startup_sysint2_irq, 463 .ack = disable_sysint2_irq,
485 .shutdown = shutdown_sysint2_irq, 464 .mask = disable_sysint2_irq,
486 .enable = enable_sysint2_irq, 465 .mask_ack = disable_sysint2_irq,
487 .disable = disable_sysint2_irq, 466 .unmask = enable_sysint2_irq,
488 .ack = ack_sysint2_irq,
489 .end = end_sysint2_irq, 467 .end = end_sysint2_irq,
490}; 468};
491 469
@@ -723,10 +701,10 @@ static int __init vr41xx_icu_init(void)
723 icu2_write(MGIUINTHREG, 0xffff); 701 icu2_write(MGIUINTHREG, 0xffff);
724 702
725 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++) 703 for (i = SYSINT1_IRQ_BASE; i <= SYSINT1_IRQ_LAST; i++)
726 irq_desc[i].chip = &sysint1_irq_type; 704 set_irq_chip(i, &sysint1_irq_type);
727 705
728 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++) 706 for (i = SYSINT2_IRQ_BASE; i <= SYSINT2_IRQ_LAST; i++)
729 irq_desc[i].chip = &sysint2_irq_type; 707 set_irq_chip(i, &sysint2_irq_type);
730 708
731 cascade_irq(INT0_IRQ, icu_get_irq); 709 cascade_irq(INT0_IRQ, icu_get_irq);
732 cascade_irq(INT1_IRQ, icu_get_irq); 710 cascade_irq(INT1_IRQ, icu_get_irq);
diff --git a/arch/mips/vr41xx/nec-cmbvr4133/irq.c b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
index 2483487344c2..a039bb7251ff 100644
--- a/arch/mips/vr41xx/nec-cmbvr4133/irq.c
+++ b/arch/mips/vr41xx/nec-cmbvr4133/irq.c
@@ -30,17 +30,6 @@ extern void init_8259A(int hoge);
30 30
31extern int vr4133_rockhopper; 31extern int vr4133_rockhopper;
32 32
33static unsigned int startup_i8259_irq(unsigned int irq)
34{
35 enable_8259A_irq(irq - I8259_IRQ_BASE);
36 return 0;
37}
38
39static void shutdown_i8259_irq(unsigned int irq)
40{
41 disable_8259A_irq(irq - I8259_IRQ_BASE);
42}
43
44static void enable_i8259_irq(unsigned int irq) 33static void enable_i8259_irq(unsigned int irq)
45{ 34{
46 enable_8259A_irq(irq - I8259_IRQ_BASE); 35 enable_8259A_irq(irq - I8259_IRQ_BASE);
@@ -64,11 +53,10 @@ static void end_i8259_irq(unsigned int irq)
64 53
65static struct irq_chip i8259_irq_type = { 54static struct irq_chip i8259_irq_type = {
66 .typename = "XT-PIC", 55 .typename = "XT-PIC",
67 .startup = startup_i8259_irq,
68 .shutdown = shutdown_i8259_irq,
69 .enable = enable_i8259_irq,
70 .disable = disable_i8259_irq,
71 .ack = ack_i8259_irq, 56 .ack = ack_i8259_irq,
57 .mask = disable_i8259_irq,
58 .mask_ack = ack_i8259_irq,
59 .unmask = enable_i8259_irq,
72 .end = end_i8259_irq, 60 .end = end_i8259_irq,
73}; 61};
74 62
@@ -104,7 +92,7 @@ void __init rockhopper_init_irq(void)
104 } 92 }
105 93
106 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++) 94 for (i = I8259_IRQ_BASE; i <= I8259_IRQ_LAST; i++)
107 irq_desc[i].chip = &i8259_irq_type; 95 set_irq_chip(i, &i8259_irq_type);
108 96
109 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade); 97 setup_irq(I8259_SLAVE_IRQ, &i8259_slave_cascade);
110 98
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
index 8319ad77b250..93430b5f4724 100644
--- a/include/asm-mips/dec/kn02.h
+++ b/include/asm-mips/dec/kn02.h
@@ -82,11 +82,9 @@
82 82
83#ifndef __ASSEMBLY__ 83#ifndef __ASSEMBLY__
84 84
85#include <linux/spinlock.h>
86#include <linux/types.h> 85#include <linux/types.h>
87 86
88extern u32 cached_kn02_csr; 87extern u32 cached_kn02_csr;
89extern spinlock_t kn02_lock;
90extern void init_kn02_irqs(int base); 88extern void init_kn02_irqs(int base);
91#endif 89#endif
92 90
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 19:41:54 -0500