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authorMyungJoo Ham <myungjoo.ham@samsung.com>2010-06-26 04:21:50 -0400
committerKukjin Kim <kgene.kim@samsung.com>2010-07-05 03:01:04 -0400
commit154d62e4cdec9eb9271cf57f9d1f57c79c4f4e18 (patch)
tree00047b72abd4952a7e61504328dc2b768ca73c18
parent79fc72d6d3ab4ee08068fe39c199aab2e677daaa (diff)
ARM: S5PV210: Correct clock register properties
1. Corrected shift values of I2S and UART clocks (CLK_GATE_IP3), which were defined incorrectly. 2. Corrected shift values of sclk_audio, uclk1, sclk_fimd, sclk_mmc, sclk_spi, sclk_pwm, which had duplicated .enable/.ctrlbit with their twins defined in struct clk init_clocks_disable[] and struct clk init_clocks[]. We've changed their .enable/.ctrlbit to use CLK_SRC_MASK register to avoid the duplicated clock problem described below. NOTE: Duplicated Clock Problem Please note that each clock definition should access different control register; otherwise, the system may suffer lockups. For example, if we have two clock definitions "a" and "b" which access the same register (and the shift value). Then, when we do: module A clk = clk_get("a"); clk->clk_enable(clk); module B (context switch) clk = clk_get("b"); clk->clk_enable(clk); do something with clk. clk->clk_disable(clk); module A (context switch) do something with clk * At this point, the system may hang. Therefore, there should be no clock definitions with the same contol register/shift. If we need to create "aliases", then, creating child clocks sharing the clock should be fine. 3. Corrected other sclk_* shift values and access registers. Signed-off-by: MyungJoo Ham <myungjoo.ham@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> [kgene.kim@samsung.com: minor title and message fix] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-s5pv210/clock.c115
1 files changed, 62 insertions, 53 deletions
diff --git a/arch/arm/mach-s5pv210/clock.c b/arch/arm/mach-s5pv210/clock.c
index 154bca4abc09..af91fefef2c6 100644
--- a/arch/arm/mach-s5pv210/clock.c
+++ b/arch/arm/mach-s5pv210/clock.c
@@ -183,6 +183,11 @@ static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable); 183 return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
184} 184}
185 185
186static int s5pv210_clk_mask1_ctrl(struct clk *clk, int enable)
187{
188 return s5p_gatectrl(S5P_CLK_SRC_MASK1, clk, enable);
189}
190
186static struct clk clk_sclk_hdmi27m = { 191static struct clk clk_sclk_hdmi27m = {
187 .name = "sclk_hdmi27m", 192 .name = "sclk_hdmi27m",
188 .id = -1, 193 .id = -1,
@@ -406,14 +411,14 @@ static struct clk init_clocks_disable[] = {
406 .id = 0, 411 .id = 0,
407 .parent = &clk_p, 412 .parent = &clk_p,
408 .enable = s5pv210_clk_ip3_ctrl, 413 .enable = s5pv210_clk_ip3_ctrl,
409 .ctrlbit = (1<<4), 414 .ctrlbit = (1 << 5),
410 }, { 415 }, {
411 .name = "i2s_v32", 416 .name = "i2s_v32",
412 .id = 1, 417 .id = 1,
413 .parent = &clk_p, 418 .parent = &clk_p,
414 .enable = s5pv210_clk_ip3_ctrl, 419 .enable = s5pv210_clk_ip3_ctrl,
415 .ctrlbit = (1<<4), 420 .ctrlbit = (1 << 6),
416 } 421 },
417}; 422};
418 423
419static struct clk init_clocks[] = { 424static struct clk init_clocks[] = {
@@ -429,25 +434,25 @@ static struct clk init_clocks[] = {
429 .id = 0, 434 .id = 0,
430 .parent = &clk_pclk_psys.clk, 435 .parent = &clk_pclk_psys.clk,
431 .enable = s5pv210_clk_ip3_ctrl, 436 .enable = s5pv210_clk_ip3_ctrl,
432 .ctrlbit = (1<<7), 437 .ctrlbit = (1 << 17),
433 }, { 438 }, {
434 .name = "uart", 439 .name = "uart",
435 .id = 1, 440 .id = 1,
436 .parent = &clk_pclk_psys.clk, 441 .parent = &clk_pclk_psys.clk,
437 .enable = s5pv210_clk_ip3_ctrl, 442 .enable = s5pv210_clk_ip3_ctrl,
438 .ctrlbit = (1<<8), 443 .ctrlbit = (1 << 18),
439 }, { 444 }, {
440 .name = "uart", 445 .name = "uart",
441 .id = 2, 446 .id = 2,
442 .parent = &clk_pclk_psys.clk, 447 .parent = &clk_pclk_psys.clk,
443 .enable = s5pv210_clk_ip3_ctrl, 448 .enable = s5pv210_clk_ip3_ctrl,
444 .ctrlbit = (1<<9), 449 .ctrlbit = (1 << 19),
445 }, { 450 }, {
446 .name = "uart", 451 .name = "uart",
447 .id = 3, 452 .id = 3,
448 .parent = &clk_pclk_psys.clk, 453 .parent = &clk_pclk_psys.clk,
449 .enable = s5pv210_clk_ip3_ctrl, 454 .enable = s5pv210_clk_ip3_ctrl,
450 .ctrlbit = (1<<10), 455 .ctrlbit = (1 << 20),
451 }, 456 },
452}; 457};
453 458
@@ -497,8 +502,8 @@ static struct clksrc_clk clk_sclk_dac = {
497 .clk = { 502 .clk = {
498 .name = "sclk_dac", 503 .name = "sclk_dac",
499 .id = -1, 504 .id = -1,
500 .ctrlbit = (1 << 10), 505 .enable = s5pv210_clk_mask0_ctrl,
501 .enable = s5pv210_clk_ip1_ctrl, 506 .ctrlbit = (1 << 2),
502 }, 507 },
503 .sources = &clkset_sclk_dac, 508 .sources = &clkset_sclk_dac,
504 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 }, 509 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 1 },
@@ -527,8 +532,8 @@ static struct clksrc_clk clk_sclk_hdmi = {
527 .clk = { 532 .clk = {
528 .name = "sclk_hdmi", 533 .name = "sclk_hdmi",
529 .id = -1, 534 .id = -1,
530 .enable = s5pv210_clk_ip1_ctrl, 535 .enable = s5pv210_clk_mask0_ctrl,
531 .ctrlbit = (1 << 11), 536 .ctrlbit = (1 << 0),
532 }, 537 },
533 .sources = &clkset_sclk_hdmi, 538 .sources = &clkset_sclk_hdmi,
534 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 }, 539 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
@@ -565,8 +570,8 @@ static struct clksrc_clk clk_sclk_audio0 = {
565 .clk = { 570 .clk = {
566 .name = "sclk_audio", 571 .name = "sclk_audio",
567 .id = 0, 572 .id = 0,
568 .enable = s5pv210_clk_ip3_ctrl, 573 .enable = s5pv210_clk_mask0_ctrl,
569 .ctrlbit = (1 << 4), 574 .ctrlbit = (1 << 24),
570 }, 575 },
571 .sources = &clkset_sclk_audio0, 576 .sources = &clkset_sclk_audio0,
572 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 }, 577 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 0, .size = 4 },
@@ -594,8 +599,8 @@ static struct clksrc_clk clk_sclk_audio1 = {
594 .clk = { 599 .clk = {
595 .name = "sclk_audio", 600 .name = "sclk_audio",
596 .id = 1, 601 .id = 1,
597 .enable = s5pv210_clk_ip3_ctrl, 602 .enable = s5pv210_clk_mask0_ctrl,
598 .ctrlbit = (1 << 5), 603 .ctrlbit = (1 << 25),
599 }, 604 },
600 .sources = &clkset_sclk_audio1, 605 .sources = &clkset_sclk_audio1,
601 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 }, 606 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 4, .size = 4 },
@@ -623,8 +628,8 @@ static struct clksrc_clk clk_sclk_audio2 = {
623 .clk = { 628 .clk = {
624 .name = "sclk_audio", 629 .name = "sclk_audio",
625 .id = 2, 630 .id = 2,
626 .enable = s5pv210_clk_ip3_ctrl, 631 .enable = s5pv210_clk_mask0_ctrl,
627 .ctrlbit = (1 << 6), 632 .ctrlbit = (1 << 26),
628 }, 633 },
629 .sources = &clkset_sclk_audio2, 634 .sources = &clkset_sclk_audio2,
630 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 }, 635 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 8, .size = 4 },
@@ -680,8 +685,8 @@ static struct clksrc_clk clksrcs[] = {
680 .clk = { 685 .clk = {
681 .name = "uclk1", 686 .name = "uclk1",
682 .id = 0, 687 .id = 0,
683 .ctrlbit = (1<<17), 688 .enable = s5pv210_clk_mask0_ctrl,
684 .enable = s5pv210_clk_ip3_ctrl, 689 .ctrlbit = (1 << 12),
685 }, 690 },
686 .sources = &clkset_uart, 691 .sources = &clkset_uart,
687 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 }, 692 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
@@ -690,8 +695,8 @@ static struct clksrc_clk clksrcs[] = {
690 .clk = { 695 .clk = {
691 .name = "uclk1", 696 .name = "uclk1",
692 .id = 1, 697 .id = 1,
693 .enable = s5pv210_clk_ip3_ctrl, 698 .enable = s5pv210_clk_mask0_ctrl,
694 .ctrlbit = (1 << 18), 699 .ctrlbit = (1 << 13),
695 }, 700 },
696 .sources = &clkset_uart, 701 .sources = &clkset_uart,
697 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 }, 702 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
@@ -700,8 +705,8 @@ static struct clksrc_clk clksrcs[] = {
700 .clk = { 705 .clk = {
701 .name = "uclk1", 706 .name = "uclk1",
702 .id = 2, 707 .id = 2,
703 .enable = s5pv210_clk_ip3_ctrl, 708 .enable = s5pv210_clk_mask0_ctrl,
704 .ctrlbit = (1 << 19), 709 .ctrlbit = (1 << 14),
705 }, 710 },
706 .sources = &clkset_uart, 711 .sources = &clkset_uart,
707 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 }, 712 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
@@ -710,8 +715,8 @@ static struct clksrc_clk clksrcs[] = {
710 .clk = { 715 .clk = {
711 .name = "uclk1", 716 .name = "uclk1",
712 .id = 3, 717 .id = 3,
713 .enable = s5pv210_clk_ip3_ctrl, 718 .enable = s5pv210_clk_mask0_ctrl,
714 .ctrlbit = (1 << 20), 719 .ctrlbit = (1 << 15),
715 }, 720 },
716 .sources = &clkset_uart, 721 .sources = &clkset_uart,
717 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 }, 722 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
@@ -720,8 +725,8 @@ static struct clksrc_clk clksrcs[] = {
720 .clk = { 725 .clk = {
721 .name = "sclk_mixer", 726 .name = "sclk_mixer",
722 .id = -1, 727 .id = -1,
723 .enable = s5pv210_clk_ip1_ctrl, 728 .enable = s5pv210_clk_mask0_ctrl,
724 .ctrlbit = (1 << 9), 729 .ctrlbit = (1 << 1),
725 }, 730 },
726 .sources = &clkset_sclk_mixer, 731 .sources = &clkset_sclk_mixer,
727 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 }, 732 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 1 },
@@ -738,8 +743,8 @@ static struct clksrc_clk clksrcs[] = {
738 .clk = { 743 .clk = {
739 .name = "sclk_fimc", 744 .name = "sclk_fimc",
740 .id = 0, 745 .id = 0,
741 .enable = s5pv210_clk_ip0_ctrl, 746 .enable = s5pv210_clk_mask1_ctrl,
742 .ctrlbit = (1 << 24), 747 .ctrlbit = (1 << 2),
743 }, 748 },
744 .sources = &clkset_group2, 749 .sources = &clkset_group2,
745 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 }, 750 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
@@ -748,8 +753,8 @@ static struct clksrc_clk clksrcs[] = {
748 .clk = { 753 .clk = {
749 .name = "sclk_fimc", 754 .name = "sclk_fimc",
750 .id = 1, 755 .id = 1,
751 .enable = s5pv210_clk_ip0_ctrl, 756 .enable = s5pv210_clk_mask1_ctrl,
752 .ctrlbit = (1 << 25), 757 .ctrlbit = (1 << 3),
753 }, 758 },
754 .sources = &clkset_group2, 759 .sources = &clkset_group2,
755 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 }, 760 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
@@ -758,8 +763,8 @@ static struct clksrc_clk clksrcs[] = {
758 .clk = { 763 .clk = {
759 .name = "sclk_fimc", 764 .name = "sclk_fimc",
760 .id = 2, 765 .id = 2,
761 .enable = s5pv210_clk_ip0_ctrl, 766 .enable = s5pv210_clk_mask1_ctrl,
762 .ctrlbit = (1 << 26), 767 .ctrlbit = (1 << 4),
763 }, 768 },
764 .sources = &clkset_group2, 769 .sources = &clkset_group2,
765 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 }, 770 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
@@ -768,6 +773,8 @@ static struct clksrc_clk clksrcs[] = {
768 .clk = { 773 .clk = {
769 .name = "sclk_cam", 774 .name = "sclk_cam",
770 .id = 0, 775 .id = 0,
776 .enable = s5pv210_clk_mask0_ctrl,
777 .ctrlbit = (1 << 3),
771 }, 778 },
772 .sources = &clkset_group2, 779 .sources = &clkset_group2,
773 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 }, 780 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
@@ -776,6 +783,8 @@ static struct clksrc_clk clksrcs[] = {
776 .clk = { 783 .clk = {
777 .name = "sclk_cam", 784 .name = "sclk_cam",
778 .id = 1, 785 .id = 1,
786 .enable = s5pv210_clk_mask0_ctrl,
787 .ctrlbit = (1 << 4),
779 }, 788 },
780 .sources = &clkset_group2, 789 .sources = &clkset_group2,
781 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 }, 790 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
@@ -784,8 +793,8 @@ static struct clksrc_clk clksrcs[] = {
784 .clk = { 793 .clk = {
785 .name = "sclk_fimd", 794 .name = "sclk_fimd",
786 .id = -1, 795 .id = -1,
787 .enable = s5pv210_clk_ip1_ctrl, 796 .enable = s5pv210_clk_mask0_ctrl,
788 .ctrlbit = (1 << 0), 797 .ctrlbit = (1 << 5),
789 }, 798 },
790 .sources = &clkset_group2, 799 .sources = &clkset_group2,
791 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 }, 800 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
@@ -794,8 +803,8 @@ static struct clksrc_clk clksrcs[] = {
794 .clk = { 803 .clk = {
795 .name = "sclk_mmc", 804 .name = "sclk_mmc",
796 .id = 0, 805 .id = 0,
797 .enable = s5pv210_clk_ip2_ctrl, 806 .enable = s5pv210_clk_mask0_ctrl,
798 .ctrlbit = (1 << 16), 807 .ctrlbit = (1 << 8),
799 }, 808 },
800 .sources = &clkset_group2, 809 .sources = &clkset_group2,
801 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 }, 810 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
@@ -804,8 +813,8 @@ static struct clksrc_clk clksrcs[] = {
804 .clk = { 813 .clk = {
805 .name = "sclk_mmc", 814 .name = "sclk_mmc",
806 .id = 1, 815 .id = 1,
807 .enable = s5pv210_clk_ip2_ctrl, 816 .enable = s5pv210_clk_mask0_ctrl,
808 .ctrlbit = (1 << 17), 817 .ctrlbit = (1 << 9),
809 }, 818 },
810 .sources = &clkset_group2, 819 .sources = &clkset_group2,
811 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 }, 820 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
@@ -814,8 +823,8 @@ static struct clksrc_clk clksrcs[] = {
814 .clk = { 823 .clk = {
815 .name = "sclk_mmc", 824 .name = "sclk_mmc",
816 .id = 2, 825 .id = 2,
817 .enable = s5pv210_clk_ip2_ctrl, 826 .enable = s5pv210_clk_mask0_ctrl,
818 .ctrlbit = (1 << 18), 827 .ctrlbit = (1 << 10),
819 }, 828 },
820 .sources = &clkset_group2, 829 .sources = &clkset_group2,
821 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 }, 830 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
@@ -824,8 +833,8 @@ static struct clksrc_clk clksrcs[] = {
824 .clk = { 833 .clk = {
825 .name = "sclk_mmc", 834 .name = "sclk_mmc",
826 .id = 3, 835 .id = 3,
827 .enable = s5pv210_clk_ip2_ctrl, 836 .enable = s5pv210_clk_mask0_ctrl,
828 .ctrlbit = (1 << 19), 837 .ctrlbit = (1 << 11),
829 }, 838 },
830 .sources = &clkset_group2, 839 .sources = &clkset_group2,
831 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 }, 840 .reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
@@ -864,8 +873,8 @@ static struct clksrc_clk clksrcs[] = {
864 .clk = { 873 .clk = {
865 .name = "sclk_csis", 874 .name = "sclk_csis",
866 .id = -1, 875 .id = -1,
867 .enable = s5pv210_clk_ip0_ctrl, 876 .enable = s5pv210_clk_mask0_ctrl,
868 .ctrlbit = (1 << 31), 877 .ctrlbit = (1 << 6),
869 }, 878 },
870 .sources = &clkset_group2, 879 .sources = &clkset_group2,
871 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 }, 880 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
@@ -874,8 +883,8 @@ static struct clksrc_clk clksrcs[] = {
874 .clk = { 883 .clk = {
875 .name = "sclk_spi", 884 .name = "sclk_spi",
876 .id = 0, 885 .id = 0,
877 .enable = s5pv210_clk_ip3_ctrl, 886 .enable = s5pv210_clk_mask0_ctrl,
878 .ctrlbit = (1 << 12), 887 .ctrlbit = (1 << 16),
879 }, 888 },
880 .sources = &clkset_group2, 889 .sources = &clkset_group2,
881 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 }, 890 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
@@ -884,8 +893,8 @@ static struct clksrc_clk clksrcs[] = {
884 .clk = { 893 .clk = {
885 .name = "sclk_spi", 894 .name = "sclk_spi",
886 .id = 1, 895 .id = 1,
887 .enable = s5pv210_clk_ip3_ctrl, 896 .enable = s5pv210_clk_mask0_ctrl,
888 .ctrlbit = (1 << 13), 897 .ctrlbit = (1 << 17),
889 }, 898 },
890 .sources = &clkset_group2, 899 .sources = &clkset_group2,
891 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 }, 900 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
@@ -894,8 +903,8 @@ static struct clksrc_clk clksrcs[] = {
894 .clk = { 903 .clk = {
895 .name = "sclk_pwi", 904 .name = "sclk_pwi",
896 .id = -1, 905 .id = -1,
897 .enable = &s5pv210_clk_ip4_ctrl, 906 .enable = s5pv210_clk_mask0_ctrl,
898 .ctrlbit = (1 << 2), 907 .ctrlbit = (1 << 29),
899 }, 908 },
900 .sources = &clkset_group2, 909 .sources = &clkset_group2,
901 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 }, 910 .reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
@@ -904,8 +913,8 @@ static struct clksrc_clk clksrcs[] = {
904 .clk = { 913 .clk = {
905 .name = "sclk_pwm", 914 .name = "sclk_pwm",
906 .id = -1, 915 .id = -1,
907 .enable = s5pv210_clk_ip3_ctrl, 916 .enable = s5pv210_clk_mask0_ctrl,
908 .ctrlbit = (1 << 23), 917 .ctrlbit = (1 << 19),
909 }, 918 },
910 .sources = &clkset_group2, 919 .sources = &clkset_group2,
911 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 }, 920 .reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
generated by cgit v1.2.2 (git 2.25.0) at 2025-11-11 17:35:44 -0500