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authorDaniel Ribeiro <drwyrm@gmail.com>2009-05-28 14:43:37 -0400
committerSamuel Ortiz <sameol@linux.intel.com>2009-06-17 13:41:35 -0400
commit13a09f93d2bf3a20c748e1d6a30160a00fc58169 (patch)
tree1dab40fb0cdf9c4a559d6b9a92a29a4cd98032d6
parent14fa56917d73d823538151b0429d98211fa439c1 (diff)
mfd: add PCAP driver
The PCAP Asic as present on EZX phones is a multi function device with voltage regulators, ADC, touch screen controller, RTC, USB transceiver, leds controller, and audio codec. It has two SPI ports, typically one is connected to the application processor and another to the baseband, this driver provides read/write functions to its registers, irq demultiplexer and ADC queueing/abstraction. This chip is used on a lot of Motorola phones, it was manufactured by TI as a custom product with the name PTWL93017, later this design evolved into the ATLAS PMIC from Freescale (MC13783). Signed-off-by: Daniel Ribeiro <drwyrm@gmail.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
Diffstat
-rw-r--r--drivers/mfd/Kconfig7
-rw-r--r--drivers/mfd/Makefile2
-rw-r--r--drivers/mfd/ezx-pcap.c505
-rw-r--r--include/linux/mfd/ezx-pcap.h256
4 files changed, 770 insertions, 0 deletions
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 61f0346650b3..287d47b78e7b 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -255,6 +255,13 @@ config AB3100_CORE
255 LEDs, vibrator, system power and temperature, power management 255 LEDs, vibrator, system power and temperature, power management
256 and ALSA sound. 256 and ALSA sound.
257 257
258config EZX_PCAP
259 bool "PCAP Support"
260 depends on GENERIC_HARDIRQS && SPI_MASTER
261 help
262 This enables the PCAP ASIC present on EZX Phones. This is
263 needed for MMC, TouchScreen, Sound, USB, etc..
264
258endmenu 265endmenu
259 266
260menu "Multimedia Capabilities Port drivers" 267menu "Multimedia Capabilities Port drivers"
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index f5f337143e69..6f8a9a1af20b 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -26,6 +26,8 @@ obj-$(CONFIG_TWL4030_CORE) += twl4030-core.o twl4030-irq.o
26 26
27obj-$(CONFIG_MFD_CORE) += mfd-core.o 27obj-$(CONFIG_MFD_CORE) += mfd-core.o
28 28
29obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o
30
29obj-$(CONFIG_MCP) += mcp-core.o 31obj-$(CONFIG_MCP) += mcp-core.o
30obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o 32obj-$(CONFIG_MCP_SA11X0) += mcp-sa11x0.o
31obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o 33obj-$(CONFIG_MCP_UCB1200) += ucb1x00-core.o
diff --git a/drivers/mfd/ezx-pcap.c b/drivers/mfd/ezx-pcap.c
new file mode 100644
index 000000000000..671a7efe86a8
--- /dev/null
+++ b/drivers/mfd/ezx-pcap.c
@@ -0,0 +1,505 @@
1/*
2 * Driver for Motorola PCAP2 as present in EZX phones
3 *
4 * Copyright (C) 2006 Harald Welte <laforge@openezx.org>
5 * Copyright (C) 2009 Daniel Ribeiro <drwyrm@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#include <linux/module.h>
14#include <linux/kernel.h>
15#include <linux/platform_device.h>
16#include <linux/interrupt.h>
17#include <linux/irq.h>
18#include <linux/mfd/ezx-pcap.h>
19#include <linux/spi/spi.h>
20
21#define PCAP_ADC_MAXQ 8
22struct pcap_adc_request {
23 u8 bank;
24 u8 ch[2];
25 u32 flags;
26 void (*callback)(void *, u16[]);
27 void *data;
28};
29
30struct pcap_adc_sync_request {
31 u16 res[2];
32 struct completion completion;
33};
34
35struct pcap_chip {
36 struct spi_device *spi;
37
38 /* IO */
39 u32 buf;
40 struct mutex io_mutex;
41
42 /* IRQ */
43 unsigned int irq_base;
44 u32 msr;
45 struct work_struct isr_work;
46 struct work_struct msr_work;
47 struct workqueue_struct *workqueue;
48
49 /* ADC */
50 struct pcap_adc_request *adc_queue[PCAP_ADC_MAXQ];
51 u8 adc_head;
52 u8 adc_tail;
53 struct mutex adc_mutex;
54};
55
56/* IO */
57static int ezx_pcap_putget(struct pcap_chip *pcap, u32 *data)
58{
59 struct spi_transfer t;
60 struct spi_message m;
61 int status;
62
63 memset(&t, 0, sizeof t);
64 spi_message_init(&m);
65 t.len = sizeof(u32);
66 spi_message_add_tail(&t, &m);
67
68 pcap->buf = *data;
69 t.tx_buf = (u8 *) &pcap->buf;
70 t.rx_buf = (u8 *) &pcap->buf;
71 status = spi_sync(pcap->spi, &m);
72
73 if (status == 0)
74 *data = pcap->buf;
75
76 return status;
77}
78
79int ezx_pcap_write(struct pcap_chip *pcap, u8 reg_num, u32 value)
80{
81 int ret;
82
83 mutex_lock(&pcap->io_mutex);
84 value &= PCAP_REGISTER_VALUE_MASK;
85 value |= PCAP_REGISTER_WRITE_OP_BIT
86 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
87 ret = ezx_pcap_putget(pcap, &value);
88 mutex_unlock(&pcap->io_mutex);
89
90 return ret;
91}
92EXPORT_SYMBOL_GPL(ezx_pcap_write);
93
94int ezx_pcap_read(struct pcap_chip *pcap, u8 reg_num, u32 *value)
95{
96 int ret;
97
98 mutex_lock(&pcap->io_mutex);
99 *value = PCAP_REGISTER_READ_OP_BIT
100 | (reg_num << PCAP_REGISTER_ADDRESS_SHIFT);
101
102 ret = ezx_pcap_putget(pcap, value);
103 mutex_unlock(&pcap->io_mutex);
104
105 return ret;
106}
107EXPORT_SYMBOL_GPL(ezx_pcap_read);
108
109/* IRQ */
110static inline unsigned int irq2pcap(struct pcap_chip *pcap, int irq)
111{
112 return 1 << (irq - pcap->irq_base);
113}
114
115int pcap_to_irq(struct pcap_chip *pcap, int irq)
116{
117 return pcap->irq_base + irq;
118}
119EXPORT_SYMBOL_GPL(pcap_to_irq);
120
121static void pcap_mask_irq(unsigned int irq)
122{
123 struct pcap_chip *pcap = get_irq_chip_data(irq);
124
125 pcap->msr |= irq2pcap(pcap, irq);
126 queue_work(pcap->workqueue, &pcap->msr_work);
127}
128
129static void pcap_unmask_irq(unsigned int irq)
130{
131 struct pcap_chip *pcap = get_irq_chip_data(irq);
132
133 pcap->msr &= ~irq2pcap(pcap, irq);
134 queue_work(pcap->workqueue, &pcap->msr_work);
135}
136
137static struct irq_chip pcap_irq_chip = {
138 .name = "pcap",
139 .mask = pcap_mask_irq,
140 .unmask = pcap_unmask_irq,
141};
142
143static void pcap_msr_work(struct work_struct *work)
144{
145 struct pcap_chip *pcap = container_of(work, struct pcap_chip, msr_work);
146
147 ezx_pcap_write(pcap, PCAP_REG_MSR, pcap->msr);
148}
149
150static void pcap_isr_work(struct work_struct *work)
151{
152 struct pcap_chip *pcap = container_of(work, struct pcap_chip, isr_work);
153 struct pcap_platform_data *pdata = pcap->spi->dev.platform_data;
154 u32 msr, isr, int_sel, service;
155 int irq;
156
157 ezx_pcap_read(pcap, PCAP_REG_MSR, &msr);
158 ezx_pcap_read(pcap, PCAP_REG_ISR, &isr);
159
160 /* We cant service/ack irqs that are assigned to port 2 */
161 if (!(pdata->config & PCAP_SECOND_PORT)) {
162 ezx_pcap_read(pcap, PCAP_REG_INT_SEL, &int_sel);
163 isr &= ~int_sel;
164 }
165 ezx_pcap_write(pcap, PCAP_REG_ISR, isr);
166
167 local_irq_disable();
168 service = isr & ~msr;
169
170 for (irq = pcap->irq_base; service; service >>= 1, irq++) {
171 if (service & 1) {
172 struct irq_desc *desc = irq_to_desc(irq);
173
174 if (WARN(!desc, KERN_WARNING
175 "Invalid PCAP IRQ %d\n", irq))
176 break;
177
178 if (desc->status & IRQ_DISABLED)
179 note_interrupt(irq, desc, IRQ_NONE);
180 else
181 desc->handle_irq(irq, desc);
182 }
183 }
184 local_irq_enable();
185}
186
187static void pcap_irq_handler(unsigned int irq, struct irq_desc *desc)
188{
189 struct pcap_chip *pcap = get_irq_data(irq);
190
191 desc->chip->ack(irq);
192 queue_work(pcap->workqueue, &pcap->isr_work);
193 return;
194}
195
196/* ADC */
197static void pcap_disable_adc(struct pcap_chip *pcap)
198{
199 u32 tmp;
200
201 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
202 tmp &= ~(PCAP_ADC_ADEN|PCAP_ADC_BATT_I_ADC|PCAP_ADC_BATT_I_POLARITY);
203 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
204}
205
206static void pcap_adc_trigger(struct pcap_chip *pcap)
207{
208 u32 tmp;
209 u8 head;
210
211 mutex_lock(&pcap->adc_mutex);
212 head = pcap->adc_head;
213 if (!pcap->adc_queue[head]) {
214 /* queue is empty, save power */
215 pcap_disable_adc(pcap);
216 mutex_unlock(&pcap->adc_mutex);
217 return;
218 }
219 mutex_unlock(&pcap->adc_mutex);
220
221 /* start conversion on requested bank */
222 tmp = pcap->adc_queue[head]->flags | PCAP_ADC_ADEN;
223
224 if (pcap->adc_queue[head]->bank == PCAP_ADC_BANK_1)
225 tmp |= PCAP_ADC_AD_SEL1;
226
227 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
228 ezx_pcap_write(pcap, PCAP_REG_ADR, PCAP_ADR_ASC);
229}
230
231static irqreturn_t pcap_adc_irq(int irq, void *_pcap)
232{
233 struct pcap_chip *pcap = _pcap;
234 struct pcap_adc_request *req;
235 u16 res[2];
236 u32 tmp;
237
238 mutex_lock(&pcap->adc_mutex);
239 req = pcap->adc_queue[pcap->adc_head];
240
241 if (WARN(!req, KERN_WARNING "adc irq without pending request\n"))
242 return IRQ_HANDLED;
243
244 /* read requested channels results */
245 ezx_pcap_read(pcap, PCAP_REG_ADC, &tmp);
246 tmp &= ~(PCAP_ADC_ADA1_MASK | PCAP_ADC_ADA2_MASK);
247 tmp |= (req->ch[0] << PCAP_ADC_ADA1_SHIFT);
248 tmp |= (req->ch[1] << PCAP_ADC_ADA2_SHIFT);
249 ezx_pcap_write(pcap, PCAP_REG_ADC, tmp);
250 ezx_pcap_read(pcap, PCAP_REG_ADR, &tmp);
251 res[0] = (tmp & PCAP_ADR_ADD1_MASK) >> PCAP_ADR_ADD1_SHIFT;
252 res[1] = (tmp & PCAP_ADR_ADD2_MASK) >> PCAP_ADR_ADD2_SHIFT;
253
254 pcap->adc_queue[pcap->adc_head] = NULL;
255 pcap->adc_head = (pcap->adc_head + 1) & (PCAP_ADC_MAXQ - 1);
256 mutex_unlock(&pcap->adc_mutex);
257
258 /* pass the results and release memory */
259 req->callback(req->data, res);
260 kfree(req);
261
262 /* trigger next conversion (if any) on queue */
263 pcap_adc_trigger(pcap);
264
265 return IRQ_HANDLED;
266}
267
268int pcap_adc_async(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
269 void *callback, void *data)
270{
271 struct pcap_adc_request *req;
272
273 /* This will be freed after we have a result */
274 req = kmalloc(sizeof(struct pcap_adc_request), GFP_KERNEL);
275 if (!req)
276 return -ENOMEM;
277
278 req->bank = bank;
279 req->flags = flags;
280 req->ch[0] = ch[0];
281 req->ch[1] = ch[1];
282 req->callback = callback;
283 req->data = data;
284
285 mutex_lock(&pcap->adc_mutex);
286 if (pcap->adc_queue[pcap->adc_tail]) {
287 mutex_unlock(&pcap->adc_mutex);
288 kfree(req);
289 return -EBUSY;
290 }
291 pcap->adc_queue[pcap->adc_tail] = req;
292 pcap->adc_tail = (pcap->adc_tail + 1) & (PCAP_ADC_MAXQ - 1);
293 mutex_unlock(&pcap->adc_mutex);
294
295 /* start conversion */
296 pcap_adc_trigger(pcap);
297
298 return 0;
299}
300EXPORT_SYMBOL_GPL(pcap_adc_async);
301
302static void pcap_adc_sync_cb(void *param, u16 res[])
303{
304 struct pcap_adc_sync_request *req = param;
305
306 req->res[0] = res[0];
307 req->res[1] = res[1];
308 complete(&req->completion);
309}
310
311int pcap_adc_sync(struct pcap_chip *pcap, u8 bank, u32 flags, u8 ch[],
312 u16 res[])
313{
314 struct pcap_adc_sync_request sync_data;
315 int ret;
316
317 init_completion(&sync_data.completion);
318 ret = pcap_adc_async(pcap, bank, flags, ch, pcap_adc_sync_cb,
319 &sync_data);
320 if (ret)
321 return ret;
322 wait_for_completion(&sync_data.completion);
323 res[0] = sync_data.res[0];
324 res[1] = sync_data.res[1];
325
326 return 0;
327}
328EXPORT_SYMBOL_GPL(pcap_adc_sync);
329
330/* subdevs */
331static int pcap_remove_subdev(struct device *dev, void *unused)
332{
333 platform_device_unregister(to_platform_device(dev));
334 return 0;
335}
336
337static int __devinit pcap_add_subdev(struct pcap_chip *pcap,
338 struct pcap_subdev *subdev)
339{
340 struct platform_device *pdev;
341
342 pdev = platform_device_alloc(subdev->name, subdev->id);
343 pdev->dev.parent = &pcap->spi->dev;
344 pdev->dev.platform_data = subdev->platform_data;
345 platform_set_drvdata(pdev, pcap);
346
347 return platform_device_add(pdev);
348}
349
350static int __devexit ezx_pcap_remove(struct spi_device *spi)
351{
352 struct pcap_chip *pcap = dev_get_drvdata(&spi->dev);
353 struct pcap_platform_data *pdata = spi->dev.platform_data;
354 int i, adc_irq;
355
356 /* remove all registered subdevs */
357 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
358
359 /* cleanup ADC */
360 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
361 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
362 free_irq(adc_irq, pcap);
363 mutex_lock(&pcap->adc_mutex);
364 for (i = 0; i < PCAP_ADC_MAXQ; i++)
365 kfree(pcap->adc_queue[i]);
366 mutex_unlock(&pcap->adc_mutex);
367
368 /* cleanup irqchip */
369 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
370 set_irq_chip_and_handler(i, NULL, NULL);
371
372 destroy_workqueue(pcap->workqueue);
373
374 kfree(pcap);
375
376 return 0;
377}
378
379static int __devinit ezx_pcap_probe(struct spi_device *spi)
380{
381 struct pcap_platform_data *pdata = spi->dev.platform_data;
382 struct pcap_chip *pcap;
383 int i, adc_irq;
384 int ret = -ENODEV;
385
386 /* platform data is required */
387 if (!pdata)
388 goto ret;
389
390 pcap = kzalloc(sizeof(*pcap), GFP_KERNEL);
391 if (!pcap) {
392 ret = -ENOMEM;
393 goto ret;
394 }
395
396 mutex_init(&pcap->io_mutex);
397 mutex_init(&pcap->adc_mutex);
398 INIT_WORK(&pcap->isr_work, pcap_isr_work);
399 INIT_WORK(&pcap->msr_work, pcap_msr_work);
400 dev_set_drvdata(&spi->dev, pcap);
401
402 /* setup spi */
403 spi->bits_per_word = 32;
404 spi->mode = SPI_MODE_0 | (pdata->config & PCAP_CS_AH ? SPI_CS_HIGH : 0);
405 ret = spi_setup(spi);
406 if (ret)
407 goto free_pcap;
408
409 pcap->spi = spi;
410
411 /* setup irq */
412 pcap->irq_base = pdata->irq_base;
413 pcap->workqueue = create_singlethread_workqueue("pcapd");
414 if (!pcap->workqueue) {
415 dev_err(&spi->dev, "cant create pcap thread\n");
416 goto free_pcap;
417 }
418
419 /* redirect interrupts to AP, except adcdone2 */
420 if (!(pdata->config & PCAP_SECOND_PORT))
421 ezx_pcap_write(pcap, PCAP_REG_INT_SEL,
422 (1 << PCAP_IRQ_ADCDONE2));
423
424 /* setup irq chip */
425 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++) {
426 set_irq_chip_and_handler(i, &pcap_irq_chip, handle_simple_irq);
427 set_irq_chip_data(i, pcap);
428#ifdef CONFIG_ARM
429 set_irq_flags(i, IRQF_VALID);
430#else
431 set_irq_noprobe(i);
432#endif
433 }
434
435 /* mask/ack all PCAP interrupts */
436 ezx_pcap_write(pcap, PCAP_REG_MSR, PCAP_MASK_ALL_INTERRUPT);
437 ezx_pcap_write(pcap, PCAP_REG_ISR, PCAP_CLEAR_INTERRUPT_REGISTER);
438 pcap->msr = PCAP_MASK_ALL_INTERRUPT;
439
440 set_irq_type(spi->irq, IRQ_TYPE_EDGE_RISING);
441 set_irq_data(spi->irq, pcap);
442 set_irq_chained_handler(spi->irq, pcap_irq_handler);
443 set_irq_wake(spi->irq, 1);
444
445 /* ADC */
446 adc_irq = pcap_to_irq(pcap, (pdata->config & PCAP_SECOND_PORT) ?
447 PCAP_IRQ_ADCDONE2 : PCAP_IRQ_ADCDONE);
448
449 ret = request_irq(adc_irq, pcap_adc_irq, 0, "ADC", pcap);
450 if (ret)
451 goto free_irqchip;
452
453 /* setup subdevs */
454 for (i = 0; i < pdata->num_subdevs; i++) {
455 ret = pcap_add_subdev(pcap, &pdata->subdevs[i]);
456 if (ret)
457 goto remove_subdevs;
458 }
459
460 /* board specific quirks */
461 if (pdata->init)
462 pdata->init(pcap);
463
464 return 0;
465
466remove_subdevs:
467 device_for_each_child(&spi->dev, NULL, pcap_remove_subdev);
468/* free_adc: */
469 free_irq(adc_irq, pcap);
470free_irqchip:
471 for (i = pcap->irq_base; i < (pcap->irq_base + PCAP_NIRQS); i++)
472 set_irq_chip_and_handler(i, NULL, NULL);
473/* destroy_workqueue: */
474 destroy_workqueue(pcap->workqueue);
475free_pcap:
476 kfree(pcap);
477ret:
478 return ret;
479}
480
481static struct spi_driver ezxpcap_driver = {
482 .probe = ezx_pcap_probe,
483 .remove = __devexit_p(ezx_pcap_remove),
484 .driver = {
485 .name = "ezx-pcap",
486 .owner = THIS_MODULE,
487 },
488};
489
490static int __init ezx_pcap_init(void)
491{
492 return spi_register_driver(&ezxpcap_driver);
493}
494
495static void __exit ezx_pcap_exit(void)
496{
497 spi_unregister_driver(&ezxpcap_driver);
498}
499
500module_init(ezx_pcap_init);
501module_exit(ezx_pcap_exit);
502
503MODULE_LICENSE("GPL");
504MODULE_AUTHOR("Daniel Ribeiro / Harald Welte");
505MODULE_DESCRIPTION("Motorola PCAP2 ASIC Driver");
diff --git a/include/linux/mfd/ezx-pcap.h b/include/linux/mfd/ezx-pcap.h
new file mode 100644
index 000000000000..c12c3c0932bf
--- /dev/null
+++ b/include/linux/mfd/ezx-pcap.h
@@ -0,0 +1,256 @@
1/*
2 * Copyright 2009 Daniel Ribeiro <drwyrm@gmail.com>
3 *
4 * For further information, please see http://wiki.openezx.org/PCAP2
5 */
6
7#ifndef EZX_PCAP_H
8#define EZX_PCAP_H
9
10struct pcap_subdev {
11 int id;
12 const char *name;
13 void *platform_data;
14};
15
16struct pcap_platform_data {
17 unsigned int irq_base;
18 unsigned int config;
19 void (*init) (void *); /* board specific init */
20 int num_subdevs;
21 struct pcap_subdev *subdevs;
22};
23
24struct pcap_chip;
25
26int ezx_pcap_write(struct pcap_chip *, u8, u32);
27int ezx_pcap_read(struct pcap_chip *, u8, u32 *);
28int pcap_to_irq(struct pcap_chip *, int);
29int pcap_adc_async(struct pcap_chip *, u8, u32, u8[], void *, void *);
30int pcap_adc_sync(struct pcap_chip *, u8, u32, u8[], u16[]);
31
32#define PCAP_SECOND_PORT 1
33#define PCAP_CS_AH 2
34
35#define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
36#define PCAP_REGISTER_READ_OP_BIT 0x00000000
37
38#define PCAP_REGISTER_VALUE_MASK 0x01ffffff
39#define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
40#define PCAP_REGISTER_ADDRESS_SHIFT 26
41#define PCAP_REGISTER_NUMBER 32
42#define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
43#define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
44
45/* registers acessible by both pcap ports */
46#define PCAP_REG_ISR 0x0 /* Interrupt Status */
47#define PCAP_REG_MSR 0x1 /* Interrupt Mask */
48#define PCAP_REG_PSTAT 0x2 /* Processor Status */
49#define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
50#define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
51#define PCAP_REG_BATT 0x8 /* Battery Control */
52#define PCAP_REG_ADC 0x9 /* AD Control */
53#define PCAP_REG_ADR 0xa /* AD Result */
54#define PCAP_REG_CODEC 0xb /* Audio Codec Control */
55#define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
56#define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
57#define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
58#define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
59#define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
60#define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
61#define PCAP_REG_GP 0x1b /* General Purpose */
62#define PCAP_REG_TEST1 0x1c
63#define PCAP_REG_TEST2 0x1d
64#define PCAP_REG_VENDOR_TEST1 0x1e
65#define PCAP_REG_VENDOR_TEST2 0x1f
66
67/* registers acessible by pcap port 1 only (a1200, e2 & e6) */
68#define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
69#define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
70#define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
71#define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
72#define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
73#define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
74#define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
75#define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
76#define PCAP_REG_PWR 0x13 /* Power Control */
77#define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
78#define PCAP_REG_VENDOR_REV 0x17
79#define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
80
81/* PCAP2 Interrupts */
82#define PCAP_NIRQS 23
83#define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
84#define PCAP_IRQ_TS 1 /* Touch Screen */
85#define PCAP_IRQ_1HZ 2 /* 1HZ timer */
86#define PCAP_IRQ_WH 3 /* ADC above high limit */
87#define PCAP_IRQ_WL 4 /* ADC below low limit */
88#define PCAP_IRQ_TODA 5 /* Time of day alarm */
89#define PCAP_IRQ_USB4V 6 /* USB above 4V */
90#define PCAP_IRQ_ONOFF 7 /* On/Off button */
91#define PCAP_IRQ_ONOFF2 8 /* On/Off button 2 */
92#define PCAP_IRQ_USB1V 9 /* USB above 1V */
93#define PCAP_IRQ_MOBPORT 10
94#define PCAP_IRQ_MIC 11 /* Mic attach/HS button */
95#define PCAP_IRQ_HS 12 /* Headset attach */
96#define PCAP_IRQ_ST 13
97#define PCAP_IRQ_PC 14 /* Power Cut */
98#define PCAP_IRQ_WARM 15
99#define PCAP_IRQ_EOL 16 /* Battery End Of Life */
100#define PCAP_IRQ_CLK 17
101#define PCAP_IRQ_SYSRST 18 /* System Reset */
102#define PCAP_IRQ_DUMMY 19
103#define PCAP_IRQ_ADCDONE2 20 /* ADC done port 2 */
104#define PCAP_IRQ_SOFTRESET 21
105#define PCAP_IRQ_MNEXB 22
106
107/* voltage regulators */
108#define V1 0
109#define V2 1
110#define V3 2
111#define V4 3
112#define V5 4
113#define V6 5
114#define V7 6
115#define V8 7
116#define V9 8
117#define V10 9
118#define VAUX1 10
119#define VAUX2 11
120#define VAUX3 12
121#define VAUX4 13
122#define VSIM 14
123#define VSIM2 15
124#define VVIB 16
125#define SW1 17
126#define SW2 18
127#define SW3 19
128#define SW1S 20
129#define SW2S 21
130
131#define PCAP_BATT_DAC_MASK 0x000000ff
132#define PCAP_BATT_DAC_SHIFT 0
133#define PCAP_BATT_B_FDBK (1 << 8)
134#define PCAP_BATT_EXT_ISENSE (1 << 9)
135#define PCAP_BATT_V_COIN_MASK 0x00003c00
136#define PCAP_BATT_V_COIN_SHIFT 10
137#define PCAP_BATT_I_COIN (1 << 14)
138#define PCAP_BATT_COIN_CH_EN (1 << 15)
139#define PCAP_BATT_EOL_SEL_MASK 0x000e0000
140#define PCAP_BATT_EOL_SEL_SHIFT 17
141#define PCAP_BATT_EOL_CMP_EN (1 << 20)
142#define PCAP_BATT_BATT_DET_EN (1 << 21)
143#define PCAP_BATT_THERMBIAS_CTRL (1 << 22)
144
145#define PCAP_ADC_ADEN (1 << 0)
146#define PCAP_ADC_RAND (1 << 1)
147#define PCAP_ADC_AD_SEL1 (1 << 2)
148#define PCAP_ADC_AD_SEL2 (1 << 3)
149#define PCAP_ADC_ADA1_MASK 0x00000070
150#define PCAP_ADC_ADA1_SHIFT 4
151#define PCAP_ADC_ADA2_MASK 0x00000380
152#define PCAP_ADC_ADA2_SHIFT 7
153#define PCAP_ADC_ATO_MASK 0x00003c00
154#define PCAP_ADC_ATO_SHIFT 10
155#define PCAP_ADC_ATOX (1 << 14)
156#define PCAP_ADC_MTR1 (1 << 15)
157#define PCAP_ADC_MTR2 (1 << 16)
158#define PCAP_ADC_TS_M_MASK 0x000e0000
159#define PCAP_ADC_TS_M_SHIFT 17
160#define PCAP_ADC_TS_REF_LOWPWR (1 << 20)
161#define PCAP_ADC_TS_REFENB (1 << 21)
162#define PCAP_ADC_BATT_I_POLARITY (1 << 22)
163#define PCAP_ADC_BATT_I_ADC (1 << 23)
164
165#define PCAP_ADC_BANK_0 0
166#define PCAP_ADC_BANK_1 1
167/* ADC bank 0 */
168#define PCAP_ADC_CH_COIN 0
169#define PCAP_ADC_CH_BATT 1
170#define PCAP_ADC_CH_BPLUS 2
171#define PCAP_ADC_CH_MOBPORTB 3
172#define PCAP_ADC_CH_TEMPERATURE 4
173#define PCAP_ADC_CH_CHARGER_ID 5
174#define PCAP_ADC_CH_AD6 6
175/* ADC bank 1 */
176#define PCAP_ADC_CH_AD7 0
177#define PCAP_ADC_CH_AD8 1
178#define PCAP_ADC_CH_AD9 2
179#define PCAP_ADC_CH_TS_X1 3
180#define PCAP_ADC_CH_TS_X2 4
181#define PCAP_ADC_CH_TS_Y1 5
182#define PCAP_ADC_CH_TS_Y2 6
183
184#define PCAP_ADC_T_NOW 0
185#define PCAP_ADC_T_IN_BURST 1
186#define PCAP_ADC_T_OUT_BURST 2
187
188#define PCAP_ADC_ATO_IN_BURST 6
189#define PCAP_ADC_ATO_OUT_BURST 0
190
191#define PCAP_ADC_TS_M_XY 1
192#define PCAP_ADC_TS_M_PRESSURE 2
193#define PCAP_ADC_TS_M_PLATE_X 3
194#define PCAP_ADC_TS_M_PLATE_Y 4
195#define PCAP_ADC_TS_M_STANDBY 5
196#define PCAP_ADC_TS_M_NONTS 6
197
198#define PCAP_ADR_ADD1_MASK 0x000003ff
199#define PCAP_ADR_ADD1_SHIFT 0
200#define PCAP_ADR_ADD2_MASK 0x000ffc00
201#define PCAP_ADR_ADD2_SHIFT 10
202#define PCAP_ADR_ADINC1 (1 << 20)
203#define PCAP_ADR_ADINC2 (1 << 21)
204#define PCAP_ADR_ASC (1 << 22)
205#define PCAP_ADR_ONESHOT (1 << 23)
206
207#define PCAP_BUSCTRL_FSENB (1 << 0)
208#define PCAP_BUSCTRL_USB_SUSPEND (1 << 1)
209#define PCAP_BUSCTRL_USB_PU (1 << 2)
210#define PCAP_BUSCTRL_USB_PD (1 << 3)
211#define PCAP_BUSCTRL_VUSB_EN (1 << 4)
212#define PCAP_BUSCTRL_USB_PS (1 << 5)
213#define PCAP_BUSCTRL_VUSB_MSTR_EN (1 << 6)
214#define PCAP_BUSCTRL_VBUS_PD_ENB (1 << 7)
215#define PCAP_BUSCTRL_CURRLIM (1 << 8)
216#define PCAP_BUSCTRL_RS232ENB (1 << 9)
217#define PCAP_BUSCTRL_RS232_DIR (1 << 10)
218#define PCAP_BUSCTRL_SE0_CONN (1 << 11)
219#define PCAP_BUSCTRL_USB_PDM (1 << 12)
220#define PCAP_BUSCTRL_BUS_PRI_ADJ (1 << 24)
221
222/* leds */
223#define PCAP_LED0 0
224#define PCAP_LED1 1
225#define PCAP_BL0 2
226#define PCAP_BL1 3
227#define PCAP_VIB 4
228#define PCAP_LED_3MA 0
229#define PCAP_LED_4MA 1
230#define PCAP_LED_5MA 2
231#define PCAP_LED_9MA 3
232#define PCAP_LED_GPIO_VAL_MASK 0x00ffffff
233#define PCAP_LED_GPIO_EN 0x01000000
234#define PCAP_LED_GPIO_INVERT 0x02000000
235#define PCAP_LED_T_MASK 0xf
236#define PCAP_LED_C_MASK 0x3
237#define PCAP_BL_MASK 0x1f
238#define PCAP_BL0_SHIFT 0
239#define PCAP_LED0_EN (1 << 5)
240#define PCAP_LED1_EN (1 << 6)
241#define PCAP_LED0_T_SHIFT 7
242#define PCAP_LED1_T_SHIFT 11
243#define PCAP_LED0_C_SHIFT 15
244#define PCAP_LED1_C_SHIFT 17
245#define PCAP_BL1_SHIFT 20
246#define PCAP_VIB_MASK 0x3
247#define PCAP_VIB_SHIFT 20
248#define PCAP_VIB_EN (1 << 19)
249
250/* RTC */
251#define PCAP_RTC_DAY_MASK 0x3fff
252#define PCAP_RTC_TOD_MASK 0xffff
253#define PCAP_RTC_PC_MASK 0x7
254#define SEC_PER_DAY 86400
255
256#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-30 17:34:59 -0400