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authorLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 15:17:06 -0400
committerLinus Torvalds <torvalds@linux-foundation.org>2012-03-28 15:17:06 -0400
commitff877c498eb2f9c4ea386270642e383bc867f63c (patch)
treeae37e2f57ac6e6d19d01b7380f77db2a1c6c5b14
parent529b73fc0a9764050dcc597f4851728e8ff59165 (diff)
parent1f5b7dcfdad3840d4bce27ab0b3cc8f376b81544 (diff)
Merge tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull "ARM: More SoC driver updates" from Olof Johansson: "This branch contains a handful of driver updates, mostly to the LPC32xx platform but also for Samsung EXYNOS and Davinci. It had a few context conflicts against patches already merged through fixes-non-critical. We should have resolved this early during the development cycle by pulling them in as a dependency, instead I did it after the fact this time." * tag 'drivers2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: gpio/samsung: use ioremap() for EXYNOS4 GPIOlib gpio/samsung: add support GPIOlib for EXYNOS5250 ARM: EXYNOS: add support GPIO for EXYNOS5250 ARM: LPC32xx: Ethernet support ARM: LPC32xx: USB Support ARM: davinci: dm644x evm: add support for VPBE display ARM: davinci: dm644x: add support for v4l2 video display ARM: EXYNOS: Hook up JPEG PD to generic PD infrastructure ARM: EXYNOS: Hook up G2D PD to generic PD infrastructure arm: lpc32xx: phy3250: add rtc & touch device ARM: LPC32xx: clock.c: Clock registration fixes ARM: LPC32xx: clock.c: jiffies wrapping ARM: LPC32xx: clock.c: Missing header file ARM: LPC32XX: Remove broken non-static declaration ARM: LPC32xx: clock.c: Fix mutex lock issues ARM: LPC32xx: clock.c: warning fix ARM: LPC32xx: Added lpc32xx_defconfig
Diffstat
-rw-r--r--arch/arm/mach-davinci/board-dm644x-evm.c109
-rw-r--r--arch/arm/mach-davinci/davinci.h8
-rw-r--r--arch/arm/mach-davinci/dm644x.c166
-rw-r--r--arch/arm/mach-exynos/common.c15
-rw-r--r--arch/arm/mach-exynos/include/mach/gpio.h239
-rw-r--r--arch/arm/mach-exynos/include/mach/map.h4
-rw-r--r--arch/arm/mach-exynos/pm_domains.c6
-rw-r--r--arch/arm/mach-lpc32xx/Kconfig25
-rw-r--r--arch/arm/mach-lpc32xx/clock.c87
-rw-r--r--arch/arm/mach-lpc32xx/common.c47
-rw-r--r--arch/arm/mach-lpc32xx/common.h4
-rw-r--r--arch/arm/mach-lpc32xx/include/mach/board.h24
-rw-r--r--arch/arm/mach-lpc32xx/irq.c4
-rw-r--r--arch/arm/mach-lpc32xx/phy3250.c3
-rw-r--r--drivers/gpio/gpio-samsung.c487
15 files changed, 1080 insertions, 148 deletions
diff --git a/arch/arm/mach-davinci/board-dm644x-evm.c b/arch/arm/mach-davinci/board-dm644x-evm.c
index 864f676eccac..3683306e0245 100644
--- a/arch/arm/mach-davinci/board-dm644x-evm.c
+++ b/arch/arm/mach-davinci/board-dm644x-evm.c
@@ -613,6 +613,113 @@ static void __init evm_init_i2c(void)
613 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); 613 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
614} 614}
615 615
616#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL)
617
618/* venc standard timings */
619static struct vpbe_enc_mode_info dm644xevm_enc_std_timing[] = {
620 {
621 .name = "ntsc",
622 .timings_type = VPBE_ENC_STD,
623 .timings = {V4L2_STD_525_60},
624 .interlaced = 1,
625 .xres = 720,
626 .yres = 480,
627 .aspect = {11, 10},
628 .fps = {30000, 1001},
629 .left_margin = 0x79,
630 .upper_margin = 0x10,
631 },
632 {
633 .name = "pal",
634 .timings_type = VPBE_ENC_STD,
635 .timings = {V4L2_STD_625_50},
636 .interlaced = 1,
637 .xres = 720,
638 .yres = 576,
639 .aspect = {54, 59},
640 .fps = {25, 1},
641 .left_margin = 0x7e,
642 .upper_margin = 0x16,
643 },
644};
645
646/* venc dv preset timings */
647static struct vpbe_enc_mode_info dm644xevm_enc_preset_timing[] = {
648 {
649 .name = "480p59_94",
650 .timings_type = VPBE_ENC_DV_PRESET,
651 .timings = {V4L2_DV_480P59_94},
652 .interlaced = 0,
653 .xres = 720,
654 .yres = 480,
655 .aspect = {1, 1},
656 .fps = {5994, 100},
657 .left_margin = 0x80,
658 .upper_margin = 0x20,
659 },
660 {
661 .name = "576p50",
662 .timings_type = VPBE_ENC_DV_PRESET,
663 .timings = {V4L2_DV_576P50},
664 .interlaced = 0,
665 .xres = 720,
666 .yres = 576,
667 .aspect = {1, 1},
668 .fps = {50, 1},
669 .left_margin = 0x7e,
670 .upper_margin = 0x30,
671 },
672};
673
674/*
675 * The outputs available from VPBE + encoders. Keep the order same
676 * as that of encoders. First those from venc followed by that from
677 * encoders. Index in the output refers to index on a particular encoder.
678 * Driver uses this index to pass it to encoder when it supports more
679 * than one output. Userspace applications use index of the array to
680 * set an output.
681 */
682static struct vpbe_output dm644xevm_vpbe_outputs[] = {
683 {
684 .output = {
685 .index = 0,
686 .name = "Composite",
687 .type = V4L2_OUTPUT_TYPE_ANALOG,
688 .std = VENC_STD_ALL,
689 .capabilities = V4L2_OUT_CAP_STD,
690 },
691 .subdev_name = VPBE_VENC_SUBDEV_NAME,
692 .default_mode = "ntsc",
693 .num_modes = ARRAY_SIZE(dm644xevm_enc_std_timing),
694 .modes = dm644xevm_enc_std_timing,
695 },
696 {
697 .output = {
698 .index = 1,
699 .name = "Component",
700 .type = V4L2_OUTPUT_TYPE_ANALOG,
701 .capabilities = V4L2_OUT_CAP_PRESETS,
702 },
703 .subdev_name = VPBE_VENC_SUBDEV_NAME,
704 .default_mode = "480p59_94",
705 .num_modes = ARRAY_SIZE(dm644xevm_enc_preset_timing),
706 .modes = dm644xevm_enc_preset_timing,
707 },
708};
709
710static struct vpbe_config dm644xevm_display_cfg = {
711 .module_name = "dm644x-vpbe-display",
712 .i2c_adapter_id = 1,
713 .osd = {
714 .module_name = VPBE_OSD_SUBDEV_NAME,
715 },
716 .venc = {
717 .module_name = VPBE_VENC_SUBDEV_NAME,
718 },
719 .num_outputs = ARRAY_SIZE(dm644xevm_vpbe_outputs),
720 .outputs = dm644xevm_vpbe_outputs,
721};
722
616static struct platform_device *davinci_evm_devices[] __initdata = { 723static struct platform_device *davinci_evm_devices[] __initdata = {
617 &davinci_fb_device, 724 &davinci_fb_device,
618 &rtc_dev, 725 &rtc_dev,
@@ -696,7 +803,7 @@ static __init void davinci_evm_init(void)
696 evm_init_i2c(); 803 evm_init_i2c();
697 804
698 davinci_setup_mmc(0, &dm6446evm_mmc_config); 805 davinci_setup_mmc(0, &dm6446evm_mmc_config);
699 dm644x_init_video(&dm644xevm_capture_cfg); 806 dm644x_init_video(&dm644xevm_capture_cfg, &dm644xevm_display_cfg);
700 807
701 davinci_serial_init(&uart_config); 808 davinci_serial_init(&uart_config);
702 dm644x_init_asp(&dm644x_evm_snd_data); 809 dm644x_init_asp(&dm644x_evm_snd_data);
diff --git a/arch/arm/mach-davinci/davinci.h b/arch/arm/mach-davinci/davinci.h
index 9d708034b57f..3e519dad5bb9 100644
--- a/arch/arm/mach-davinci/davinci.h
+++ b/arch/arm/mach-davinci/davinci.h
@@ -29,9 +29,15 @@
29 29
30#include <media/davinci/vpfe_capture.h> 30#include <media/davinci/vpfe_capture.h>
31#include <media/davinci/vpif_types.h> 31#include <media/davinci/vpif_types.h>
32#include <media/davinci/vpss.h>
33#include <media/davinci/vpbe_types.h>
34#include <media/davinci/vpbe_venc.h>
35#include <media/davinci/vpbe.h>
36#include <media/davinci/vpbe_osd.h>
32 37
33#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000 38#define DAVINCI_SYSTEM_MODULE_BASE 0x01c40000
34#define SYSMOD_VIDCLKCTL 0x38 39#define SYSMOD_VIDCLKCTL 0x38
40#define SYSMOD_VPSS_CLKCTL 0x44
35#define SYSMOD_VDD3P3VPWDN 0x48 41#define SYSMOD_VDD3P3VPWDN 0x48
36#define SYSMOD_VSCLKDIS 0x6c 42#define SYSMOD_VSCLKDIS 0x6c
37#define SYSMOD_PUPDCTL1 0x7c 43#define SYSMOD_PUPDCTL1 0x7c
@@ -83,7 +89,7 @@ void dm365_set_vpfe_config(struct vpfe_config *cfg);
83/* DM644x function declarations */ 89/* DM644x function declarations */
84void __init dm644x_init(void); 90void __init dm644x_init(void);
85void __init dm644x_init_asp(struct snd_platform_data *pdata); 91void __init dm644x_init_asp(struct snd_platform_data *pdata);
86int __init dm644x_init_video(struct vpfe_config *); 92int __init dm644x_init_video(struct vpfe_config *, struct vpbe_config *);
87 93
88/* DM646x function declarations */ 94/* DM646x function declarations */
89void __init dm646x_init(void); 95void __init dm646x_init(void);
diff --git a/arch/arm/mach-davinci/dm644x.c b/arch/arm/mach-davinci/dm644x.c
index 23e81cafba8d..c8b866657fcb 100644
--- a/arch/arm/mach-davinci/dm644x.c
+++ b/arch/arm/mach-davinci/dm644x.c
@@ -627,7 +627,7 @@ static struct resource dm644x_vpfe_resources[] = {
627 }, 627 },
628}; 628};
629 629
630static u64 vpfe_capture_dma_mask = DMA_BIT_MASK(32); 630static u64 dm644x_video_dma_mask = DMA_BIT_MASK(32);
631static struct resource dm644x_ccdc_resource[] = { 631static struct resource dm644x_ccdc_resource[] = {
632 /* CCDC Base address */ 632 /* CCDC Base address */
633 { 633 {
@@ -643,7 +643,7 @@ static struct platform_device dm644x_ccdc_dev = {
643 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource), 643 .num_resources = ARRAY_SIZE(dm644x_ccdc_resource),
644 .resource = dm644x_ccdc_resource, 644 .resource = dm644x_ccdc_resource,
645 .dev = { 645 .dev = {
646 .dma_mask = &vpfe_capture_dma_mask, 646 .dma_mask = &dm644x_video_dma_mask,
647 .coherent_dma_mask = DMA_BIT_MASK(32), 647 .coherent_dma_mask = DMA_BIT_MASK(32),
648 }, 648 },
649}; 649};
@@ -654,7 +654,134 @@ static struct platform_device dm644x_vpfe_dev = {
654 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources), 654 .num_resources = ARRAY_SIZE(dm644x_vpfe_resources),
655 .resource = dm644x_vpfe_resources, 655 .resource = dm644x_vpfe_resources,
656 .dev = { 656 .dev = {
657 .dma_mask = &vpfe_capture_dma_mask, 657 .dma_mask = &dm644x_video_dma_mask,
658 .coherent_dma_mask = DMA_BIT_MASK(32),
659 },
660};
661
662#define DM644X_OSD_BASE 0x01c72600
663
664static struct resource dm644x_osd_resources[] = {
665 {
666 .start = DM644X_OSD_BASE,
667 .end = DM644X_OSD_BASE + 0x1ff,
668 .flags = IORESOURCE_MEM,
669 },
670};
671
672static struct osd_platform_data dm644x_osd_data = {
673 .vpbe_type = VPBE_VERSION_1,
674};
675
676static struct platform_device dm644x_osd_dev = {
677 .name = VPBE_OSD_SUBDEV_NAME,
678 .id = -1,
679 .num_resources = ARRAY_SIZE(dm644x_osd_resources),
680 .resource = dm644x_osd_resources,
681 .dev = {
682 .dma_mask = &dm644x_video_dma_mask,
683 .coherent_dma_mask = DMA_BIT_MASK(32),
684 .platform_data = &dm644x_osd_data,
685 },
686};
687
688#define DM644X_VENC_BASE 0x01c72400
689
690static struct resource dm644x_venc_resources[] = {
691 {
692 .start = DM644X_VENC_BASE,
693 .end = DM644X_VENC_BASE + 0x17f,
694 .flags = IORESOURCE_MEM,
695 },
696};
697
698#define DM644X_VPSS_MUXSEL_PLL2_MODE BIT(0)
699#define DM644X_VPSS_MUXSEL_VPBECLK_MODE BIT(1)
700#define DM644X_VPSS_VENCLKEN BIT(3)
701#define DM644X_VPSS_DACCLKEN BIT(4)
702
703static int dm644x_venc_setup_clock(enum vpbe_enc_timings_type type,
704 unsigned int mode)
705{
706 int ret = 0;
707 u32 v = DM644X_VPSS_VENCLKEN;
708
709 switch (type) {
710 case VPBE_ENC_STD:
711 v |= DM644X_VPSS_DACCLKEN;
712 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
713 break;
714 case VPBE_ENC_DV_PRESET:
715 switch (mode) {
716 case V4L2_DV_480P59_94:
717 case V4L2_DV_576P50:
718 v |= DM644X_VPSS_MUXSEL_PLL2_MODE |
719 DM644X_VPSS_DACCLKEN;
720 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
721 break;
722 case V4L2_DV_720P60:
723 case V4L2_DV_1080I60:
724 case V4L2_DV_1080P30:
725 /*
726 * For HD, use external clock source since
727 * HD requires higher clock rate
728 */
729 v |= DM644X_VPSS_MUXSEL_VPBECLK_MODE;
730 writel(v, DAVINCI_SYSMOD_VIRT(SYSMOD_VPSS_CLKCTL));
731 break;
732 default:
733 ret = -EINVAL;
734 break;
735 }
736 break;
737 default:
738 ret = -EINVAL;
739 }
740
741 return ret;
742}
743
744static struct resource dm644x_v4l2_disp_resources[] = {
745 {
746 .start = IRQ_VENCINT,
747 .end = IRQ_VENCINT,
748 .flags = IORESOURCE_IRQ,
749 },
750};
751
752static struct platform_device dm644x_vpbe_display = {
753 .name = "vpbe-v4l2",
754 .id = -1,
755 .num_resources = ARRAY_SIZE(dm644x_v4l2_disp_resources),
756 .resource = dm644x_v4l2_disp_resources,
757 .dev = {
758 .dma_mask = &dm644x_video_dma_mask,
759 .coherent_dma_mask = DMA_BIT_MASK(32),
760 },
761};
762
763static struct venc_platform_data dm644x_venc_pdata = {
764 .venc_type = VPBE_VERSION_1,
765 .setup_clock = dm644x_venc_setup_clock,
766};
767
768static struct platform_device dm644x_venc_dev = {
769 .name = VPBE_VENC_SUBDEV_NAME,
770 .id = -1,
771 .num_resources = ARRAY_SIZE(dm644x_venc_resources),
772 .resource = dm644x_venc_resources,
773 .dev = {
774 .dma_mask = &dm644x_video_dma_mask,
775 .coherent_dma_mask = DMA_BIT_MASK(32),
776 .platform_data = &dm644x_venc_pdata,
777 },
778};
779
780static struct platform_device dm644x_vpbe_dev = {
781 .name = "vpbe_controller",
782 .id = -1,
783 .dev = {
784 .dma_mask = &dm644x_video_dma_mask,
658 .coherent_dma_mask = DMA_BIT_MASK(32), 785 .coherent_dma_mask = DMA_BIT_MASK(32),
659 }, 786 },
660}; 787};
@@ -786,17 +913,30 @@ void __init dm644x_init(void)
786 davinci_map_sysmod(); 913 davinci_map_sysmod();
787} 914}
788 915
789int __init dm644x_init_video(struct vpfe_config *vpfe_cfg) 916int __init dm644x_init_video(struct vpfe_config *vpfe_cfg,
917 struct vpbe_config *vpbe_cfg)
790{ 918{
791 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg; 919 if (vpfe_cfg || vpbe_cfg)
792 920 platform_device_register(&dm644x_vpss_device);
793 /* Add ccdc clock aliases */ 921
794 clk_add_alias("master", dm644x_ccdc_dev.name, "vpss_master", NULL); 922 if (vpfe_cfg) {
795 clk_add_alias("slave", dm644x_ccdc_dev.name, "vpss_slave", NULL); 923 dm644x_vpfe_dev.dev.platform_data = vpfe_cfg;
796 924 platform_device_register(&dm644x_ccdc_dev);
797 platform_device_register(&dm644x_vpss_device); 925 platform_device_register(&dm644x_vpfe_dev);
798 platform_device_register(&dm644x_ccdc_dev); 926 /* Add ccdc clock aliases */
799 platform_device_register(&dm644x_vpfe_dev); 927 clk_add_alias("master", dm644x_ccdc_dev.name,
928 "vpss_master", NULL);
929 clk_add_alias("slave", dm644x_ccdc_dev.name,
930 "vpss_slave", NULL);
931 }
932
933 if (vpbe_cfg) {
934 dm644x_vpbe_dev.dev.platform_data = vpbe_cfg;
935 platform_device_register(&dm644x_osd_dev);
936 platform_device_register(&dm644x_venc_dev);
937 platform_device_register(&dm644x_vpbe_dev);
938 platform_device_register(&dm644x_vpbe_display);
939 }
800 940
801 return 0; 941 return 0;
802} 942}
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index 97ca2592ce83..d67e21e526e6 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -160,21 +160,6 @@ static struct map_desc exynos4_iodesc[] __initdata = {
160 .length = SZ_4K, 160 .length = SZ_4K,
161 .type = MT_DEVICE, 161 .type = MT_DEVICE,
162 }, { 162 }, {
163 .virtual = (unsigned long)S5P_VA_GPIO1,
164 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO1),
165 .length = SZ_4K,
166 .type = MT_DEVICE,
167 }, {
168 .virtual = (unsigned long)S5P_VA_GPIO2,
169 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO2),
170 .length = SZ_4K,
171 .type = MT_DEVICE,
172 }, {
173 .virtual = (unsigned long)S5P_VA_GPIO3,
174 .pfn = __phys_to_pfn(EXYNOS4_PA_GPIO3),
175 .length = SZ_256,
176 .type = MT_DEVICE,
177 }, {
178 .virtual = (unsigned long)S5P_VA_DMC0, 163 .virtual = (unsigned long)S5P_VA_DMC0,
179 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0), 164 .pfn = __phys_to_pfn(EXYNOS4_PA_DMC0),
180 .length = SZ_64K, 165 .length = SZ_64K,
diff --git a/arch/arm/mach-exynos/include/mach/gpio.h b/arch/arm/mach-exynos/include/mach/gpio.h
index 80523ca9bb49..d7498afe036a 100644
--- a/arch/arm/mach-exynos/include/mach/gpio.h
+++ b/arch/arm/mach-exynos/include/mach/gpio.h
@@ -1,9 +1,8 @@
1/* linux/arch/arm/mach-exynos4/include/mach/gpio.h 1/*
2 * 2 * Copyright (c) 2010-2012 Samsung Electronics Co., Ltd.
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com 3 * http://www.samsung.com
5 * 4 *
6 * EXYNOS4 - GPIO lib support 5 * EXYNOS - GPIO lib support
7 * 6 *
8 * This program is free software; you can redistribute it and/or modify 7 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
@@ -13,9 +12,13 @@
13#ifndef __ASM_ARCH_GPIO_H 12#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__ 13#define __ASM_ARCH_GPIO_H __FILE__
15 14
16/* Practically, GPIO banks up to GPZ are the configurable gpio banks */ 15/* Macro for EXYNOS GPIO numbering */
16
17#define EXYNOS_GPIO_NEXT(__gpio) \
18 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
19
20/* EXYNOS4 GPIO bank sizes */
17 21
18/* GPIO bank sizes */
19#define EXYNOS4_GPIO_A0_NR (8) 22#define EXYNOS4_GPIO_A0_NR (8)
20#define EXYNOS4_GPIO_A1_NR (6) 23#define EXYNOS4_GPIO_A1_NR (6)
21#define EXYNOS4_GPIO_B_NR (8) 24#define EXYNOS4_GPIO_B_NR (8)
@@ -54,52 +57,50 @@
54#define EXYNOS4_GPIO_Y6_NR (8) 57#define EXYNOS4_GPIO_Y6_NR (8)
55#define EXYNOS4_GPIO_Z_NR (7) 58#define EXYNOS4_GPIO_Z_NR (7)
56 59
57/* GPIO bank numbers */ 60/* EXYNOS4 GPIO bank numbers */
58
59#define EXYNOS4_GPIO_NEXT(__gpio) \
60 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
61 61
62enum s5p_gpio_number { 62enum exynos4_gpio_number {
63 EXYNOS4_GPIO_A0_START = 0, 63 EXYNOS4_GPIO_A0_START = 0,
64 EXYNOS4_GPIO_A1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A0), 64 EXYNOS4_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A0),
65 EXYNOS4_GPIO_B_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_A1), 65 EXYNOS4_GPIO_B_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_A1),
66 EXYNOS4_GPIO_C0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_B), 66 EXYNOS4_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_B),
67 EXYNOS4_GPIO_C1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C0), 67 EXYNOS4_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C0),
68 EXYNOS4_GPIO_D0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_C1), 68 EXYNOS4_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_C1),
69 EXYNOS4_GPIO_D1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D0), 69 EXYNOS4_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D0),
70 EXYNOS4_GPIO_E0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_D1), 70 EXYNOS4_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_D1),
71 EXYNOS4_GPIO_E1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E0), 71 EXYNOS4_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E0),
72 EXYNOS4_GPIO_E2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E1), 72 EXYNOS4_GPIO_E2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E1),
73 EXYNOS4_GPIO_E3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E2), 73 EXYNOS4_GPIO_E3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E2),
74 EXYNOS4_GPIO_E4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E3), 74 EXYNOS4_GPIO_E4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E3),
75 EXYNOS4_GPIO_F0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_E4), 75 EXYNOS4_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_E4),
76 EXYNOS4_GPIO_F1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F0), 76 EXYNOS4_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F0),
77 EXYNOS4_GPIO_F2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F1), 77 EXYNOS4_GPIO_F2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F1),
78 EXYNOS4_GPIO_F3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F2), 78 EXYNOS4_GPIO_F3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F2),
79 EXYNOS4_GPIO_J0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_F3), 79 EXYNOS4_GPIO_J0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_F3),
80 EXYNOS4_GPIO_J1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J0), 80 EXYNOS4_GPIO_J1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J0),
81 EXYNOS4_GPIO_K0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_J1), 81 EXYNOS4_GPIO_K0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_J1),
82 EXYNOS4_GPIO_K1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K0), 82 EXYNOS4_GPIO_K1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K0),
83 EXYNOS4_GPIO_K2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K1), 83 EXYNOS4_GPIO_K2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K1),
84 EXYNOS4_GPIO_K3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K2), 84 EXYNOS4_GPIO_K3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K2),
85 EXYNOS4_GPIO_L0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_K3), 85 EXYNOS4_GPIO_L0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_K3),
86 EXYNOS4_GPIO_L1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L0), 86 EXYNOS4_GPIO_L1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L0),
87 EXYNOS4_GPIO_L2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L1), 87 EXYNOS4_GPIO_L2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L1),
88 EXYNOS4_GPIO_X0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_L2), 88 EXYNOS4_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_L2),
89 EXYNOS4_GPIO_X1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X0), 89 EXYNOS4_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X0),
90 EXYNOS4_GPIO_X2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X1), 90 EXYNOS4_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X1),
91 EXYNOS4_GPIO_X3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X2), 91 EXYNOS4_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X2),
92 EXYNOS4_GPIO_Y0_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_X3), 92 EXYNOS4_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_X3),
93 EXYNOS4_GPIO_Y1_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y0), 93 EXYNOS4_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y0),
94 EXYNOS4_GPIO_Y2_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y1), 94 EXYNOS4_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y1),
95 EXYNOS4_GPIO_Y3_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y2), 95 EXYNOS4_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y2),
96 EXYNOS4_GPIO_Y4_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y3), 96 EXYNOS4_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y3),
97 EXYNOS4_GPIO_Y5_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y4), 97 EXYNOS4_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y4),
98 EXYNOS4_GPIO_Y6_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y5), 98 EXYNOS4_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y5),
99 EXYNOS4_GPIO_Z_START = EXYNOS4_GPIO_NEXT(EXYNOS4_GPIO_Y6), 99 EXYNOS4_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS4_GPIO_Y6),
100}; 100};
101 101
102/* EXYNOS4 GPIO number definitions */ 102/* EXYNOS4 GPIO number definitions */
103
103#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr)) 104#define EXYNOS4_GPA0(_nr) (EXYNOS4_GPIO_A0_START + (_nr))
104#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr)) 105#define EXYNOS4_GPA1(_nr) (EXYNOS4_GPIO_A1_START + (_nr))
105#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr)) 106#define EXYNOS4_GPB(_nr) (EXYNOS4_GPIO_B_START + (_nr))
@@ -139,11 +140,147 @@ enum s5p_gpio_number {
139#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr)) 140#define EXYNOS4_GPZ(_nr) (EXYNOS4_GPIO_Z_START + (_nr))
140 141
141/* the end of the EXYNOS4 specific gpios */ 142/* the end of the EXYNOS4 specific gpios */
143
142#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1) 144#define EXYNOS4_GPIO_END (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + 1)
143#define S3C_GPIO_END EXYNOS4_GPIO_END
144 145
145/* define the number of gpios we need to the one after the GPZ() range */ 146/* EXYNOS5 GPIO bank sizes */
146#define ARCH_NR_GPIOS (EXYNOS4_GPZ(EXYNOS4_GPIO_Z_NR) + \ 147
147 CONFIG_SAMSUNG_GPIO_EXTRA + 1) 148#define EXYNOS5_GPIO_A0_NR (8)
149#define EXYNOS5_GPIO_A1_NR (6)
150#define EXYNOS5_GPIO_A2_NR (8)
151#define EXYNOS5_GPIO_B0_NR (5)
152#define EXYNOS5_GPIO_B1_NR (5)
153#define EXYNOS5_GPIO_B2_NR (4)
154#define EXYNOS5_GPIO_B3_NR (4)
155#define EXYNOS5_GPIO_C0_NR (7)
156#define EXYNOS5_GPIO_C1_NR (7)
157#define EXYNOS5_GPIO_C2_NR (7)
158#define EXYNOS5_GPIO_C3_NR (7)
159#define EXYNOS5_GPIO_D0_NR (8)
160#define EXYNOS5_GPIO_D1_NR (8)
161#define EXYNOS5_GPIO_Y0_NR (6)
162#define EXYNOS5_GPIO_Y1_NR (4)
163#define EXYNOS5_GPIO_Y2_NR (6)
164#define EXYNOS5_GPIO_Y3_NR (8)
165#define EXYNOS5_GPIO_Y4_NR (8)
166#define EXYNOS5_GPIO_Y5_NR (8)
167#define EXYNOS5_GPIO_Y6_NR (8)
168#define EXYNOS5_GPIO_X0_NR (8)
169#define EXYNOS5_GPIO_X1_NR (8)
170#define EXYNOS5_GPIO_X2_NR (8)
171#define EXYNOS5_GPIO_X3_NR (8)
172#define EXYNOS5_GPIO_E0_NR (8)
173#define EXYNOS5_GPIO_E1_NR (2)
174#define EXYNOS5_GPIO_F0_NR (4)
175#define EXYNOS5_GPIO_F1_NR (4)
176#define EXYNOS5_GPIO_G0_NR (8)
177#define EXYNOS5_GPIO_G1_NR (8)
178#define EXYNOS5_GPIO_G2_NR (2)
179#define EXYNOS5_GPIO_H0_NR (4)
180#define EXYNOS5_GPIO_H1_NR (8)
181#define EXYNOS5_GPIO_V0_NR (8)
182#define EXYNOS5_GPIO_V1_NR (8)
183#define EXYNOS5_GPIO_V2_NR (8)
184#define EXYNOS5_GPIO_V3_NR (8)
185#define EXYNOS5_GPIO_V4_NR (2)
186#define EXYNOS5_GPIO_Z_NR (7)
187
188/* EXYNOS5 GPIO bank numbers */
189
190enum exynos5_gpio_number {
191 EXYNOS5_GPIO_A0_START = 0,
192 EXYNOS5_GPIO_A1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A0),
193 EXYNOS5_GPIO_A2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A1),
194 EXYNOS5_GPIO_B0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_A2),
195 EXYNOS5_GPIO_B1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B0),
196 EXYNOS5_GPIO_B2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B1),
197 EXYNOS5_GPIO_B3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B2),
198 EXYNOS5_GPIO_C0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_B3),
199 EXYNOS5_GPIO_C1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C0),
200 EXYNOS5_GPIO_C2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C1),
201 EXYNOS5_GPIO_C3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C2),
202 EXYNOS5_GPIO_D0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_C3),
203 EXYNOS5_GPIO_D1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D0),
204 EXYNOS5_GPIO_Y0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_D1),
205 EXYNOS5_GPIO_Y1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y0),
206 EXYNOS5_GPIO_Y2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y1),
207 EXYNOS5_GPIO_Y3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y2),
208 EXYNOS5_GPIO_Y4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y3),
209 EXYNOS5_GPIO_Y5_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y4),
210 EXYNOS5_GPIO_Y6_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y5),
211 EXYNOS5_GPIO_X0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_Y6),
212 EXYNOS5_GPIO_X1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X0),
213 EXYNOS5_GPIO_X2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X1),
214 EXYNOS5_GPIO_X3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X2),
215 EXYNOS5_GPIO_E0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_X3),
216 EXYNOS5_GPIO_E1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E0),
217 EXYNOS5_GPIO_F0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_E1),
218 EXYNOS5_GPIO_F1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F0),
219 EXYNOS5_GPIO_G0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_F1),
220 EXYNOS5_GPIO_G1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G0),
221 EXYNOS5_GPIO_G2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G1),
222 EXYNOS5_GPIO_H0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_G2),
223 EXYNOS5_GPIO_H1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H0),
224 EXYNOS5_GPIO_V0_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_H1),
225 EXYNOS5_GPIO_V1_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V0),
226 EXYNOS5_GPIO_V2_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V1),
227 EXYNOS5_GPIO_V3_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V2),
228 EXYNOS5_GPIO_V4_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V3),
229 EXYNOS5_GPIO_Z_START = EXYNOS_GPIO_NEXT(EXYNOS5_GPIO_V4),
230};
231
232/* EXYNOS5 GPIO number definitions */
233
234#define EXYNOS5_GPA0(_nr) (EXYNOS5_GPIO_A0_START + (_nr))
235#define EXYNOS5_GPA1(_nr) (EXYNOS5_GPIO_A1_START + (_nr))
236#define EXYNOS5_GPA2(_nr) (EXYNOS5_GPIO_A2_START + (_nr))
237#define EXYNOS5_GPB0(_nr) (EXYNOS5_GPIO_B0_START + (_nr))
238#define EXYNOS5_GPB1(_nr) (EXYNOS5_GPIO_B1_START + (_nr))
239#define EXYNOS5_GPB2(_nr) (EXYNOS5_GPIO_B2_START + (_nr))
240#define EXYNOS5_GPB3(_nr) (EXYNOS5_GPIO_B3_START + (_nr))
241#define EXYNOS5_GPC0(_nr) (EXYNOS5_GPIO_C0_START + (_nr))
242#define EXYNOS5_GPC1(_nr) (EXYNOS5_GPIO_C1_START + (_nr))
243#define EXYNOS5_GPC2(_nr) (EXYNOS5_GPIO_C2_START + (_nr))
244#define EXYNOS5_GPC3(_nr) (EXYNOS5_GPIO_C3_START + (_nr))
245#define EXYNOS5_GPD0(_nr) (EXYNOS5_GPIO_D0_START + (_nr))
246#define EXYNOS5_GPD1(_nr) (EXYNOS5_GPIO_D1_START + (_nr))
247#define EXYNOS5_GPY0(_nr) (EXYNOS5_GPIO_Y0_START + (_nr))
248#define EXYNOS5_GPY1(_nr) (EXYNOS5_GPIO_Y1_START + (_nr))
249#define EXYNOS5_GPY2(_nr) (EXYNOS5_GPIO_Y2_START + (_nr))
250#define EXYNOS5_GPY3(_nr) (EXYNOS5_GPIO_Y3_START + (_nr))
251#define EXYNOS5_GPY4(_nr) (EXYNOS5_GPIO_Y4_START + (_nr))
252#define EXYNOS5_GPY5(_nr) (EXYNOS5_GPIO_Y5_START + (_nr))
253#define EXYNOS5_GPY6(_nr) (EXYNOS5_GPIO_Y6_START + (_nr))
254#define EXYNOS5_GPX0(_nr) (EXYNOS5_GPIO_X0_START + (_nr))
255#define EXYNOS5_GPX1(_nr) (EXYNOS5_GPIO_X1_START + (_nr))
256#define EXYNOS5_GPX2(_nr) (EXYNOS5_GPIO_X2_START + (_nr))
257#define EXYNOS5_GPX3(_nr) (EXYNOS5_GPIO_X3_START + (_nr))
258#define EXYNOS5_GPE0(_nr) (EXYNOS5_GPIO_E0_START + (_nr))
259#define EXYNOS5_GPE1(_nr) (EXYNOS5_GPIO_E1_START + (_nr))
260#define EXYNOS5_GPF0(_nr) (EXYNOS5_GPIO_F0_START + (_nr))
261#define EXYNOS5_GPF1(_nr) (EXYNOS5_GPIO_F1_START + (_nr))
262#define EXYNOS5_GPG0(_nr) (EXYNOS5_GPIO_G0_START + (_nr))
263#define EXYNOS5_GPG1(_nr) (EXYNOS5_GPIO_G1_START + (_nr))
264#define EXYNOS5_GPG2(_nr) (EXYNOS5_GPIO_G2_START + (_nr))
265#define EXYNOS5_GPH0(_nr) (EXYNOS5_GPIO_H0_START + (_nr))
266#define EXYNOS5_GPH1(_nr) (EXYNOS5_GPIO_H1_START + (_nr))
267#define EXYNOS5_GPV0(_nr) (EXYNOS5_GPIO_V0_START + (_nr))
268#define EXYNOS5_GPV1(_nr) (EXYNOS5_GPIO_V1_START + (_nr))
269#define EXYNOS5_GPV2(_nr) (EXYNOS5_GPIO_V2_START + (_nr))
270#define EXYNOS5_GPV3(_nr) (EXYNOS5_GPIO_V3_START + (_nr))
271#define EXYNOS5_GPV4(_nr) (EXYNOS5_GPIO_V4_START + (_nr))
272#define EXYNOS5_GPZ(_nr) (EXYNOS5_GPIO_Z_START + (_nr))
273
274/* the end of the EXYNOS5 specific gpios */
275
276#define EXYNOS5_GPIO_END (EXYNOS5_GPZ(EXYNOS5_GPIO_Z_NR) + 1)
277
278/* actually, EXYNOS5_GPIO_END is bigger than EXYNOS4 */
279
280#define S3C_GPIO_END (EXYNOS5_GPIO_END)
281
282/* define the number of gpios */
283
284#define ARCH_NR_GPIOS (CONFIG_SAMSUNG_GPIO_EXTRA + S3C_GPIO_END)
148 285
149#endif /* __ASM_ARCH_GPIO_H */ 286#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 609127df9b02..54307b09813a 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -101,6 +101,10 @@
101#define EXYNOS4_PA_GPIO1 0x11400000 101#define EXYNOS4_PA_GPIO1 0x11400000
102#define EXYNOS4_PA_GPIO2 0x11000000 102#define EXYNOS4_PA_GPIO2 0x11000000
103#define EXYNOS4_PA_GPIO3 0x03860000 103#define EXYNOS4_PA_GPIO3 0x03860000
104#define EXYNOS5_PA_GPIO1 0x11400000
105#define EXYNOS5_PA_GPIO2 0x13400000
106#define EXYNOS5_PA_GPIO3 0x10D10000
107#define EXYNOS5_PA_GPIO4 0x03860000
104 108
105#define EXYNOS4_PA_MIPI_CSIS0 0x11880000 109#define EXYNOS4_PA_MIPI_CSIS0 0x11880000
106#define EXYNOS4_PA_MIPI_CSIS1 0x11890000 110#define EXYNOS4_PA_MIPI_CSIS1 0x11890000
diff --git a/arch/arm/mach-exynos/pm_domains.c b/arch/arm/mach-exynos/pm_domains.c
index 0b04af2b13cc..13b306808b42 100644
--- a/arch/arm/mach-exynos/pm_domains.c
+++ b/arch/arm/mach-exynos/pm_domains.c
@@ -183,6 +183,12 @@ static __init int exynos4_pm_init_power_domain(void)
183#ifdef CONFIG_S5P_DEV_CSIS1 183#ifdef CONFIG_S5P_DEV_CSIS1
184 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam); 184 exynos_pm_add_dev_to_genpd(&s5p_device_mipi_csis1, &exynos4_pd_cam);
185#endif 185#endif
186#ifdef CONFIG_S5P_DEV_G2D
187 exynos_pm_add_dev_to_genpd(&s5p_device_g2d, &exynos4_pd_lcd0);
188#endif
189#ifdef CONFIG_S5P_DEV_JPEG
190 exynos_pm_add_dev_to_genpd(&s5p_device_jpeg, &exynos4_pd_cam);
191#endif
186 return 0; 192 return 0;
187} 193}
188arch_initcall(exynos4_pm_init_power_domain); 194arch_initcall(exynos4_pm_init_power_domain);
diff --git a/arch/arm/mach-lpc32xx/Kconfig b/arch/arm/mach-lpc32xx/Kconfig
index fde663508696..75946ac89ee9 100644
--- a/arch/arm/mach-lpc32xx/Kconfig
+++ b/arch/arm/mach-lpc32xx/Kconfig
@@ -29,5 +29,30 @@ config ARCH_LPC32XX_UART6_SELECT
29 29
30endmenu 30endmenu
31 31
32menu "LPC32XX chip components"
33
34config ARCH_LPC32XX_IRAM_FOR_NET
35 bool "Use IRAM for network buffers"
36 default y
37 help
38 Say Y here to use the LPC internal fast IRAM (i.e. 256KB SRAM) as
39 network buffer. If the total combined required buffer sizes is
40 larger than the size of IRAM, then SDRAM will be used instead.
41
42 This can be enabled safely if the IRAM is not intended for other
43 uses.
44
45config ARCH_LPC32XX_MII_SUPPORT
46 bool "Check to enable MII support or leave disabled for RMII support"
47 help
48 Say Y here to enable MII support, or N for RMII support. Regardless of
49 which support is selected, the ethernet interface driver needs to be
50 selected in the device driver networking section.
51
52 The PHY3250 reference board uses RMII, so users of this board should
53 say N.
54
55endmenu
56
32endif 57endif
33 58
diff --git a/arch/arm/mach-lpc32xx/clock.c b/arch/arm/mach-lpc32xx/clock.c
index f55c772d1816..b7ef51119d37 100644
--- a/arch/arm/mach-lpc32xx/clock.c
+++ b/arch/arm/mach-lpc32xx/clock.c
@@ -87,6 +87,7 @@
87#include <linux/list.h> 87#include <linux/list.h>
88#include <linux/errno.h> 88#include <linux/errno.h>
89#include <linux/device.h> 89#include <linux/device.h>
90#include <linux/delay.h>
90#include <linux/err.h> 91#include <linux/err.h>
91#include <linux/clk.h> 92#include <linux/clk.h>
92#include <linux/amba/bus.h> 93#include <linux/amba/bus.h>
@@ -100,6 +101,8 @@
100 101
101static DEFINE_SPINLOCK(global_clkregs_lock); 102static DEFINE_SPINLOCK(global_clkregs_lock);
102 103
104static int usb_pll_enable, usb_pll_valid;
105
103static struct clk clk_armpll; 106static struct clk clk_armpll;
104static struct clk clk_usbpll; 107static struct clk clk_usbpll;
105 108
@@ -384,30 +387,62 @@ static u32 local_clk_usbpll_setup(struct clk_pll_setup *pHCLKPllSetup)
384static int local_usbpll_enable(struct clk *clk, int enable) 387static int local_usbpll_enable(struct clk *clk, int enable)
385{ 388{
386 u32 reg; 389 u32 reg;
387 int ret = -ENODEV; 390 int ret = 0;
388 unsigned long timeout = jiffies + msecs_to_jiffies(10); 391 unsigned long timeout = jiffies + msecs_to_jiffies(20);
389 392
390 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); 393 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
391 394
392 if (enable == 0) { 395 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN2 |
393 reg &= ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 | 396 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
394 LPC32XX_CLKPWR_USBCTRL_CLK_EN2); 397 LPC32XX_CLKPWR_USB_CTRL);
395 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); 398 __raw_writel(reg & ~LPC32XX_CLKPWR_USBCTRL_CLK_EN1,
396 } else if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP) { 399 LPC32XX_CLKPWR_USB_CTRL);
400
401 if (enable && usb_pll_valid && usb_pll_enable) {
402 ret = -ENODEV;
403 /*
404 * If the PLL rate has been previously set, then the rate
405 * in the PLL register is valid and can be enabled here.
406 * Otherwise, it needs to be enabled as part of setrate.
407 */
408
409 /*
410 * Gate clock into PLL
411 */
397 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1; 412 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
398 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); 413 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
399 414
400 /* Wait for PLL lock */ 415 /*
416 * Enable PLL
417 */
418 reg |= LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP;
419 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
420
421 /*
422 * Wait for PLL to lock
423 */
401 while (time_before(jiffies, timeout) && (ret == -ENODEV)) { 424 while (time_before(jiffies, timeout) && (ret == -ENODEV)) {
402 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); 425 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
403 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS) 426 if (reg & LPC32XX_CLKPWR_USBCTRL_PLL_STS)
404 ret = 0; 427 ret = 0;
428 else
429 udelay(10);
405 } 430 }
406 431
432 /*
433 * Gate clock from PLL if PLL is locked
434 */
407 if (ret == 0) { 435 if (ret == 0) {
408 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; 436 __raw_writel(reg | LPC32XX_CLKPWR_USBCTRL_CLK_EN2,
409 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); 437 LPC32XX_CLKPWR_USB_CTRL);
438 } else {
439 __raw_writel(reg & ~(LPC32XX_CLKPWR_USBCTRL_CLK_EN1 |
440 LPC32XX_CLKPWR_USBCTRL_PLL_PWRUP),
441 LPC32XX_CLKPWR_USB_CTRL);
410 } 442 }
443 } else if ((enable == 0) && usb_pll_valid && usb_pll_enable) {
444 usb_pll_valid = 0;
445 usb_pll_enable = 0;
411 } 446 }
412 447
413 return ret; 448 return ret;
@@ -425,7 +460,7 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
425 */ 460 */
426 rate = rate * 1000; 461 rate = rate * 1000;
427 462
428 clkin = clk->parent->rate; 463 clkin = clk->get_rate(clk);
429 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & 464 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
430 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; 465 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
431 clkin = clkin / usbdiv; 466 clkin = clkin / usbdiv;
@@ -439,7 +474,8 @@ static unsigned long local_usbpll_round_rate(struct clk *clk,
439 474
440static int local_usbpll_set_rate(struct clk *clk, unsigned long rate) 475static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
441{ 476{
442 u32 clkin, reg, usbdiv; 477 int ret = -ENODEV;
478 u32 clkin, usbdiv;
443 struct clk_pll_setup pllsetup; 479 struct clk_pll_setup pllsetup;
444 480
445 /* 481 /*
@@ -448,7 +484,7 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
448 */ 484 */
449 rate = rate * 1000; 485 rate = rate * 1000;
450 486
451 clkin = clk->get_rate(clk); 487 clkin = clk->get_rate(clk->parent);
452 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) & 488 usbdiv = (__raw_readl(LPC32XX_CLKPWR_USBCLK_PDIV) &
453 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1; 489 LPC32XX_CLKPWR_USBPDIV_PLL_MASK) + 1;
454 clkin = clkin / usbdiv; 490 clkin = clkin / usbdiv;
@@ -457,22 +493,25 @@ static int local_usbpll_set_rate(struct clk *clk, unsigned long rate)
457 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0) 493 if (local_clk_find_pll_cfg(clkin, rate, &pllsetup) == 0)
458 return -EINVAL; 494 return -EINVAL;
459 495
496 /*
497 * Disable PLL clocks during PLL change
498 */
460 local_usbpll_enable(clk, 0); 499 local_usbpll_enable(clk, 0);
461 500 pllsetup.analog_on = 0;
462 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL);
463 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN1;
464 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL);
465
466 pllsetup.analog_on = 1;
467 local_clk_usbpll_setup(&pllsetup); 501 local_clk_usbpll_setup(&pllsetup);
468 502
469 clk->rate = clk_check_pll_setup(clkin, &pllsetup); 503 /*
504 * Start USB PLL and check PLL status
505 */
506
507 usb_pll_valid = 1;
508 usb_pll_enable = 1;
470 509
471 reg = __raw_readl(LPC32XX_CLKPWR_USB_CTRL); 510 ret = local_usbpll_enable(clk, 1);
472 reg |= LPC32XX_CLKPWR_USBCTRL_CLK_EN2; 511 if (ret >= 0)
473 __raw_writel(reg, LPC32XX_CLKPWR_USB_CTRL); 512 clk->rate = clk_check_pll_setup(clkin, &pllsetup);
474 513
475 return 0; 514 return ret;
476} 515}
477 516
478static struct clk clk_usbpll = { 517static struct clk clk_usbpll = {
diff --git a/arch/arm/mach-lpc32xx/common.c b/arch/arm/mach-lpc32xx/common.c
index 6c76bb36559b..bbbf063a74c2 100644
--- a/arch/arm/mach-lpc32xx/common.c
+++ b/arch/arm/mach-lpc32xx/common.c
@@ -160,6 +160,53 @@ struct platform_device lpc32xx_adc_device = {
160}; 160};
161 161
162/* 162/*
163 * USB support
164 */
165/* The dmamask must be set for OHCI to work */
166static u64 ohci_dmamask = ~(u32) 0;
167static struct resource ohci_resources[] = {
168 {
169 .start = IO_ADDRESS(LPC32XX_USB_BASE),
170 .end = IO_ADDRESS(LPC32XX_USB_BASE + 0x100 - 1),
171 .flags = IORESOURCE_MEM,
172 }, {
173 .start = IRQ_LPC32XX_USB_HOST,
174 .flags = IORESOURCE_IRQ,
175 },
176};
177struct platform_device lpc32xx_ohci_device = {
178 .name = "usb-ohci",
179 .id = -1,
180 .dev = {
181 .dma_mask = &ohci_dmamask,
182 .coherent_dma_mask = 0xFFFFFFFF,
183 },
184 .num_resources = ARRAY_SIZE(ohci_resources),
185 .resource = ohci_resources,
186};
187
188/*
189 * Network Support
190 */
191static struct resource net_resources[] = {
192 [0] = DEFINE_RES_MEM(LPC32XX_ETHERNET_BASE, SZ_4K),
193 [1] = DEFINE_RES_MEM(LPC32XX_IRAM_BASE, SZ_128K),
194 [2] = DEFINE_RES_IRQ(IRQ_LPC32XX_ETHERNET),
195};
196
197static u64 lpc32xx_mac_dma_mask = 0xffffffffUL;
198struct platform_device lpc32xx_net_device = {
199 .name = "lpc-eth",
200 .id = 0,
201 .dev = {
202 .dma_mask = &lpc32xx_mac_dma_mask,
203 .coherent_dma_mask = 0xffffffffUL,
204 },
205 .num_resources = ARRAY_SIZE(net_resources),
206 .resource = net_resources,
207};
208
209/*
163 * Returns the unique ID for the device 210 * Returns the unique ID for the device
164 */ 211 */
165void lpc32xx_get_uid(u32 devid[4]) 212void lpc32xx_get_uid(u32 devid[4])
diff --git a/arch/arm/mach-lpc32xx/common.h b/arch/arm/mach-lpc32xx/common.h
index 68f2e46d98ad..68e45e8c9486 100644
--- a/arch/arm/mach-lpc32xx/common.h
+++ b/arch/arm/mach-lpc32xx/common.h
@@ -19,6 +19,7 @@
19#ifndef __LPC32XX_COMMON_H 19#ifndef __LPC32XX_COMMON_H
20#define __LPC32XX_COMMON_H 20#define __LPC32XX_COMMON_H
21 21
22#include <mach/board.h>
22#include <linux/platform_device.h> 23#include <linux/platform_device.h>
23 24
24/* 25/*
@@ -31,6 +32,8 @@ extern struct platform_device lpc32xx_i2c2_device;
31extern struct platform_device lpc32xx_tsc_device; 32extern struct platform_device lpc32xx_tsc_device;
32extern struct platform_device lpc32xx_adc_device; 33extern struct platform_device lpc32xx_adc_device;
33extern struct platform_device lpc32xx_rtc_device; 34extern struct platform_device lpc32xx_rtc_device;
35extern struct platform_device lpc32xx_ohci_device;
36extern struct platform_device lpc32xx_net_device;
34 37
35/* 38/*
36 * Other arch specific structures and functions 39 * Other arch specific structures and functions
@@ -67,7 +70,6 @@ extern u32 clk_get_pclk_div(void);
67extern void lpc32xx_get_uid(u32 devid[4]); 70extern void lpc32xx_get_uid(u32 devid[4]);
68 71
69extern u32 lpc32xx_return_iram_size(void); 72extern u32 lpc32xx_return_iram_size(void);
70
71/* 73/*
72 * Pointers used for sizing and copying suspend function data 74 * Pointers used for sizing and copying suspend function data
73 */ 75 */
diff --git a/arch/arm/mach-lpc32xx/include/mach/board.h b/arch/arm/mach-lpc32xx/include/mach/board.h
new file mode 100644
index 000000000000..52531ca7bd1d
--- /dev/null
+++ b/arch/arm/mach-lpc32xx/include/mach/board.h
@@ -0,0 +1,24 @@
1/*
2 * arm/arch/mach-lpc32xx/include/mach/board.h
3 *
4 * Author: Kevin Wells <kevin.wells@nxp.com>
5 *
6 * Copyright (C) 2010 NXP Semiconductors
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#ifndef __ASM_ARCH_BOARD_H
20#define __ASM_ARCH_BOARD_H
21
22extern u32 lpc32xx_return_iram_size(void);
23
24#endif /* __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index c74de01ab5b6..d080cb1123dd 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -150,6 +150,10 @@ static const struct lpc32xx_event_info lpc32xx_events[NR_IRQS] = {
150 .event_group = &lpc32xx_event_int_regs, 150 .event_group = &lpc32xx_event_int_regs,
151 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT, 151 .mask = LPC32XX_CLKPWR_INTSRC_KEY_BIT,
152 }, 152 },
153 [IRQ_LPC32XX_ETHERNET] = {
154 .event_group = &lpc32xx_event_int_regs,
155 .mask = LPC32XX_CLKPWR_INTSRC_MAC_BIT,
156 },
153 [IRQ_LPC32XX_USB_OTG_ATX] = { 157 [IRQ_LPC32XX_USB_OTG_ATX] = {
154 .event_group = &lpc32xx_event_int_regs, 158 .event_group = &lpc32xx_event_int_regs,
155 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT, 159 .mask = LPC32XX_CLKPWR_INTSRC_USBATXINT_BIT,
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index 0d79a3f8a5e0..7f7401ec7487 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,7 @@
37 37
38#include <mach/hardware.h> 38#include <mach/hardware.h>
39#include <mach/platform.h> 39#include <mach/platform.h>
40#include <mach/board.h>
40#include <mach/gpio-lpc32xx.h> 41#include <mach/gpio-lpc32xx.h>
41#include "common.h" 42#include "common.h"
42 43
@@ -255,6 +256,8 @@ static struct platform_device *phy3250_devs[] __initdata = {
255 &lpc32xx_watchdog_device, 256 &lpc32xx_watchdog_device,
256 &lpc32xx_gpio_led_device, 257 &lpc32xx_gpio_led_device,
257 &lpc32xx_adc_device, 258 &lpc32xx_adc_device,
259 &lpc32xx_ohci_device,
260 &lpc32xx_net_device,
258}; 261};
259 262
260static struct amba_device *amba_devs[] __initdata = { 263static struct amba_device *amba_devs[] __initdata = {
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 0a79a1167a25..46277877b7ec 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -169,7 +169,7 @@ int s3c24xx_gpio_setpull_1down(struct samsung_gpio_chip *chip,
169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN); 169 return s3c24xx_gpio_setpull_1(chip, off, pull, S3C_GPIO_PULL_DOWN);
170} 170}
171 171
172static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip, 172static int exynos_gpio_setpull(struct samsung_gpio_chip *chip,
173 unsigned int off, samsung_gpio_pull_t pull) 173 unsigned int off, samsung_gpio_pull_t pull)
174{ 174{
175 if (pull == S3C_GPIO_PULL_UP) 175 if (pull == S3C_GPIO_PULL_UP)
@@ -178,7 +178,7 @@ static int exynos4_gpio_setpull(struct samsung_gpio_chip *chip,
178 return samsung_gpio_setpull_updown(chip, off, pull); 178 return samsung_gpio_setpull_updown(chip, off, pull);
179} 179}
180 180
181static samsung_gpio_pull_t exynos4_gpio_getpull(struct samsung_gpio_chip *chip, 181static samsung_gpio_pull_t exynos_gpio_getpull(struct samsung_gpio_chip *chip,
182 unsigned int off) 182 unsigned int off)
183{ 183{
184 samsung_gpio_pull_t pull; 184 samsung_gpio_pull_t pull;
@@ -452,9 +452,9 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
452}; 452};
453#endif 453#endif
454 454
455static struct samsung_gpio_cfg exynos4_gpio_cfg = { 455static struct samsung_gpio_cfg exynos_gpio_cfg = {
456 .set_pull = exynos4_gpio_setpull, 456 .set_pull = exynos_gpio_setpull,
457 .get_pull = exynos4_gpio_getpull, 457 .get_pull = exynos_gpio_getpull,
458 .set_config = samsung_gpio_setcfg_4bit, 458 .set_config = samsung_gpio_setcfg_4bit,
459 .get_config = samsung_gpio_getcfg_4bit, 459 .get_config = samsung_gpio_getcfg_4bit,
460}; 460};
@@ -502,13 +502,13 @@ static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
502 .get_config = samsung_gpio_getcfg_2bit, 502 .get_config = samsung_gpio_getcfg_2bit,
503 }, 503 },
504 [8] = { 504 [8] = {
505 .set_pull = exynos4_gpio_setpull, 505 .set_pull = exynos_gpio_setpull,
506 .get_pull = exynos4_gpio_getpull, 506 .get_pull = exynos_gpio_getpull,
507 }, 507 },
508 [9] = { 508 [9] = {
509 .cfg_eint = 0x3, 509 .cfg_eint = 0x3,
510 .set_pull = exynos4_gpio_setpull, 510 .set_pull = exynos_gpio_setpull,
511 .get_pull = exynos4_gpio_getpull, 511 .get_pull = exynos_gpio_getpull,
512 } 512 }
513}; 513};
514 514
@@ -2113,10 +2113,10 @@ static struct samsung_gpio_chip s5pv210_gpios_4bit[] = {
2113}; 2113};
2114 2114
2115/* 2115/*
2116 * Followings are the gpio banks in EXYNOS4210 2116 * Followings are the gpio banks in EXYNOS SoCs
2117 * 2117 *
2118 * The 'config' member when left to NULL, is initialized to the default 2118 * The 'config' member when left to NULL, is initialized to the default
2119 * structure samsung_gpio_cfgs[3] in the init function below. 2119 * structure exynos_gpio_cfg in the init function below.
2120 * 2120 *
2121 * The 'base' member is also initialized in the init function below. 2121 * The 'base' member is also initialized in the init function below.
2122 * Note: The initialization of 'base' member of samsung_gpio_chip structure 2122 * Note: The initialization of 'base' member of samsung_gpio_chip structure
@@ -2331,7 +2331,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2331 .label = "GPY6", 2331 .label = "GPY6",
2332 }, 2332 },
2333 }, { 2333 }, {
2334 .base = (S5P_VA_GPIO2 + 0xC00),
2335 .config = &samsung_gpio_cfgs[9], 2334 .config = &samsung_gpio_cfgs[9],
2336 .irq_base = IRQ_EINT(0), 2335 .irq_base = IRQ_EINT(0),
2337 .chip = { 2336 .chip = {
@@ -2341,7 +2340,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2341 .to_irq = samsung_gpiolib_to_irq, 2340 .to_irq = samsung_gpiolib_to_irq,
2342 }, 2341 },
2343 }, { 2342 }, {
2344 .base = (S5P_VA_GPIO2 + 0xC20),
2345 .config = &samsung_gpio_cfgs[9], 2343 .config = &samsung_gpio_cfgs[9],
2346 .irq_base = IRQ_EINT(8), 2344 .irq_base = IRQ_EINT(8),
2347 .chip = { 2345 .chip = {
@@ -2351,7 +2349,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2351 .to_irq = samsung_gpiolib_to_irq, 2349 .to_irq = samsung_gpiolib_to_irq,
2352 }, 2350 },
2353 }, { 2351 }, {
2354 .base = (S5P_VA_GPIO2 + 0xC40),
2355 .config = &samsung_gpio_cfgs[9], 2352 .config = &samsung_gpio_cfgs[9],
2356 .irq_base = IRQ_EINT(16), 2353 .irq_base = IRQ_EINT(16),
2357 .chip = { 2354 .chip = {
@@ -2361,7 +2358,6 @@ static struct samsung_gpio_chip exynos4_gpios_2[] = {
2361 .to_irq = samsung_gpiolib_to_irq, 2358 .to_irq = samsung_gpiolib_to_irq,
2362 }, 2359 },
2363 }, { 2360 }, {
2364 .base = (S5P_VA_GPIO2 + 0xC60),
2365 .config = &samsung_gpio_cfgs[9], 2361 .config = &samsung_gpio_cfgs[9],
2366 .irq_base = IRQ_EINT(24), 2362 .irq_base = IRQ_EINT(24),
2367 .chip = { 2363 .chip = {
@@ -2386,8 +2382,280 @@ static struct samsung_gpio_chip exynos4_gpios_3[] = {
2386#endif 2382#endif
2387}; 2383};
2388 2384
2389#if defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF) 2385static struct samsung_gpio_chip exynos5_gpios_1[] = {
2390static int exynos4_gpio_xlate(struct gpio_chip *gc, 2386#ifdef CONFIG_ARCH_EXYNOS5
2387 {
2388 .chip = {
2389 .base = EXYNOS5_GPA0(0),
2390 .ngpio = EXYNOS5_GPIO_A0_NR,
2391 .label = "GPA0",
2392 },
2393 }, {
2394 .chip = {
2395 .base = EXYNOS5_GPA1(0),
2396 .ngpio = EXYNOS5_GPIO_A1_NR,
2397 .label = "GPA1",
2398 },
2399 }, {
2400 .chip = {
2401 .base = EXYNOS5_GPA2(0),
2402 .ngpio = EXYNOS5_GPIO_A2_NR,
2403 .label = "GPA2",
2404 },
2405 }, {
2406 .chip = {
2407 .base = EXYNOS5_GPB0(0),
2408 .ngpio = EXYNOS5_GPIO_B0_NR,
2409 .label = "GPB0",
2410 },
2411 }, {
2412 .chip = {
2413 .base = EXYNOS5_GPB1(0),
2414 .ngpio = EXYNOS5_GPIO_B1_NR,
2415 .label = "GPB1",
2416 },
2417 }, {
2418 .chip = {
2419 .base = EXYNOS5_GPB2(0),
2420 .ngpio = EXYNOS5_GPIO_B2_NR,
2421 .label = "GPB2",
2422 },
2423 }, {
2424 .chip = {
2425 .base = EXYNOS5_GPB3(0),
2426 .ngpio = EXYNOS5_GPIO_B3_NR,
2427 .label = "GPB3",
2428 },
2429 }, {
2430 .chip = {
2431 .base = EXYNOS5_GPC0(0),
2432 .ngpio = EXYNOS5_GPIO_C0_NR,
2433 .label = "GPC0",
2434 },
2435 }, {
2436 .chip = {
2437 .base = EXYNOS5_GPC1(0),
2438 .ngpio = EXYNOS5_GPIO_C1_NR,
2439 .label = "GPC1",
2440 },
2441 }, {
2442 .chip = {
2443 .base = EXYNOS5_GPC2(0),
2444 .ngpio = EXYNOS5_GPIO_C2_NR,
2445 .label = "GPC2",
2446 },
2447 }, {
2448 .chip = {
2449 .base = EXYNOS5_GPC3(0),
2450 .ngpio = EXYNOS5_GPIO_C3_NR,
2451 .label = "GPC3",
2452 },
2453 }, {
2454 .chip = {
2455 .base = EXYNOS5_GPD0(0),
2456 .ngpio = EXYNOS5_GPIO_D0_NR,
2457 .label = "GPD0",
2458 },
2459 }, {
2460 .chip = {
2461 .base = EXYNOS5_GPD1(0),
2462 .ngpio = EXYNOS5_GPIO_D1_NR,
2463 .label = "GPD1",
2464 },
2465 }, {
2466 .chip = {
2467 .base = EXYNOS5_GPY0(0),
2468 .ngpio = EXYNOS5_GPIO_Y0_NR,
2469 .label = "GPY0",
2470 },
2471 }, {
2472 .chip = {
2473 .base = EXYNOS5_GPY1(0),
2474 .ngpio = EXYNOS5_GPIO_Y1_NR,
2475 .label = "GPY1",
2476 },
2477 }, {
2478 .chip = {
2479 .base = EXYNOS5_GPY2(0),
2480 .ngpio = EXYNOS5_GPIO_Y2_NR,
2481 .label = "GPY2",
2482 },
2483 }, {
2484 .chip = {
2485 .base = EXYNOS5_GPY3(0),
2486 .ngpio = EXYNOS5_GPIO_Y3_NR,
2487 .label = "GPY3",
2488 },
2489 }, {
2490 .chip = {
2491 .base = EXYNOS5_GPY4(0),
2492 .ngpio = EXYNOS5_GPIO_Y4_NR,
2493 .label = "GPY4",
2494 },
2495 }, {
2496 .chip = {
2497 .base = EXYNOS5_GPY5(0),
2498 .ngpio = EXYNOS5_GPIO_Y5_NR,
2499 .label = "GPY5",
2500 },
2501 }, {
2502 .chip = {
2503 .base = EXYNOS5_GPY6(0),
2504 .ngpio = EXYNOS5_GPIO_Y6_NR,
2505 .label = "GPY6",
2506 },
2507 }, {
2508 .config = &samsung_gpio_cfgs[9],
2509 .irq_base = IRQ_EINT(0),
2510 .chip = {
2511 .base = EXYNOS5_GPX0(0),
2512 .ngpio = EXYNOS5_GPIO_X0_NR,
2513 .label = "GPX0",
2514 .to_irq = samsung_gpiolib_to_irq,
2515 },
2516 }, {
2517 .config = &samsung_gpio_cfgs[9],
2518 .irq_base = IRQ_EINT(8),
2519 .chip = {
2520 .base = EXYNOS5_GPX1(0),
2521 .ngpio = EXYNOS5_GPIO_X1_NR,
2522 .label = "GPX1",
2523 .to_irq = samsung_gpiolib_to_irq,
2524 },
2525 }, {
2526 .config = &samsung_gpio_cfgs[9],
2527 .irq_base = IRQ_EINT(16),
2528 .chip = {
2529 .base = EXYNOS5_GPX2(0),
2530 .ngpio = EXYNOS5_GPIO_X2_NR,
2531 .label = "GPX2",
2532 .to_irq = samsung_gpiolib_to_irq,
2533 },
2534 }, {
2535 .config = &samsung_gpio_cfgs[9],
2536 .irq_base = IRQ_EINT(24),
2537 .chip = {
2538 .base = EXYNOS5_GPX3(0),
2539 .ngpio = EXYNOS5_GPIO_X3_NR,
2540 .label = "GPX3",
2541 .to_irq = samsung_gpiolib_to_irq,
2542 },
2543 },
2544#endif
2545};
2546
2547static struct samsung_gpio_chip exynos5_gpios_2[] = {
2548#ifdef CONFIG_ARCH_EXYNOS5
2549 {
2550 .chip = {
2551 .base = EXYNOS5_GPE0(0),
2552 .ngpio = EXYNOS5_GPIO_E0_NR,
2553 .label = "GPE0",
2554 },
2555 }, {
2556 .chip = {
2557 .base = EXYNOS5_GPE1(0),
2558 .ngpio = EXYNOS5_GPIO_E1_NR,
2559 .label = "GPE1",
2560 },
2561 }, {
2562 .chip = {
2563 .base = EXYNOS5_GPF0(0),
2564 .ngpio = EXYNOS5_GPIO_F0_NR,
2565 .label = "GPF0",
2566 },
2567 }, {
2568 .chip = {
2569 .base = EXYNOS5_GPF1(0),
2570 .ngpio = EXYNOS5_GPIO_F1_NR,
2571 .label = "GPF1",
2572 },
2573 }, {
2574 .chip = {
2575 .base = EXYNOS5_GPG0(0),
2576 .ngpio = EXYNOS5_GPIO_G0_NR,
2577 .label = "GPG0",
2578 },
2579 }, {
2580 .chip = {
2581 .base = EXYNOS5_GPG1(0),
2582 .ngpio = EXYNOS5_GPIO_G1_NR,
2583 .label = "GPG1",
2584 },
2585 }, {
2586 .chip = {
2587 .base = EXYNOS5_GPG2(0),
2588 .ngpio = EXYNOS5_GPIO_G2_NR,
2589 .label = "GPG2",
2590 },
2591 }, {
2592 .chip = {
2593 .base = EXYNOS5_GPH0(0),
2594 .ngpio = EXYNOS5_GPIO_H0_NR,
2595 .label = "GPH0",
2596 },
2597 }, {
2598 .chip = {
2599 .base = EXYNOS5_GPH1(0),
2600 .ngpio = EXYNOS5_GPIO_H1_NR,
2601 .label = "GPH1",
2602
2603 },
2604 },
2605#endif
2606};
2607
2608static struct samsung_gpio_chip exynos5_gpios_3[] = {
2609#ifdef CONFIG_ARCH_EXYNOS5
2610 {
2611 .chip = {
2612 .base = EXYNOS5_GPV0(0),
2613 .ngpio = EXYNOS5_GPIO_V0_NR,
2614 .label = "GPV0",
2615 },
2616 }, {
2617 .chip = {
2618 .base = EXYNOS5_GPV1(0),
2619 .ngpio = EXYNOS5_GPIO_V1_NR,
2620 .label = "GPV1",
2621 },
2622 }, {
2623 .chip = {
2624 .base = EXYNOS5_GPV2(0),
2625 .ngpio = EXYNOS5_GPIO_V2_NR,
2626 .label = "GPV2",
2627 },
2628 }, {
2629 .chip = {
2630 .base = EXYNOS5_GPV3(0),
2631 .ngpio = EXYNOS5_GPIO_V3_NR,
2632 .label = "GPV3",
2633 },
2634 }, {
2635 .chip = {
2636 .base = EXYNOS5_GPV4(0),
2637 .ngpio = EXYNOS5_GPIO_V4_NR,
2638 .label = "GPV4",
2639 },
2640 },
2641#endif
2642};
2643
2644static struct samsung_gpio_chip exynos5_gpios_4[] = {
2645#ifdef CONFIG_ARCH_EXYNOS5
2646 {
2647 .chip = {
2648 .base = EXYNOS5_GPZ(0),
2649 .ngpio = EXYNOS5_GPIO_Z_NR,
2650 .label = "GPZ",
2651 },
2652 },
2653#endif
2654};
2655
2656
2657#if defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF)
2658static int exynos_gpio_xlate(struct gpio_chip *gc,
2391 const struct of_phandle_args *gpiospec, u32 *flags) 2659 const struct of_phandle_args *gpiospec, u32 *flags)
2392{ 2660{
2393 unsigned int pin; 2661 unsigned int pin;
@@ -2413,13 +2681,13 @@ static int exynos4_gpio_xlate(struct gpio_chip *gc,
2413 return gpiospec->args[0]; 2681 return gpiospec->args[0];
2414} 2682}
2415 2683
2416static const struct of_device_id exynos4_gpio_dt_match[] __initdata = { 2684static const struct of_device_id exynos_gpio_dt_match[] __initdata = {
2417 { .compatible = "samsung,exynos4-gpio", }, 2685 { .compatible = "samsung,exynos4-gpio", },
2418 {} 2686 {}
2419}; 2687};
2420 2688
2421static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, 2689static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2422 u64 base, u64 offset) 2690 u64 base, u64 offset)
2423{ 2691{
2424 struct gpio_chip *gc = &chip->chip; 2692 struct gpio_chip *gc = &chip->chip;
2425 u64 address; 2693 u64 address;
@@ -2429,28 +2697,29 @@ static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2429 2697
2430 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset; 2698 address = chip->base ? base + ((u32)chip->base & 0xfff) : base + offset;
2431 gc->of_node = of_find_matching_node_by_address(NULL, 2699 gc->of_node = of_find_matching_node_by_address(NULL,
2432 exynos4_gpio_dt_match, address); 2700 exynos_gpio_dt_match, address);
2433 if (!gc->of_node) { 2701 if (!gc->of_node) {
2434 pr_info("gpio: device tree node not found for gpio controller" 2702 pr_info("gpio: device tree node not found for gpio controller"
2435 " with base address %08llx\n", address); 2703 " with base address %08llx\n", address);
2436 return; 2704 return;
2437 } 2705 }
2438 gc->of_gpio_n_cells = 4; 2706 gc->of_gpio_n_cells = 4;
2439 gc->of_xlate = exynos4_gpio_xlate; 2707 gc->of_xlate = exynos_gpio_xlate;
2440} 2708}
2441#elif defined(CONFIG_ARCH_EXYNOS4) 2709#elif defined(CONFIG_ARCH_EXYNOS)
2442static __init void exynos4_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip, 2710static __init void exynos_gpiolib_attach_ofnode(struct samsung_gpio_chip *chip,
2443 u64 base, u64 offset) 2711 u64 base, u64 offset)
2444{ 2712{
2445 return; 2713 return;
2446} 2714}
2447#endif /* defined(CONFIG_ARCH_EXYNOS4) && defined(CONFIG_OF) */ 2715#endif /* defined(CONFIG_ARCH_EXYNOS) && defined(CONFIG_OF) */
2448 2716
2449/* TODO: cleanup soc_is_* */ 2717/* TODO: cleanup soc_is_* */
2450static __init int samsung_gpiolib_init(void) 2718static __init int samsung_gpiolib_init(void)
2451{ 2719{
2452 struct samsung_gpio_chip *chip; 2720 struct samsung_gpio_chip *chip;
2453 int i, nr_chips; 2721 int i, nr_chips;
2722 void __iomem *gpio_base1, *gpio_base2, *gpio_base3, *gpio_base4;
2454 int group = 0; 2723 int group = 0;
2455 2724
2456 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs)); 2725 samsung_gpiolib_set_cfg(samsung_gpio_cfgs, ARRAY_SIZE(samsung_gpio_cfgs));
@@ -2516,66 +2785,200 @@ static __init int samsung_gpiolib_init(void)
2516 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR); 2785 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2517#endif 2786#endif
2518 } else if (soc_is_exynos4210()) { 2787 } else if (soc_is_exynos4210()) {
2519 group = 0; 2788#ifdef CONFIG_CPU_EXYNOS4210
2789 void __iomem *gpx_base;
2520 2790
2521 /* gpio part1 */ 2791 /* gpio part1 */
2792 gpio_base1 = ioremap(EXYNOS4_PA_GPIO1, SZ_4K);
2793 if (gpio_base1 == NULL) {
2794 pr_err("unable to ioremap for gpio_base1\n");
2795 goto err_ioremap1;
2796 }
2797
2522 chip = exynos4_gpios_1; 2798 chip = exynos4_gpios_1;
2523 nr_chips = ARRAY_SIZE(exynos4_gpios_1); 2799 nr_chips = ARRAY_SIZE(exynos4_gpios_1);
2524 2800
2525 for (i = 0; i < nr_chips; i++, chip++) { 2801 for (i = 0; i < nr_chips; i++, chip++) {
2526 if (!chip->config) { 2802 if (!chip->config) {
2527 chip->config = &exynos4_gpio_cfg; 2803 chip->config = &exynos_gpio_cfg;
2528 chip->group = group++; 2804 chip->group = group++;
2529 } 2805 }
2530#ifdef CONFIG_CPU_EXYNOS4210 2806 exynos_gpiolib_attach_ofnode(chip,
2531 exynos4_gpiolib_attach_ofnode(chip,
2532 EXYNOS4_PA_GPIO1, i * 0x20); 2807 EXYNOS4_PA_GPIO1, i * 0x20);
2533#endif
2534 } 2808 }
2535 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1, nr_chips, S5P_VA_GPIO1); 2809 samsung_gpiolib_add_4bit_chips(exynos4_gpios_1,
2810 nr_chips, gpio_base1);
2536 2811
2537 /* gpio part2 */ 2812 /* gpio part2 */
2813 gpio_base2 = ioremap(EXYNOS4_PA_GPIO2, SZ_4K);
2814 if (gpio_base2 == NULL) {
2815 pr_err("unable to ioremap for gpio_base2\n");
2816 goto err_ioremap2;
2817 }
2818
2819 /* need to set base address for gpx */
2820 chip = &exynos4_gpios_2[16];
2821 gpx_base = gpio_base2 + 0xC00;
2822 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2823 chip->base = gpx_base;
2824
2538 chip = exynos4_gpios_2; 2825 chip = exynos4_gpios_2;
2539 nr_chips = ARRAY_SIZE(exynos4_gpios_2); 2826 nr_chips = ARRAY_SIZE(exynos4_gpios_2);
2540 2827
2541 for (i = 0; i < nr_chips; i++, chip++) { 2828 for (i = 0; i < nr_chips; i++, chip++) {
2542 if (!chip->config) { 2829 if (!chip->config) {
2543 chip->config = &exynos4_gpio_cfg; 2830 chip->config = &exynos_gpio_cfg;
2544 chip->group = group++; 2831 chip->group = group++;
2545 } 2832 }
2546#ifdef CONFIG_CPU_EXYNOS4210 2833 exynos_gpiolib_attach_ofnode(chip,
2547 exynos4_gpiolib_attach_ofnode(chip,
2548 EXYNOS4_PA_GPIO2, i * 0x20); 2834 EXYNOS4_PA_GPIO2, i * 0x20);
2549#endif
2550 } 2835 }
2551 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2, nr_chips, S5P_VA_GPIO2); 2836 samsung_gpiolib_add_4bit_chips(exynos4_gpios_2,
2837 nr_chips, gpio_base2);
2552 2838
2553 /* gpio part3 */ 2839 /* gpio part3 */
2840 gpio_base3 = ioremap(EXYNOS4_PA_GPIO3, SZ_256);
2841 if (gpio_base3 == NULL) {
2842 pr_err("unable to ioremap for gpio_base3\n");
2843 goto err_ioremap3;
2844 }
2845
2554 chip = exynos4_gpios_3; 2846 chip = exynos4_gpios_3;
2555 nr_chips = ARRAY_SIZE(exynos4_gpios_3); 2847 nr_chips = ARRAY_SIZE(exynos4_gpios_3);
2556 2848
2557 for (i = 0; i < nr_chips; i++, chip++) { 2849 for (i = 0; i < nr_chips; i++, chip++) {
2558 if (!chip->config) { 2850 if (!chip->config) {
2559 chip->config = &exynos4_gpio_cfg; 2851 chip->config = &exynos_gpio_cfg;
2560 chip->group = group++; 2852 chip->group = group++;
2561 } 2853 }
2562#ifdef CONFIG_CPU_EXYNOS4210 2854 exynos_gpiolib_attach_ofnode(chip,
2563 exynos4_gpiolib_attach_ofnode(chip,
2564 EXYNOS4_PA_GPIO3, i * 0x20); 2855 EXYNOS4_PA_GPIO3, i * 0x20);
2565#endif
2566 } 2856 }
2567 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3, nr_chips, S5P_VA_GPIO3); 2857 samsung_gpiolib_add_4bit_chips(exynos4_gpios_3,
2858 nr_chips, gpio_base3);
2568 2859
2569#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT) 2860#if defined(CONFIG_CPU_EXYNOS4210) && defined(CONFIG_S5P_GPIO_INT)
2570 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS); 2861 s5p_register_gpioint_bank(IRQ_GPIO_XA, 0, IRQ_GPIO1_NR_GROUPS);
2571 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS); 2862 s5p_register_gpioint_bank(IRQ_GPIO_XB, IRQ_GPIO1_NR_GROUPS, IRQ_GPIO2_NR_GROUPS);
2572#endif 2863#endif
2864
2865#endif /* CONFIG_CPU_EXYNOS4210 */
2866 } else if (soc_is_exynos5250()) {
2867#ifdef CONFIG_SOC_EXYNOS5250
2868 void __iomem *gpx_base;
2869
2870 /* gpio part1 */
2871 gpio_base1 = ioremap(EXYNOS5_PA_GPIO1, SZ_4K);
2872 if (gpio_base1 == NULL) {
2873 pr_err("unable to ioremap for gpio_base1\n");
2874 goto err_ioremap1;
2875 }
2876
2877 /* need to set base address for gpx */
2878 chip = &exynos5_gpios_1[20];
2879 gpx_base = gpio_base1 + 0xC00;
2880 for (i = 0; i < 4; i++, chip++, gpx_base += 0x20)
2881 chip->base = gpx_base;
2882
2883 chip = exynos5_gpios_1;
2884 nr_chips = ARRAY_SIZE(exynos5_gpios_1);
2885
2886 for (i = 0; i < nr_chips; i++, chip++) {
2887 if (!chip->config) {
2888 chip->config = &exynos_gpio_cfg;
2889 chip->group = group++;
2890 }
2891 exynos_gpiolib_attach_ofnode(chip,
2892 EXYNOS5_PA_GPIO1, i * 0x20);
2893 }
2894 samsung_gpiolib_add_4bit_chips(exynos5_gpios_1,
2895 nr_chips, gpio_base1);
2896
2897 /* gpio part2 */
2898 gpio_base2 = ioremap(EXYNOS5_PA_GPIO2, SZ_4K);
2899 if (gpio_base2 == NULL) {
2900 pr_err("unable to ioremap for gpio_base2\n");
2901 goto err_ioremap2;
2902 }
2903
2904 chip = exynos5_gpios_2;
2905 nr_chips = ARRAY_SIZE(exynos5_gpios_2);
2906
2907 for (i = 0; i < nr_chips; i++, chip++) {
2908 if (!chip->config) {
2909 chip->config = &exynos_gpio_cfg;
2910 chip->group = group++;
2911 }
2912 exynos_gpiolib_attach_ofnode(chip,
2913 EXYNOS5_PA_GPIO2, i * 0x20);
2914 }
2915 samsung_gpiolib_add_4bit_chips(exynos5_gpios_2,
2916 nr_chips, gpio_base2);
2917
2918 /* gpio part3 */
2919 gpio_base3 = ioremap(EXYNOS5_PA_GPIO3, SZ_4K);
2920 if (gpio_base3 == NULL) {
2921 pr_err("unable to ioremap for gpio_base3\n");
2922 goto err_ioremap3;
2923 }
2924
2925 /* need to set base address for gpv */
2926 exynos5_gpios_3[0].base = gpio_base3;
2927 exynos5_gpios_3[1].base = gpio_base3 + 0x20;
2928 exynos5_gpios_3[2].base = gpio_base3 + 0x60;
2929 exynos5_gpios_3[3].base = gpio_base3 + 0x80;
2930 exynos5_gpios_3[4].base = gpio_base3 + 0xC0;
2931
2932 chip = exynos5_gpios_3;
2933 nr_chips = ARRAY_SIZE(exynos5_gpios_3);
2934
2935 for (i = 0; i < nr_chips; i++, chip++) {
2936 if (!chip->config) {
2937 chip->config = &exynos_gpio_cfg;
2938 chip->group = group++;
2939 }
2940 exynos_gpiolib_attach_ofnode(chip,
2941 EXYNOS5_PA_GPIO3, i * 0x20);
2942 }
2943 samsung_gpiolib_add_4bit_chips(exynos5_gpios_3,
2944 nr_chips, gpio_base3);
2945
2946 /* gpio part4 */
2947 gpio_base4 = ioremap(EXYNOS5_PA_GPIO4, SZ_4K);
2948 if (gpio_base4 == NULL) {
2949 pr_err("unable to ioremap for gpio_base4\n");
2950 goto err_ioremap4;
2951 }
2952
2953 chip = exynos5_gpios_4;
2954 nr_chips = ARRAY_SIZE(exynos5_gpios_4);
2955
2956 for (i = 0; i < nr_chips; i++, chip++) {
2957 if (!chip->config) {
2958 chip->config = &exynos_gpio_cfg;
2959 chip->group = group++;
2960 }
2961 exynos_gpiolib_attach_ofnode(chip,
2962 EXYNOS5_PA_GPIO4, i * 0x20);
2963 }
2964 samsung_gpiolib_add_4bit_chips(exynos5_gpios_4,
2965 nr_chips, gpio_base4);
2966#endif /* CONFIG_SOC_EXYNOS5250 */
2573 } else { 2967 } else {
2574 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n"); 2968 WARN(1, "Unknown SoC in gpio-samsung, no GPIOs added\n");
2575 return -ENODEV; 2969 return -ENODEV;
2576 } 2970 }
2577 2971
2578 return 0; 2972 return 0;
2973
2974err_ioremap4:
2975 iounmap(gpio_base3);
2976err_ioremap3:
2977 iounmap(gpio_base2);
2978err_ioremap2:
2979 iounmap(gpio_base1);
2980err_ioremap1:
2981 return -ENOMEM;
2579} 2982}
2580core_initcall(samsung_gpiolib_init); 2983core_initcall(samsung_gpiolib_init);
2581 2984
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 00:43:20 -0400