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authorVijay Rai <vijay.rai@freescale.com>2015-01-05 10:44:42 -0500
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>2015-01-09 17:33:04 -0500
commitfddceb8b5399083bcc042266f188116cc779fc80 (patch)
tree018ed4ac4038d64d739aacdf2fbd25e29a81ede9
parent5fafc8947d0b90473e9c2710088e8762802bcc56 (diff)
tty: 8250: Add 64byte UART support for FSL platforms
Some of FSL SoCs like T1040 has new version of UART controller which can support 64byte FiFo. To enable 64 byte support, following needs to be done: -FCR[EN64] needs to be programmed to 1 to enable it. -Also, when FCR[EN64]==1, RTL bits to be used as below to define various Receive Trigger Levels: -FCR[RTL] = 00 1 byte -FCR[RTL] = 01 16 bytes -FCR[RTL] = 10 32 bytes -FCR[RTL] = 11 56 bytes -tx_loadsz is set to 63-bytes instead of 64-bytes to implement workaround of errata A-008006 which states that tx_loadsz should be configured less than Maximum supported fifo bytes Signed-off-by: Vijay Rai <vijay.rai@freescale.com> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
-rw-r--r--drivers/tty/serial/8250/8250_core.c23
-rw-r--r--include/uapi/linux/serial_core.h3
-rw-r--r--include/uapi/linux/serial_reg.h3
3 files changed, 26 insertions, 3 deletions
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 3bfcfdb57d05..689169c11f0f 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -329,6 +329,17 @@ static const struct serial8250_config uart_config[] = {
329 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10, 329 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
330 .flags = UART_CAP_FIFO | UART_CAP_AFE, 330 .flags = UART_CAP_FIFO | UART_CAP_AFE,
331 }, 331 },
332/* tx_loadsz is set to 63-bytes instead of 64-bytes to implement
333workaround of errata A-008006 which states that tx_loadsz should be
334configured less than Maximum supported fifo bytes */
335 [PORT_16550A_FSL64] = {
336 .name = "16550A_FSL64",
337 .fifo_size = 64,
338 .tx_loadsz = 63,
339 .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10 |
340 UART_FCR7_64BYTE,
341 .flags = UART_CAP_FIFO,
342 },
332}; 343};
333 344
334/* Uart divisor latch read */ 345/* Uart divisor latch read */
@@ -956,7 +967,17 @@ static void autoconfig_16550a(struct uart_8250_port *up)
956 up->port.type = PORT_16650; 967 up->port.type = PORT_16650;
957 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP; 968 up->capabilities |= UART_CAP_EFR | UART_CAP_SLEEP;
958 } else { 969 } else {
959 DEBUG_AUTOCONF("Motorola 8xxx DUART "); 970 serial_out(up, UART_LCR, 0);
971 serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
972 UART_FCR7_64BYTE);
973 status1 = serial_in(up, UART_IIR) >> 5;
974 serial_out(up, UART_FCR, 0);
975 serial_out(up, UART_LCR, 0);
976
977 if (status1 == 7)
978 up->port.type = PORT_16550A_FSL64;
979 else
980 DEBUG_AUTOCONF("Motorola 8xxx DUART ");
960 } 981 }
961 serial_out(up, UART_EFR, 0); 982 serial_out(up, UART_EFR, 0);
962 return; 983 return;
diff --git a/include/uapi/linux/serial_core.h b/include/uapi/linux/serial_core.h
index 9124e837c181..ee628c489e47 100644
--- a/include/uapi/linux/serial_core.h
+++ b/include/uapi/linux/serial_core.h
@@ -55,7 +55,8 @@
55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */ 55#define PORT_ALTR_16550_F64 27 /* Altera 16550 UART with 64 FIFOs */
56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */ 56#define PORT_ALTR_16550_F128 28 /* Altera 16550 UART with 128 FIFOs */
57#define PORT_RT2880 29 /* Ralink RT2880 internal UART */ 57#define PORT_RT2880 29 /* Ralink RT2880 internal UART */
58#define PORT_MAX_8250 29 /* max port ID */ 58#define PORT_16550A_FSL64 30 /* Freescale 16550 UART with 64 FIFOs */
59#define PORT_MAX_8250 30 /* max port ID */
59 60
60/* 61/*
61 * ARM specific type numbers. These are not currently guaranteed 62 * ARM specific type numbers. These are not currently guaranteed
diff --git a/include/uapi/linux/serial_reg.h b/include/uapi/linux/serial_reg.h
index 53af3b790129..00adb01fa5f3 100644
--- a/include/uapi/linux/serial_reg.h
+++ b/include/uapi/linux/serial_reg.h
@@ -86,7 +86,8 @@
86#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */ 86#define UART_FCR6_T_TRIGGER_8 0x10 /* Mask for transmit trigger set at 8 */
87#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */ 87#define UART_FCR6_T_TRIGGER_24 0x20 /* Mask for transmit trigger set at 24 */
88#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */ 88#define UART_FCR6_T_TRIGGER_30 0x30 /* Mask for transmit trigger set at 30 */
89#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750) */ 89#define UART_FCR7_64BYTE 0x20 /* Go into 64 byte mode (TI16C750 and
90 some Freescale UARTs) */
90 91
91#define UART_FCR_R_TRIG_SHIFT 6 92#define UART_FCR_R_TRIG_SHIFT 6
92#define UART_FCR_R_TRIG_BITS(x) \ 93#define UART_FCR_R_TRIG_BITS(x) \