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authorLinus Walleij <linus.walleij@linaro.org>2013-11-15 03:28:39 -0500
committerLinus Walleij <linus.walleij@linaro.org>2013-11-26 15:01:56 -0500
commitfda989c0b51a563d23d3cf3d4c20dd3405268644 (patch)
tree99afa58955cf8dd74bac389638f65b88e2b30109
parent279571358df1e3f9788f1095d73b777fdb68c7e0 (diff)
ARM: ux500: drop STM pinmap settings
The pin mappings for the STM (System Trace Macrocell) are not really used by anything: we have no driver for is and the settings are not connected to any device. We can recreate the different mux outputs in the device tree the day we need them. Drop these for now. Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat
-rw-r--r--arch/arm/mach-ux500/board-mop500-pins.c200
1 files changed, 0 insertions, 200 deletions
diff --git a/arch/arm/mach-ux500/board-mop500-pins.c b/arch/arm/mach-ux500/board-mop500-pins.c
index 07ddb89a6dbe..c311d11d6c3d 100644
--- a/arch/arm/mach-ux500/board-mop500-pins.c
+++ b/arch/arm/mach-ux500/board-mop500-pins.c
@@ -27,7 +27,6 @@ static enum custom_pin_cfg_t pinsfor;
27#define BIAS(a,b) static unsigned long a[] = { b } 27#define BIAS(a,b) static unsigned long a[] = { b }
28 28
29BIAS(pd, PIN_PULL_DOWN); 29BIAS(pd, PIN_PULL_DOWN);
30BIAS(in_nopull, PIN_INPUT_NOPULL);
31BIAS(in_pu, PIN_INPUT_PULLUP); 30BIAS(in_pu, PIN_INPUT_PULLUP);
32BIAS(in_pd, PIN_INPUT_PULLDOWN); 31BIAS(in_pd, PIN_INPUT_PULLDOWN);
33BIAS(out_lo, PIN_OUTPUT_LOW); 32BIAS(out_lo, PIN_OUTPUT_LOW);
@@ -43,15 +42,6 @@ BIAS(gpio_in_pu_slpm_gpio_nopull, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED|PIN_SLPM
43BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL); 42BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
44BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED); 43BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
45BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED); 44BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
46/* Sleep modes */
47BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|
48 PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
49BIAS(slpm_out_lo_pdis, PIN_SLEEPMODE_ENABLED|
50 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE|PIN_SLPM_PDIS_DISABLED);
51BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|
52 PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
53BIAS(slpm_in_pu_wkup_pdis_en, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_PULLUP|
54 PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_ENABLED);
55 45
56/* We use these to define hog settings that are always done on boot */ 46/* We use these to define hog settings that are always done on boot */
57#define DB8500_MUX_HOG(group,func) \ 47#define DB8500_MUX_HOG(group,func) \
@@ -321,190 +311,6 @@ static struct pinctrl_map __initdata ab8505_pinmap[] = {
321 AB8505_PIN_HOG("GPIO53_D15", in_pd), 311 AB8505_PIN_HOG("GPIO53_D15", in_pd),
322}; 312};
323 313
324/* Pin control settings */
325static struct pinctrl_map __initdata mop500_family_pinmap[] = {
326 /* STM APE pins states */
327 DB8500_MUX_STATE("stmape_c_1", "stmape",
328 "stm", "ape_mipi34"),
329 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
330 "stm", "ape_mipi34"), /* clk */
331 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
332 "stm", "ape_mipi34"), /* dat3 */
333 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
334 "stm", "ape_mipi34"), /* dat2 */
335 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
336 "stm", "ape_mipi34"), /* dat1 */
337 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
338 "stm", "ape_mipi34"), /* dat0 */
339
340 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
341 "stm", "ape_mipi34_sleep"), /* clk */
342 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
343 "stm", "ape_mipi34_sleep"), /* dat3 */
344 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
345 "stm", "ape_mipi34_sleep"), /* dat2 */
346 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
347 "stm", "ape_mipi34_sleep"), /* dat1 */
348 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
349 "stm", "ape_mipi34_sleep"), /* dat0 */
350
351 DB8500_MUX_STATE("stmape_oc1_1", "stmape",
352 "stm", "ape_microsd"),
353 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
354 "stm", "ape_microsd"), /* clk */
355 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
356 "stm", "ape_microsd"), /* dat0 */
357 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
358 "stm", "ape_microsd"), /* dat1 */
359 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
360 "stm", "ape_microsd"), /* dat2 */
361 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
362 "stm", "ape_microsd"), /* dat3 */
363
364 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
365 "stm", "ape_microsd_sleep"), /* clk */
366 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
367 "stm", "ape_microsd_sleep"), /* dat0 */
368 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
369 "stm", "ape_microsd_sleep"), /* dat1 */
370 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
371 "stm", "ape_microsd_sleep"), /* dat2 */
372 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
373 "stm", "ape_microsd_sleep"), /* dat3 */
374
375 /* STM Modem pins states */
376 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
377 "stm", "mod_mipi34"),
378 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
379 "stm", "mod_mipi34"),
380 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
381 "stm", "mod_mipi34"),
382 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
383 "stm", "mod_mipi34"), /* clk */
384 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
385 "stm", "mod_mipi34"), /* dat3 */
386 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
387 "stm", "mod_mipi34"), /* dat2 */
388 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
389 "stm", "mod_mipi34"), /* dat1 */
390 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
391 "stm", "mod_mipi34"), /* dat0 */
392 DB8500_PIN_STATE("GPIO75_H2", in_pu,
393 "stm", "mod_mipi34"), /* uartmod rx */
394 DB8500_PIN_STATE("GPIO76_J2", out_lo,
395 "stm", "mod_mipi34"), /* uartmod tx */
396
397 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
398 "stm", "mod_mipi34_sleep"), /* clk */
399 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
400 "stm", "mod_mipi34_sleep"), /* dat3 */
401 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
402 "stm", "mod_mipi34_sleep"), /* dat2 */
403 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
404 "stm", "mod_mipi34_sleep"), /* dat1 */
405 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
406 "stm", "mod_mipi34_sleep"), /* dat0 */
407 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
408 "stm", "mod_mipi34_sleep"), /* uartmod rx */
409 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
410 "stm", "mod_mipi34_sleep"), /* uartmod tx */
411
412 DB8500_MUX_STATE("stmmod_b_1", "stmmod",
413 "stm", "mod_microsd"),
414 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
415 "stm", "mod_microsd"),
416 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
417 "stm", "mod_microsd"),
418 DB8500_PIN_STATE("GPIO23_AA4", in_nopull,
419 "stm", "mod_microsd"), /* clk */
420 DB8500_PIN_STATE("GPIO25_Y4", in_nopull,
421 "stm", "mod_microsd"), /* dat0 */
422 DB8500_PIN_STATE("GPIO26_Y2", in_nopull,
423 "stm", "mod_microsd"), /* dat1 */
424 DB8500_PIN_STATE("GPIO27_AA2", in_nopull,
425 "stm", "mod_microsd"), /* dat2 */
426 DB8500_PIN_STATE("GPIO28_AA1", in_nopull,
427 "stm", "mod_microsd"), /* dat3 */
428 DB8500_PIN_STATE("GPIO75_H2", in_pu,
429 "stm", "mod_microsd"), /* uartmod rx */
430 DB8500_PIN_STATE("GPIO76_J2", out_lo,
431 "stm", "mod_microsd"), /* uartmod tx */
432
433 DB8500_PIN_STATE("GPIO23_AA4", slpm_out_lo_wkup_pdis,
434 "stm", "mod_microsd_sleep"), /* clk */
435 DB8500_PIN_STATE("GPIO25_Y4", slpm_in_wkup_pdis,
436 "stm", "mod_microsd_sleep"), /* dat0 */
437 DB8500_PIN_STATE("GPIO26_Y2", slpm_in_wkup_pdis,
438 "stm", "mod_microsd_sleep"), /* dat1 */
439 DB8500_PIN_STATE("GPIO27_AA2", slpm_in_wkup_pdis,
440 "stm", "mod_microsd_sleep"), /* dat2 */
441 DB8500_PIN_STATE("GPIO28_AA1", slpm_in_wkup_pdis,
442 "stm", "mod_microsd_sleep"), /* dat3 */
443 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
444 "stm", "mod_microsd_sleep"), /* uartmod rx */
445 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
446 "stm", "mod_microsd_sleep"), /* uartmod tx */
447
448 /* STM dual Modem/APE pins state */
449 DB8500_MUX_STATE("stmmod_oc3_2", "stmmod",
450 "stm", "mod_mipi34_ape_mipi60"),
451 DB8500_MUX_STATE("stmape_c_2", "stmape",
452 "stm", "mod_mipi34_ape_mipi60"),
453 DB8500_MUX_STATE("uartmodrx_oc3_1", "uartmod",
454 "stm", "mod_mipi34_ape_mipi60"),
455 DB8500_MUX_STATE("uartmodtx_oc3_1", "uartmod",
456 "stm", "mod_mipi34_ape_mipi60"),
457 DB8500_PIN_STATE("GPIO70_G5", in_nopull,
458 "stm", "mod_mipi34_ape_mipi60"), /* clk */
459 DB8500_PIN_STATE("GPIO71_G4", in_nopull,
460 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
461 DB8500_PIN_STATE("GPIO72_H4", in_nopull,
462 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
463 DB8500_PIN_STATE("GPIO73_H3", in_nopull,
464 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
465 DB8500_PIN_STATE("GPIO74_J3", in_nopull,
466 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
467 DB8500_PIN_STATE("GPIO75_H2", in_pu,
468 "stm", "mod_mipi34_ape_mipi60"), /* uartmod rx */
469 DB8500_PIN_STATE("GPIO76_J2", out_lo,
470 "stm", "mod_mipi34_ape_mipi60"), /* uartmod tx */
471 DB8500_PIN_STATE("GPIO155_C19", in_nopull,
472 "stm", "mod_mipi34_ape_mipi60"), /* clk */
473 DB8500_PIN_STATE("GPIO156_C17", in_nopull,
474 "stm", "mod_mipi34_ape_mipi60"), /* dat3 */
475 DB8500_PIN_STATE("GPIO157_A18", in_nopull,
476 "stm", "mod_mipi34_ape_mipi60"), /* dat2 */
477 DB8500_PIN_STATE("GPIO158_C18", in_nopull,
478 "stm", "mod_mipi34_ape_mipi60"), /* dat1 */
479 DB8500_PIN_STATE("GPIO159_B19", in_nopull,
480 "stm", "mod_mipi34_ape_mipi60"), /* dat0 */
481
482 DB8500_PIN_STATE("GPIO70_G5", slpm_out_lo_pdis,
483 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
484 DB8500_PIN_STATE("GPIO71_G4", slpm_out_lo_pdis,
485 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
486 DB8500_PIN_STATE("GPIO72_H4", slpm_out_lo_pdis,
487 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
488 DB8500_PIN_STATE("GPIO73_H3", slpm_out_lo_pdis,
489 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
490 DB8500_PIN_STATE("GPIO74_J3", slpm_out_lo_pdis,
491 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
492 DB8500_PIN_STATE("GPIO75_H2", slpm_in_wkup_pdis,
493 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod rx */
494 DB8500_PIN_STATE("GPIO76_J2", slpm_out_lo_wkup_pdis,
495 "stm", "mod_mipi34_ape_mipi60_sleep"), /* uartmod tx */
496 DB8500_PIN_STATE("GPIO155_C19", slpm_in_wkup_pdis,
497 "stm", "mod_mipi34_ape_mipi60_sleep"), /* clk */
498 DB8500_PIN_STATE("GPIO156_C17", slpm_in_wkup_pdis,
499 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat3 */
500 DB8500_PIN_STATE("GPIO157_A18", slpm_in_wkup_pdis,
501 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat2 */
502 DB8500_PIN_STATE("GPIO158_C18", slpm_in_wkup_pdis,
503 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat1 */
504 DB8500_PIN_STATE("GPIO159_B19", slpm_in_wkup_pdis,
505 "stm", "mod_mipi34_ape_mipi60_sleep"), /* dat0 */
506};
507
508/* 314/*
509 * These are specifically for the MOP500 and HREFP (pre-v60) version of the 315 * These are specifically for the MOP500 and HREFP (pre-v60) version of the
510 * board, which utilized a TC35892 GPIO expander instead of using a lot of 316 * board, which utilized a TC35892 GPIO expander instead of using a lot of
@@ -690,8 +496,6 @@ static void __init mop500_href_family_pinmaps_init(void)
690 496
691void __init mop500_pinmaps_init(void) 497void __init mop500_pinmaps_init(void)
692{ 498{
693 pinctrl_register_mappings(mop500_family_pinmap,
694 ARRAY_SIZE(mop500_family_pinmap));
695 pinctrl_register_mappings(mop500_pinmap, 499 pinctrl_register_mappings(mop500_pinmap,
696 ARRAY_SIZE(mop500_pinmap)); 500 ARRAY_SIZE(mop500_pinmap));
697 mop500_href_family_pinmaps_init(); 501 mop500_href_family_pinmaps_init();
@@ -705,8 +509,6 @@ void __init mop500_pinmaps_init(void)
705 509
706void __init snowball_pinmaps_init(void) 510void __init snowball_pinmaps_init(void)
707{ 511{
708 pinctrl_register_mappings(mop500_family_pinmap,
709 ARRAY_SIZE(mop500_family_pinmap));
710 pinctrl_register_mappings(snowball_pinmap, 512 pinctrl_register_mappings(snowball_pinmap,
711 ARRAY_SIZE(snowball_pinmap)); 513 ARRAY_SIZE(snowball_pinmap));
712 pinctrl_register_mappings(u8500_pinmap, 514 pinctrl_register_mappings(u8500_pinmap,
@@ -717,8 +519,6 @@ void __init snowball_pinmaps_init(void)
717 519
718void __init hrefv60_pinmaps_init(void) 520void __init hrefv60_pinmaps_init(void)
719{ 521{
720 pinctrl_register_mappings(mop500_family_pinmap,
721 ARRAY_SIZE(mop500_family_pinmap));
722 pinctrl_register_mappings(hrefv60_pinmap, 522 pinctrl_register_mappings(hrefv60_pinmap,
723 ARRAY_SIZE(hrefv60_pinmap)); 523 ARRAY_SIZE(hrefv60_pinmap));
724 mop500_href_family_pinmaps_init(); 524 mop500_href_family_pinmaps_init();
generated by cgit v1.2.2 (git 2.25.0) at 2025-07-16 12:48:55 -0400