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authorChew, Chiau Ee <chiau.ee.chew@intel.com>2013-05-16 03:33:29 -0400
committerTejun Heo <tj@kernel.org>2013-05-16 14:06:29 -0400
commitfca8c90d519dedd4f4b19901d005c243f7f0bf2e (patch)
tree016c4c1bd8d0d8cb28b0ac25f27b51b980703947
parent8c3d3d4b12bf8de8c59fe1eb1bf866a8676ca309 (diff)
ata_piix: add PCI IDs for Intel BayTail
Adds IDE-mode SATA Device IDs for the Intel BayTrail platform. Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com> Signed-off-by: Tejun Heo <tj@kernel.org> Cc: stable@vger.kernel.org
-rw-r--r--drivers/ata/ata_piix.c15
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 26bda6ed9a00..9a8a674e8fac 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -151,6 +151,7 @@ enum piix_controller_ids {
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */ 151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb, 152 ich8_sata_snb,
153 ich8_2port_sata_snb, 153 ich8_2port_sata_snb,
154 ich8_2port_sata_byt,
154}; 155};
155 156
156struct piix_map_db { 157struct piix_map_db {
@@ -334,6 +335,9 @@ static const struct pci_device_id piix_pci_tbl[] = {
334 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb }, 335 { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
335 /* SATA Controller IDE (Wellsburg) */ 336 /* SATA Controller IDE (Wellsburg) */
336 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata }, 337 { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
338 /* SATA Controller IDE (BayTrail) */
339 { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
340 { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
337 341
338 { } /* terminate list */ 342 { } /* terminate list */
339}; 343};
@@ -441,6 +445,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
441 [tolapai_sata] = &tolapai_map_db, 445 [tolapai_sata] = &tolapai_map_db,
442 [ich8_sata_snb] = &ich8_map_db, 446 [ich8_sata_snb] = &ich8_map_db,
443 [ich8_2port_sata_snb] = &ich8_2port_map_db, 447 [ich8_2port_sata_snb] = &ich8_2port_map_db,
448 [ich8_2port_sata_byt] = &ich8_2port_map_db,
444}; 449};
445 450
446static struct pci_bits piix_enable_bits[] = { 451static struct pci_bits piix_enable_bits[] = {
@@ -1254,6 +1259,16 @@ static struct ata_port_info piix_port_info[] = {
1254 .udma_mask = ATA_UDMA6, 1259 .udma_mask = ATA_UDMA6,
1255 .port_ops = &piix_sata_ops, 1260 .port_ops = &piix_sata_ops,
1256 }, 1261 },
1262
1263 [ich8_2port_sata_byt] =
1264 {
1265 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1266 .pio_mask = ATA_PIO4,
1267 .mwdma_mask = ATA_MWDMA2,
1268 .udma_mask = ATA_UDMA6,
1269 .port_ops = &piix_sata_ops,
1270 },
1271
1257}; 1272};
1258 1273
1259#define AHCI_PCI_BAR 5 1274#define AHCI_PCI_BAR 5