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authorAlex Deucher <alexander.deucher@amd.com>2013-08-06 12:40:16 -0400
committerAlex Deucher <alexander.deucher@amd.com>2013-08-07 17:37:18 -0400
commitf61d5b46771a352fad1ac7f99008ef52a7ffcb72 (patch)
treeb305a6940a4b04980f54e30a0807ada45eed6d1f
parent3744b248f9c617295f1fd015d67281a67e592ecb (diff)
drm/radeon/cik: use a mutex to properly lock srbm instanced registers
We need proper locking in the driver when accessing instanced registers on CIK. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
-rw-r--r--drivers/gpu/drm/radeon/cik.c10
-rw-r--r--drivers/gpu/drm/radeon/radeon.h2
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c1
3 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 58136f20c060..8928bd109c16 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2587,9 +2587,11 @@ u32 cik_compute_ring_get_rptr(struct radeon_device *rdev,
2587 if (rdev->wb.enabled) { 2587 if (rdev->wb.enabled) {
2588 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]); 2588 rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
2589 } else { 2589 } else {
2590 mutex_lock(&rdev->srbm_mutex);
2590 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 2591 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
2591 rptr = RREG32(CP_HQD_PQ_RPTR); 2592 rptr = RREG32(CP_HQD_PQ_RPTR);
2592 cik_srbm_select(rdev, 0, 0, 0, 0); 2593 cik_srbm_select(rdev, 0, 0, 0, 0);
2594 mutex_unlock(&rdev->srbm_mutex);
2593 } 2595 }
2594 rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 2596 rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
2595 2597
@@ -2604,9 +2606,11 @@ u32 cik_compute_ring_get_wptr(struct radeon_device *rdev,
2604 if (rdev->wb.enabled) { 2606 if (rdev->wb.enabled) {
2605 wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]); 2607 wptr = le32_to_cpu(rdev->wb.wb[ring->wptr_offs/4]);
2606 } else { 2608 } else {
2609 mutex_lock(&rdev->srbm_mutex);
2607 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0); 2610 cik_srbm_select(rdev, ring->me, ring->pipe, ring->queue, 0);
2608 wptr = RREG32(CP_HQD_PQ_WPTR); 2611 wptr = RREG32(CP_HQD_PQ_WPTR);
2609 cik_srbm_select(rdev, 0, 0, 0, 0); 2612 cik_srbm_select(rdev, 0, 0, 0, 0);
2613 mutex_unlock(&rdev->srbm_mutex);
2610 } 2614 }
2611 wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift; 2615 wptr = (wptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
2612 2616
@@ -2897,6 +2901,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
2897 WREG32(CP_CPF_DEBUG, tmp); 2901 WREG32(CP_CPF_DEBUG, tmp);
2898 2902
2899 /* init the pipes */ 2903 /* init the pipes */
2904 mutex_lock(&rdev->srbm_mutex);
2900 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) { 2905 for (i = 0; i < (rdev->mec.num_pipe * rdev->mec.num_mec); i++) {
2901 int me = (i < 4) ? 1 : 2; 2906 int me = (i < 4) ? 1 : 2;
2902 int pipe = (i < 4) ? i : (i - 4); 2907 int pipe = (i < 4) ? i : (i - 4);
@@ -2919,6 +2924,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
2919 WREG32(CP_HPD_EOP_CONTROL, tmp); 2924 WREG32(CP_HPD_EOP_CONTROL, tmp);
2920 } 2925 }
2921 cik_srbm_select(rdev, 0, 0, 0, 0); 2926 cik_srbm_select(rdev, 0, 0, 0, 0);
2927 mutex_unlock(&rdev->srbm_mutex);
2922 2928
2923 /* init the queues. Just two for now. */ 2929 /* init the queues. Just two for now. */
2924 for (i = 0; i < 2; i++) { 2930 for (i = 0; i < 2; i++) {
@@ -2972,6 +2978,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
2972 mqd->static_thread_mgmt23[0] = 0xffffffff; 2978 mqd->static_thread_mgmt23[0] = 0xffffffff;
2973 mqd->static_thread_mgmt23[1] = 0xffffffff; 2979 mqd->static_thread_mgmt23[1] = 0xffffffff;
2974 2980
2981 mutex_lock(&rdev->srbm_mutex);
2975 cik_srbm_select(rdev, rdev->ring[idx].me, 2982 cik_srbm_select(rdev, rdev->ring[idx].me,
2976 rdev->ring[idx].pipe, 2983 rdev->ring[idx].pipe,
2977 rdev->ring[idx].queue, 0); 2984 rdev->ring[idx].queue, 0);
@@ -3099,6 +3106,7 @@ static int cik_cp_compute_resume(struct radeon_device *rdev)
3099 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active); 3106 WREG32(CP_HQD_ACTIVE, mqd->queue_state.cp_hqd_active);
3100 3107
3101 cik_srbm_select(rdev, 0, 0, 0, 0); 3108 cik_srbm_select(rdev, 0, 0, 0, 0);
3109 mutex_unlock(&rdev->srbm_mutex);
3102 3110
3103 radeon_bo_kunmap(rdev->ring[idx].mqd_obj); 3111 radeon_bo_kunmap(rdev->ring[idx].mqd_obj);
3104 radeon_bo_unreserve(rdev->ring[idx].mqd_obj); 3112 radeon_bo_unreserve(rdev->ring[idx].mqd_obj);
@@ -4320,6 +4328,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
4320 4328
4321 /* XXX SH_MEM regs */ 4329 /* XXX SH_MEM regs */
4322 /* where to put LDS, scratch, GPUVM in FSA64 space */ 4330 /* where to put LDS, scratch, GPUVM in FSA64 space */
4331 mutex_lock(&rdev->srbm_mutex);
4323 for (i = 0; i < 16; i++) { 4332 for (i = 0; i < 16; i++) {
4324 cik_srbm_select(rdev, 0, 0, 0, i); 4333 cik_srbm_select(rdev, 0, 0, 0, i);
4325 /* CP and shaders */ 4334 /* CP and shaders */
@@ -4335,6 +4344,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
4335 /* XXX SDMA RLC - todo */ 4344 /* XXX SDMA RLC - todo */
4336 } 4345 }
4337 cik_srbm_select(rdev, 0, 0, 0, 0); 4346 cik_srbm_select(rdev, 0, 0, 0, 0);
4347 mutex_unlock(&rdev->srbm_mutex);
4338 4348
4339 cik_pcie_gart_tlb_flush(rdev); 4349 cik_pcie_gart_tlb_flush(rdev);
4340 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", 4350 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 76dbe8e9b5c8..274b8e1b889f 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -2095,6 +2095,8 @@ struct radeon_device {
2095 /* ACPI interface */ 2095 /* ACPI interface */
2096 struct radeon_atif atif; 2096 struct radeon_atif atif;
2097 struct radeon_atcs atcs; 2097 struct radeon_atcs atcs;
2098 /* srbm instance registers */
2099 struct mutex srbm_mutex;
2098}; 2100};
2099 2101
2100int radeon_device_init(struct radeon_device *rdev, 2102int radeon_device_init(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 84dd2dcbcf69..63398ae1dbf5 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -1163,6 +1163,7 @@ int radeon_device_init(struct radeon_device *rdev,
1163 mutex_init(&rdev->gem.mutex); 1163 mutex_init(&rdev->gem.mutex);
1164 mutex_init(&rdev->pm.mutex); 1164 mutex_init(&rdev->pm.mutex);
1165 mutex_init(&rdev->gpu_clock_mutex); 1165 mutex_init(&rdev->gpu_clock_mutex);
1166 mutex_init(&rdev->srbm_mutex);
1166 init_rwsem(&rdev->pm.mclk_lock); 1167 init_rwsem(&rdev->pm.mclk_lock);
1167 init_rwsem(&rdev->exclusive_lock); 1168 init_rwsem(&rdev->exclusive_lock);
1168 init_waitqueue_head(&rdev->irq.vblank_queue); 1169 init_waitqueue_head(&rdev->irq.vblank_queue);