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authorHeiko Stuebner <heiko@sntech.de>2013-01-29 13:25:22 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-02-03 18:52:46 -0500
commitef602eb53c84100ab801ffa3a11ea02315fe38a8 (patch)
tree777a5643be1bf1afe0b860eae42a1296a9edbfc3
parentb4a343e5b333ca02f7731c824b600fe64d8ce28c (diff)
ARM: S3C24XX: move s3c2416 irq init to common irq code
This is needed to further clean up the irq init. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-s3c24xx/Makefile2
-rw-r--r--arch/arm/mach-s3c24xx/irq-pm.c23
-rw-r--r--arch/arm/mach-s3c24xx/irq-s3c2416.c348
-rw-r--r--arch/arm/plat-s3c24xx/irq.c286
4 files changed, 310 insertions, 349 deletions
diff --git a/arch/arm/mach-s3c24xx/Makefile b/arch/arm/mach-s3c24xx/Makefile
index 08b87cdb98b7..68d134f4efa0 100644
--- a/arch/arm/mach-s3c24xx/Makefile
+++ b/arch/arm/mach-s3c24xx/Makefile
@@ -28,7 +28,7 @@ obj-$(CONFIG_S3C2412_DMA) += dma-s3c2412.o
28obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o 28obj-$(CONFIG_S3C2412_PM) += pm-s3c2412.o
29obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o 29obj-$(CONFIG_S3C2412_PM_SLEEP) += sleep-s3c2412.o
30 30
31obj-$(CONFIG_CPU_S3C2416) += s3c2416.o irq-s3c2416.o clock-s3c2416.o 31obj-$(CONFIG_CPU_S3C2416) += s3c2416.o clock-s3c2416.o
32obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o 32obj-$(CONFIG_S3C2416_PM) += pm-s3c2416.o
33 33
34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o 34obj-$(CONFIG_CPU_S3C2440) += s3c2440.o irq-s3c2440.o clock-s3c2440.o
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index 640ec916f4c7..e1199599873e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -99,3 +99,26 @@ struct syscore_ops s3c24xx_irq_syscore_ops = {
99 .suspend = s3c24xx_irq_suspend, 99 .suspend = s3c24xx_irq_suspend,
100 .resume = s3c24xx_irq_resume, 100 .resume = s3c24xx_irq_resume,
101}; 101};
102
103#ifdef CONFIG_CPU_S3C2416
104static struct sleep_save s3c2416_irq_save[] = {
105 SAVE_ITEM(S3C2416_INTMSK2),
106};
107
108static int s3c2416_irq_suspend(void)
109{
110 s3c_pm_do_save(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
111
112 return 0;
113}
114
115static void s3c2416_irq_resume(void)
116{
117 s3c_pm_do_restore(s3c2416_irq_save, ARRAY_SIZE(s3c2416_irq_save));
118}
119
120struct syscore_ops s3c2416_irq_syscore_ops = {
121 .suspend = s3c2416_irq_suspend,
122 .resume = s3c2416_irq_resume,
123};
124#endif
diff --git a/arch/arm/mach-s3c24xx/irq-s3c2416.c b/arch/arm/mach-s3c24xx/irq-s3c2416.c
deleted file mode 100644
index ff141b0af26b..000000000000
--- a/arch/arm/mach-s3c24xx/irq-s3c2416.c
+++ /dev/null
@@ -1,348 +0,0 @@
1/* linux/arch/arm/mach-s3c2416/irq.c
2 *
3 * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>,
4 * as part of OpenInkpot project
5 * Copyright (c) 2009 Promwad Innovation Company
6 * Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22*/
23
24#include <linux/init.h>
25#include <linux/module.h>
26#include <linux/interrupt.h>
27#include <linux/ioport.h>
28#include <linux/device.h>
29#include <linux/io.h>
30#include <linux/syscore_ops.h>
31
32#include <mach/hardware.h>
33#include <asm/irq.h>
34
35#include <asm/mach/irq.h>
36
37#include <mach/regs-irq.h>
38#include <mach/regs-gpio.h>
39
40#include <plat/cpu.h>
41#include <plat/pm.h>
42#include <plat/irq.h>
43
44#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
45
46static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
47{
48 unsigned int subsrc, submsk;
49 unsigned int end;
50
51 /* read the current pending interrupts, and the mask
52 * for what it is available */
53
54 subsrc = __raw_readl(S3C2410_SUBSRCPND);
55 submsk = __raw_readl(S3C2410_INTSUBMSK);
56
57 subsrc &= ~submsk;
58 subsrc >>= (irq - S3C2410_IRQSUB(0));
59 subsrc &= (1 << len)-1;
60
61 end = len + irq;
62
63 for (; irq < end && subsrc; irq++) {
64 if (subsrc & 1)
65 generic_handle_irq(irq);
66
67 subsrc >>= 1;
68 }
69}
70
71/* WDT/AC97 sub interrupts */
72
73static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
74{
75 s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
76}
77
78#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
79#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
80
81static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
82{
83 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
84}
85
86static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
87{
88 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
89}
90
91static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
92{
93 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
94}
95
96static struct irq_chip s3c2416_irq_wdtac97 = {
97 .irq_mask = s3c2416_irq_wdtac97_mask,
98 .irq_unmask = s3c2416_irq_wdtac97_unmask,
99 .irq_ack = s3c2416_irq_wdtac97_ack,
100};
101
102/* LCD sub interrupts */
103
104static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
105{
106 s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
107}
108
109#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
110#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
111
112static void s3c2416_irq_lcd_mask(struct irq_data *data)
113{
114 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
115}
116
117static void s3c2416_irq_lcd_unmask(struct irq_data *data)
118{
119 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
120}
121
122static void s3c2416_irq_lcd_ack(struct irq_data *data)
123{
124 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
125}
126
127static struct irq_chip s3c2416_irq_lcd = {
128 .irq_mask = s3c2416_irq_lcd_mask,
129 .irq_unmask = s3c2416_irq_lcd_unmask,
130 .irq_ack = s3c2416_irq_lcd_ack,
131};
132
133/* DMA sub interrupts */
134
135static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
136{
137 s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
138}
139
140#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
141#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
142
143
144static void s3c2416_irq_dma_mask(struct irq_data *data)
145{
146 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
147}
148
149static void s3c2416_irq_dma_unmask(struct irq_data *data)
150{
151 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
152}
153
154static void s3c2416_irq_dma_ack(struct irq_data *data)
155{
156 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
157}
158
159static struct irq_chip s3c2416_irq_dma = {
160 .irq_mask = s3c2416_irq_dma_mask,
161 .irq_unmask = s3c2416_irq_dma_unmask,
162 .irq_ack = s3c2416_irq_dma_ack,
163};
164
165/* UART3 sub interrupts */
166
167static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
168{
169 s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
170}
171
172#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
173#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
174
175static void s3c2416_irq_uart3_mask(struct irq_data *data)
176{
177 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
178}
179
180static void s3c2416_irq_uart3_unmask(struct irq_data *data)
181{
182 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
183}
184
185static void s3c2416_irq_uart3_ack(struct irq_data *data)
186{
187 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
188}
189
190static struct irq_chip s3c2416_irq_uart3 = {
191 .irq_mask = s3c2416_irq_uart3_mask,
192 .irq_unmask = s3c2416_irq_uart3_unmask,
193 .irq_ack = s3c2416_irq_uart3_ack,
194};
195
196/* second interrupt register */
197
198static inline void s3c2416_irq_ack_second(struct irq_data *data)
199{
200 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
201
202 __raw_writel(bitval, S3C2416_SRCPND2);
203 __raw_writel(bitval, S3C2416_INTPND2);
204}
205
206static void s3c2416_irq_mask_second(struct irq_data *data)
207{
208 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
209 unsigned long mask;
210
211 mask = __raw_readl(S3C2416_INTMSK2);
212 mask |= bitval;
213 __raw_writel(mask, S3C2416_INTMSK2);
214}
215
216static void s3c2416_irq_unmask_second(struct irq_data *data)
217{
218 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
219 unsigned long mask;
220
221 mask = __raw_readl(S3C2416_INTMSK2);
222 mask &= ~bitval;
223 __raw_writel(mask, S3C2416_INTMSK2);
224}
225
226struct irq_chip s3c2416_irq_second = {
227 .irq_ack = s3c2416_irq_ack_second,
228 .irq_mask = s3c2416_irq_mask_second,
229 .irq_unmask = s3c2416_irq_unmask_second,
230};
231
232
233/* IRQ initialisation code */
234
235static int s3c2416_add_sub(unsigned int base,
236 void (*demux)(unsigned int,
237 struct irq_desc *),
238 struct irq_chip *chip,
239 unsigned int start, unsigned int end)
240{
241 unsigned int irqno;
242
243 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
244 irq_set_chained_handler(base, demux);
245
246 for (irqno = start; irqno <= end; irqno++) {
247 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
248 set_irq_flags(irqno, IRQF_VALID);
249 }
250
251 return 0;
252}
253
254static void s3c2416_irq_add_second(void)
255{
256 unsigned long pend;
257 unsigned long last;
258 int irqno;
259 int i;
260
261 /* first, clear all interrupts pending... */
262 last = 0;
263 for (i = 0; i < 4; i++) {
264 pend = __raw_readl(S3C2416_INTPND2);
265
266 if (pend == 0 || pend == last)
267 break;
268
269 __raw_writel(pend, S3C2416_SRCPND2);
270 __raw_writel(pend, S3C2416_INTPND2);
271 printk(KERN_INFO "irq: clearing pending status %08x\n",
272 (int)pend);
273 last = pend;
274 }
275
276 for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
277 switch (irqno) {
278 case IRQ_S3C2416_RESERVED2:
279 case IRQ_S3C2416_RESERVED3:
280 /* no IRQ here */
281 break;
282 default:
283 irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
284 handle_edge_irq);
285 set_irq_flags(irqno, IRQF_VALID);
286 }
287 }
288}
289
290static int s3c2416_irq_add(struct device *dev,
291 struct subsys_interface *sif)
292{
293 printk(KERN_INFO "S3C2416: IRQ Support\n");
294
295 s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
296 IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
297
298 s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
299 &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
300
301 s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
302 &s3c2416_irq_uart3,
303 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
304
305 s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
306 &s3c2416_irq_wdtac97,
307 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
308
309 s3c2416_irq_add_second();
310
311 return 0;
312}
313
314static struct subsys_interface s3c2416_irq_interface = {
315 .name = "s3c2416_irq",
316 .subsys = &s3c2416_subsys,
317 .add_dev = s3c2416_irq_add,
318};
319
320static int __init s3c2416_irq_init(void)
321{
322 return subsys_interface_register(&s3c2416_irq_interface);
323}
324
325arch_initcall(s3c2416_irq_init);
326
327#ifdef CONFIG_PM
328static struct sleep_save irq_save[] = {
329 SAVE_ITEM(S3C2416_INTMSK2),
330};
331
332int s3c2416_irq_suspend(void)
333{
334 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
335
336 return 0;
337}
338
339void s3c2416_irq_resume(void)
340{
341 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
342}
343
344struct syscore_ops s3c2416_irq_syscore_ops = {
345 .suspend = s3c2416_irq_suspend,
346 .resume = s3c2416_irq_resume,
347};
348#endif
diff --git a/arch/arm/plat-s3c24xx/irq.c b/arch/arm/plat-s3c24xx/irq.c
index 259d0e4a532f..e43214461960 100644
--- a/arch/arm/plat-s3c24xx/irq.c
+++ b/arch/arm/plat-s3c24xx/irq.c
@@ -626,3 +626,289 @@ void __init s3c24xx_init_irq(void)
626 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018); 626 s3c24xx_init_intc(NULL, &init_subint[0], main_intc, 0x4a000018);
627 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4); 627 s3c24xx_init_intc(NULL, &init_eint[0], main_intc, 0x560000a4);
628} 628}
629
630#ifdef CONFIG_CPU_S3C2416
631#define INTMSK(start, end) ((1 << ((end) + 1 - (start))) - 1)
632
633static inline void s3c2416_irq_demux(unsigned int irq, unsigned int len)
634{
635 unsigned int subsrc, submsk;
636 unsigned int end;
637
638 /* read the current pending interrupts, and the mask
639 * for what it is available */
640
641 subsrc = __raw_readl(S3C2410_SUBSRCPND);
642 submsk = __raw_readl(S3C2410_INTSUBMSK);
643
644 subsrc &= ~submsk;
645 subsrc >>= (irq - S3C2410_IRQSUB(0));
646 subsrc &= (1 << len)-1;
647
648 end = len + irq;
649
650 for (; irq < end && subsrc; irq++) {
651 if (subsrc & 1)
652 generic_handle_irq(irq);
653
654 subsrc >>= 1;
655 }
656}
657
658/* WDT/AC97 sub interrupts */
659
660static void s3c2416_irq_demux_wdtac97(unsigned int irq, struct irq_desc *desc)
661{
662 s3c2416_irq_demux(IRQ_S3C2443_WDT, 4);
663}
664
665#define INTMSK_WDTAC97 (1UL << (IRQ_WDT - IRQ_EINT0))
666#define SUBMSK_WDTAC97 INTMSK(IRQ_S3C2443_WDT, IRQ_S3C2443_AC97)
667
668static void s3c2416_irq_wdtac97_mask(struct irq_data *data)
669{
670 s3c_irqsub_mask(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
671}
672
673static void s3c2416_irq_wdtac97_unmask(struct irq_data *data)
674{
675 s3c_irqsub_unmask(data->irq, INTMSK_WDTAC97);
676}
677
678static void s3c2416_irq_wdtac97_ack(struct irq_data *data)
679{
680 s3c_irqsub_maskack(data->irq, INTMSK_WDTAC97, SUBMSK_WDTAC97);
681}
682
683static struct irq_chip s3c2416_irq_wdtac97 = {
684 .irq_mask = s3c2416_irq_wdtac97_mask,
685 .irq_unmask = s3c2416_irq_wdtac97_unmask,
686 .irq_ack = s3c2416_irq_wdtac97_ack,
687};
688
689/* LCD sub interrupts */
690
691static void s3c2416_irq_demux_lcd(unsigned int irq, struct irq_desc *desc)
692{
693 s3c2416_irq_demux(IRQ_S3C2443_LCD1, 4);
694}
695
696#define INTMSK_LCD (1UL << (IRQ_LCD - IRQ_EINT0))
697#define SUBMSK_LCD INTMSK(IRQ_S3C2443_LCD1, IRQ_S3C2443_LCD4)
698
699static void s3c2416_irq_lcd_mask(struct irq_data *data)
700{
701 s3c_irqsub_mask(data->irq, INTMSK_LCD, SUBMSK_LCD);
702}
703
704static void s3c2416_irq_lcd_unmask(struct irq_data *data)
705{
706 s3c_irqsub_unmask(data->irq, INTMSK_LCD);
707}
708
709static void s3c2416_irq_lcd_ack(struct irq_data *data)
710{
711 s3c_irqsub_maskack(data->irq, INTMSK_LCD, SUBMSK_LCD);
712}
713
714static struct irq_chip s3c2416_irq_lcd = {
715 .irq_mask = s3c2416_irq_lcd_mask,
716 .irq_unmask = s3c2416_irq_lcd_unmask,
717 .irq_ack = s3c2416_irq_lcd_ack,
718};
719
720/* DMA sub interrupts */
721
722static void s3c2416_irq_demux_dma(unsigned int irq, struct irq_desc *desc)
723{
724 s3c2416_irq_demux(IRQ_S3C2443_DMA0, 6);
725}
726
727#define INTMSK_DMA (1UL << (IRQ_S3C2443_DMA - IRQ_EINT0))
728#define SUBMSK_DMA INTMSK(IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5)
729
730
731static void s3c2416_irq_dma_mask(struct irq_data *data)
732{
733 s3c_irqsub_mask(data->irq, INTMSK_DMA, SUBMSK_DMA);
734}
735
736static void s3c2416_irq_dma_unmask(struct irq_data *data)
737{
738 s3c_irqsub_unmask(data->irq, INTMSK_DMA);
739}
740
741static void s3c2416_irq_dma_ack(struct irq_data *data)
742{
743 s3c_irqsub_maskack(data->irq, INTMSK_DMA, SUBMSK_DMA);
744}
745
746static struct irq_chip s3c2416_irq_dma = {
747 .irq_mask = s3c2416_irq_dma_mask,
748 .irq_unmask = s3c2416_irq_dma_unmask,
749 .irq_ack = s3c2416_irq_dma_ack,
750};
751
752/* UART3 sub interrupts */
753
754static void s3c2416_irq_demux_uart3(unsigned int irq, struct irq_desc *desc)
755{
756 s3c2416_irq_demux(IRQ_S3C2443_RX3, 3);
757}
758
759#define INTMSK_UART3 (1UL << (IRQ_S3C2443_UART3 - IRQ_EINT0))
760#define SUBMSK_UART3 (0x7 << (IRQ_S3C2443_RX3 - S3C2410_IRQSUB(0)))
761
762static void s3c2416_irq_uart3_mask(struct irq_data *data)
763{
764 s3c_irqsub_mask(data->irq, INTMSK_UART3, SUBMSK_UART3);
765}
766
767static void s3c2416_irq_uart3_unmask(struct irq_data *data)
768{
769 s3c_irqsub_unmask(data->irq, INTMSK_UART3);
770}
771
772static void s3c2416_irq_uart3_ack(struct irq_data *data)
773{
774 s3c_irqsub_maskack(data->irq, INTMSK_UART3, SUBMSK_UART3);
775}
776
777static struct irq_chip s3c2416_irq_uart3 = {
778 .irq_mask = s3c2416_irq_uart3_mask,
779 .irq_unmask = s3c2416_irq_uart3_unmask,
780 .irq_ack = s3c2416_irq_uart3_ack,
781};
782
783/* second interrupt register */
784
785static inline void s3c2416_irq_ack_second(struct irq_data *data)
786{
787 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
788
789 __raw_writel(bitval, S3C2416_SRCPND2);
790 __raw_writel(bitval, S3C2416_INTPND2);
791}
792
793static void s3c2416_irq_mask_second(struct irq_data *data)
794{
795 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
796 unsigned long mask;
797
798 mask = __raw_readl(S3C2416_INTMSK2);
799 mask |= bitval;
800 __raw_writel(mask, S3C2416_INTMSK2);
801}
802
803static void s3c2416_irq_unmask_second(struct irq_data *data)
804{
805 unsigned long bitval = 1UL << (data->irq - IRQ_S3C2416_2D);
806 unsigned long mask;
807
808 mask = __raw_readl(S3C2416_INTMSK2);
809 mask &= ~bitval;
810 __raw_writel(mask, S3C2416_INTMSK2);
811}
812
813static struct irq_chip s3c2416_irq_second = {
814 .irq_ack = s3c2416_irq_ack_second,
815 .irq_mask = s3c2416_irq_mask_second,
816 .irq_unmask = s3c2416_irq_unmask_second,
817};
818
819
820/* IRQ initialisation code */
821
822static int s3c2416_add_sub(unsigned int base,
823 void (*demux)(unsigned int,
824 struct irq_desc *),
825 struct irq_chip *chip,
826 unsigned int start, unsigned int end)
827{
828 unsigned int irqno;
829
830 irq_set_chip_and_handler(base, &s3c_irq_level_chip, handle_level_irq);
831 irq_set_chained_handler(base, demux);
832
833 for (irqno = start; irqno <= end; irqno++) {
834 irq_set_chip_and_handler(irqno, chip, handle_level_irq);
835 set_irq_flags(irqno, IRQF_VALID);
836 }
837
838 return 0;
839}
840
841static void s3c2416_irq_add_second(void)
842{
843 unsigned long pend;
844 unsigned long last;
845 int irqno;
846 int i;
847
848 /* first, clear all interrupts pending... */
849 last = 0;
850 for (i = 0; i < 4; i++) {
851 pend = __raw_readl(S3C2416_INTPND2);
852
853 if (pend == 0 || pend == last)
854 break;
855
856 __raw_writel(pend, S3C2416_SRCPND2);
857 __raw_writel(pend, S3C2416_INTPND2);
858 printk(KERN_INFO "irq: clearing pending status %08x\n",
859 (int)pend);
860 last = pend;
861 }
862
863 for (irqno = IRQ_S3C2416_2D; irqno <= IRQ_S3C2416_I2S1; irqno++) {
864 switch (irqno) {
865 case IRQ_S3C2416_RESERVED2:
866 case IRQ_S3C2416_RESERVED3:
867 /* no IRQ here */
868 break;
869 default:
870 irq_set_chip_and_handler(irqno, &s3c2416_irq_second,
871 handle_edge_irq);
872 set_irq_flags(irqno, IRQF_VALID);
873 }
874 }
875}
876
877static int s3c2416_irq_add(struct device *dev,
878 struct subsys_interface *sif)
879{
880 printk(KERN_INFO "S3C2416: IRQ Support\n");
881
882 s3c2416_add_sub(IRQ_LCD, s3c2416_irq_demux_lcd, &s3c2416_irq_lcd,
883 IRQ_S3C2443_LCD2, IRQ_S3C2443_LCD4);
884
885 s3c2416_add_sub(IRQ_S3C2443_DMA, s3c2416_irq_demux_dma,
886 &s3c2416_irq_dma, IRQ_S3C2443_DMA0, IRQ_S3C2443_DMA5);
887
888 s3c2416_add_sub(IRQ_S3C2443_UART3, s3c2416_irq_demux_uart3,
889 &s3c2416_irq_uart3,
890 IRQ_S3C2443_RX3, IRQ_S3C2443_ERR3);
891
892 s3c2416_add_sub(IRQ_WDT, s3c2416_irq_demux_wdtac97,
893 &s3c2416_irq_wdtac97,
894 IRQ_S3C2443_WDT, IRQ_S3C2443_AC97);
895
896 s3c2416_irq_add_second();
897
898 return 0;
899}
900
901static struct subsys_interface s3c2416_irq_interface = {
902 .name = "s3c2416_irq",
903 .subsys = &s3c2416_subsys,
904 .add_dev = s3c2416_irq_add,
905};
906
907static int __init s3c2416_irq_init(void)
908{
909 return subsys_interface_register(&s3c2416_irq_interface);
910}
911
912arch_initcall(s3c2416_irq_init);
913
914#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-04 03:09:09 -0500