IB/mlx5: Support IB_WR_REG_SIG_MR

This patch implements IB_WR_REG_SIG_MR posted by the user.

Baisically this WR involves 3 WQEs in order to prepare and properly
register the signature layout:

1. post UMR WR to register the sig_mr in one of two possible ways:
    * In case the user registered a single MR for data so the UMR data segment
      consists of:
      - single klm (data MR) passed by the user
      - BSF with signature attributes requested by the user.
    * In case the user registered 2 MRs, one for data and one for protection,
      the UMR consists of:
      - strided block format which includes data and protection MRs and
        their repetitive block format.
      - BSF with signature attributes requested by the user.

2. post SET_PSV in order to set the memory domain initial
   signature parameters passed by the user.
   SET_PSV is not signaled and solicited CQE.

3. post SET_PSV in order to set the wire domain initial
   signature parameters passed by the user.
   SET_PSV is not signaled and solicited CQE.

* After this compound WR we place a small fence for next WR to come.

This patch also introduces some helper functions to set the BSF correctly
and determining the signature format selectors.

Signed-off-by: Sagi Grimberg <sagig@mellanox.com>
Signed-off-by: Roland Dreier <roland@purestorage.com>

2 files changed, 483 insertions, 0 deletions

diff --git a/drivers/infiniband/hw/mlx5/qp.c b/drivers/infiniband/hw/mlx5/qp.c
index 1dbadbfc4474..67e79989b181 100644
--- a/drivers/infiniband/hw/mlx5/qp.c
+++ b/drivers/infiniband/hw/mlx5/qp.c
@@ -1777,6 +1777,26 @@ static __be64 frwr_mkey_mask(void)
         return cpu_to_be64(result);
 }
 
+static __be64 sig_mkey_mask(void)
+{
+        u64 result;
+
+        result = MLX5_MKEY_MASK_LEN             |
+                MLX5_MKEY_MASK_PAGE_SIZE        |
+                MLX5_MKEY_MASK_START_ADDR       |
+                MLX5_MKEY_MASK_EN_RINVAL        |
+                MLX5_MKEY_MASK_KEY              |
+                MLX5_MKEY_MASK_LR               |
+                MLX5_MKEY_MASK_LW               |
+                MLX5_MKEY_MASK_RR               |
+                MLX5_MKEY_MASK_RW               |
+                MLX5_MKEY_MASK_SMALL_FENCE      |
+                MLX5_MKEY_MASK_FREE             |
+                MLX5_MKEY_MASK_BSF_EN;
+
+        return cpu_to_be64(result);
+}
+
 static void set_frwr_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
                                  struct ib_send_wr *wr, int li)
 {
@@ -1961,6 +1981,339 @@ static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
         return 0;
 }
 
+static u16 prot_field_size(enum ib_signature_type type)
+{
+        switch (type) {
+        case IB_SIG_TYPE_T10_DIF:
+                return MLX5_DIF_SIZE;
+        default:
+                return 0;
+        }
+}
+
+static u8 bs_selector(int block_size)
+{
+        switch (block_size) {
+        case 512:           return 0x1;
+        case 520:           return 0x2;
+        case 4096:          return 0x3;
+        case 4160:          return 0x4;
+        case 1073741824:    return 0x5;
+        default:            return 0;
+        }
+}
+
+static int format_selector(struct ib_sig_attrs *attr,
+                           struct ib_sig_domain *domain,
+                           int *selector)
+{
+
+#define FORMAT_DIF_NONE         0
+#define FORMAT_DIF_CRC_INC      8
+#define FORMAT_DIF_CRC_NO_INC   12
+#define FORMAT_DIF_CSUM_INC     13
+#define FORMAT_DIF_CSUM_NO_INC  14
+
+        switch (domain->sig.dif.type) {
+        case IB_T10DIF_NONE:
+                /* No DIF */
+                *selector = FORMAT_DIF_NONE;
+                break;
+        case IB_T10DIF_TYPE1: /* Fall through */
+        case IB_T10DIF_TYPE2:
+                switch (domain->sig.dif.bg_type) {
+                case IB_T10DIF_CRC:
+                        *selector = FORMAT_DIF_CRC_INC;
+                        break;
+                case IB_T10DIF_CSUM:
+                        *selector = FORMAT_DIF_CSUM_INC;
+                        break;
+                default:
+                        return 1;
+                }
+                break;
+        case IB_T10DIF_TYPE3:
+                switch (domain->sig.dif.bg_type) {
+                case IB_T10DIF_CRC:
+                        *selector = domain->sig.dif.type3_inc_reftag ?
+                                           FORMAT_DIF_CRC_INC :
+                                           FORMAT_DIF_CRC_NO_INC;
+                        break;
+                case IB_T10DIF_CSUM:
+                        *selector = domain->sig.dif.type3_inc_reftag ?
+                                           FORMAT_DIF_CSUM_INC :
+                                           FORMAT_DIF_CSUM_NO_INC;
+                        break;
+                default:
+                        return 1;
+                }
+                break;
+        default:
+                return 1;
+        }
+
+        return 0;
+}
+
+static int mlx5_set_bsf(struct ib_mr *sig_mr,
+                        struct ib_sig_attrs *sig_attrs,
+                        struct mlx5_bsf *bsf, u32 data_size)
+{
+        struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
+        struct mlx5_bsf_basic *basic = &bsf->basic;
+        struct ib_sig_domain *mem = &sig_attrs->mem;
+        struct ib_sig_domain *wire = &sig_attrs->wire;
+        int ret, selector;
+
+        switch (sig_attrs->mem.sig_type) {
+        case IB_SIG_TYPE_T10_DIF:
+                if (sig_attrs->wire.sig_type != IB_SIG_TYPE_T10_DIF)
+                        return -EINVAL;
+
+                /* Input domain check byte mask */
+                basic->check_byte_mask = sig_attrs->check_mask;
+                if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
+                    mem->sig.dif.type == wire->sig.dif.type) {
+                        /* Same block structure */
+                        basic->bsf_size_sbs = 1 << 4;
+                        if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
+                                basic->wire.copy_byte_mask = 0xff;
+                        else
+                                basic->wire.copy_byte_mask = 0x3f;
+                } else
+                        basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
+
+                basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
+                basic->raw_data_size = cpu_to_be32(data_size);
+
+                ret = format_selector(sig_attrs, mem, &selector);
+                if (ret)
+                        return -EINVAL;
+                basic->m_bfs_psv = cpu_to_be32(selector << 24 |
+                                               msig->psv_memory.psv_idx);
+
+                ret = format_selector(sig_attrs, wire, &selector);
+                if (ret)
+                        return -EINVAL;
+                basic->w_bfs_psv = cpu_to_be32(selector << 24 |
+                                               msig->psv_wire.psv_idx);
+                break;
+
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
+static int set_sig_data_segment(struct ib_send_wr *wr, struct mlx5_ib_qp *qp,
+                                void **seg, int *size)
+{
+        struct ib_sig_attrs *sig_attrs = wr->wr.sig_handover.sig_attrs;
+        struct ib_mr *sig_mr = wr->wr.sig_handover.sig_mr;
+        struct mlx5_bsf *bsf;
+        u32 data_len = wr->sg_list->length;
+        u32 data_key = wr->sg_list->lkey;
+        u64 data_va = wr->sg_list->addr;
+        int ret;
+        int wqe_size;
+
+        if (!wr->wr.sig_handover.prot) {
+                /**
+                 * Source domain doesn't contain signature information
+                 * So need construct:
+                 *                  ------------------
+                 *                 |     data_klm     |
+                 *                  ------------------
+                 *                 |       BSF        |
+                 *                  ------------------
+                 **/
+                struct mlx5_klm *data_klm = *seg;
+