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authorJiang Liu <jiang.liu@huawei.com>2012-08-20 15:53:19 -0400
committerBjorn Helgaas <bhelgaas@google.com>2012-08-23 12:11:14 -0400
commite5c8ae5fcaadc7947ce3a8e0f82134e56fe4e15b (patch)
tree5e68d3907bad3b36d60615505361e12709dab448
parentc772b44e32ea8255e5d0ffaac0a7b76043b14565 (diff)
cxgb4: Use PCI Express Capability accessors
Use PCI Express Capability access functions to simplify cxgb4 driver. Signed-off-by: Jiang Liu <jiang.liu@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c10
-rw-r--r--drivers/net/ethernet/chelsio/cxgb4/t4_hw.c6
2 files changed, 3 insertions, 13 deletions
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index 5ed49af23d6a..4a20821511e7 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -3694,15 +3694,7 @@ static void __devinit print_port_info(const struct net_device *dev)
3694 3694
3695static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev) 3695static void __devinit enable_pcie_relaxed_ordering(struct pci_dev *dev)
3696{ 3696{
3697 u16 v; 3697 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
3698 int pos;
3699
3700 pos = pci_pcie_cap(dev);
3701 if (pos > 0) {
3702 pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &v);
3703 v |= PCI_EXP_DEVCTL_RELAX_EN;
3704 pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, v);
3705 }
3706} 3698}
3707 3699
3708/* 3700/*
diff --git a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
index fa947dfa4c30..af1601323173 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
@@ -2741,11 +2741,9 @@ static void __devinit get_pci_mode(struct adapter *adapter,
2741 struct pci_params *p) 2741 struct pci_params *p)
2742{ 2742{
2743 u16 val; 2743 u16 val;
2744 u32 pcie_cap = pci_pcie_cap(adapter->pdev);
2745 2744
2746 if (pcie_cap) { 2745 if (pci_is_pcie(adapter->pdev)) {
2747 pci_read_config_word(adapter->pdev, pcie_cap + PCI_EXP_LNKSTA, 2746 pcie_capability_read_word(adapter->pdev, PCI_EXP_LNKSTA, &val);
2748 &val);
2749 p->speed = val & PCI_EXP_LNKSTA_CLS; 2747 p->speed = val & PCI_EXP_LNKSTA_CLS;
2750 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4; 2748 p->width = (val & PCI_EXP_LNKSTA_NLW) >> 4;
2751 } 2749 }