diff options
author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2007-07-18 10:10:34 -0400 |
---|---|---|
committer | Greg Kroah-Hartman <gregkh@suse.de> | 2007-07-19 20:46:08 -0400 |
commit | e294531dc9f2c1f5291373dcdd5013c0cdcbdee2 (patch) | |
tree | 52c04cf3d53d67838b4811a89467184cca2958d1 | |
parent | 809a58b896ba07e771adc76a47c83e4ca1969da8 (diff) |
USB: r8a66597-hcd: fixes some problem
This patch incorporates some updates. Updates include:
- Fix the problem that control transfer might fail
- Change from GFP_KERNEL to GFP_ATOMIC
- Clean up some coding style issue
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r-- | drivers/usb/host/r8a66597-hcd.c | 110 | ||||
-rw-r--r-- | drivers/usb/host/r8a66597.h | 87 |
2 files changed, 96 insertions, 101 deletions
diff --git a/drivers/usb/host/r8a66597-hcd.c b/drivers/usb/host/r8a66597-hcd.c index a7a7070c6e2a..d60f1985320c 100644 --- a/drivers/usb/host/r8a66597-hcd.c +++ b/drivers/usb/host/r8a66597-hcd.c | |||
@@ -35,10 +35,8 @@ | |||
35 | #include <linux/interrupt.h> | 35 | #include <linux/interrupt.h> |
36 | #include <linux/usb.h> | 36 | #include <linux/usb.h> |
37 | #include <linux/platform_device.h> | 37 | #include <linux/platform_device.h> |
38 | 38 | #include <linux/io.h> | |
39 | #include <asm/io.h> | 39 | #include <linux/irq.h> |
40 | #include <asm/irq.h> | ||
41 | #include <asm/system.h> | ||
42 | 40 | ||
43 | #include "../core/hcd.h" | 41 | #include "../core/hcd.h" |
44 | #include "r8a66597.h" | 42 | #include "r8a66597.h" |
@@ -54,16 +52,21 @@ static const char hcd_name[] = "r8a66597_hcd"; | |||
54 | /* module parameters */ | 52 | /* module parameters */ |
55 | static unsigned short clock = XTAL12; | 53 | static unsigned short clock = XTAL12; |
56 | module_param(clock, ushort, 0644); | 54 | module_param(clock, ushort, 0644); |
57 | MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0(default=0)"); | 55 | MODULE_PARM_DESC(clock, "input clock: 48MHz=32768, 24MHz=16384, 12MHz=0 " |
56 | "(default=0)"); | ||
57 | |||
58 | static unsigned short vif = LDRV; | 58 | static unsigned short vif = LDRV; |
59 | module_param(vif, ushort, 0644); | 59 | module_param(vif, ushort, 0644); |
60 | MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)"); | 60 | MODULE_PARM_DESC(vif, "input VIF: 3.3V=32768, 1.5V=0(default=32768)"); |
61 | static unsigned short endian = 0; | 61 | |
62 | static unsigned short endian; | ||
62 | module_param(endian, ushort, 0644); | 63 | module_param(endian, ushort, 0644); |
63 | MODULE_PARM_DESC(endian, "data endian: big=256, little=0(default=0)"); | 64 | MODULE_PARM_DESC(endian, "data endian: big=256, little=0 (default=0)"); |
65 | |||
64 | static unsigned short irq_sense = INTL; | 66 | static unsigned short irq_sense = INTL; |
65 | module_param(irq_sense, ushort, 0644); | 67 | module_param(irq_sense, ushort, 0644); |
66 | MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0(default=32)"); | 68 | MODULE_PARM_DESC(irq_sense, "IRQ sense: low level=32, falling edge=0 " |
69 | "(default=32)"); | ||
67 | 70 | ||
68 | static void packet_write(struct r8a66597 *r8a66597, u16 pipenum); | 71 | static void packet_write(struct r8a66597 *r8a66597, u16 pipenum); |
69 | static int r8a66597_get_frame(struct usb_hcd *hcd); | 72 | static int r8a66597_get_frame(struct usb_hcd *hcd); |
@@ -308,7 +311,7 @@ static int make_r8a66597_device(struct r8a66597 *r8a66597, | |||
308 | struct r8a66597_device *dev; | 311 | struct r8a66597_device *dev; |
309 | int usb_address = urb->setup_packet[2]; /* urb->pipe is address 0 */ | 312 | int usb_address = urb->setup_packet[2]; /* urb->pipe is address 0 */ |
310 | 313 | ||
311 | dev = kzalloc(sizeof(struct r8a66597_device), GFP_KERNEL); | 314 | dev = kzalloc(sizeof(struct r8a66597_device), GFP_ATOMIC); |
312 | if (dev == NULL) | 315 | if (dev == NULL) |
313 | return -ENOMEM; | 316 | return -ENOMEM; |
314 | 317 | ||
@@ -611,33 +614,33 @@ static u16 get_empty_pipenum(struct r8a66597 *r8a66597, | |||
611 | u16 array[R8A66597_MAX_NUM_PIPE], i = 0, min; | 614 | u16 array[R8A66597_MAX_NUM_PIPE], i = 0, min; |
612 | 615 | ||
613 | memset(array, 0, sizeof(array)); | 616 | memset(array, 0, sizeof(array)); |
614 | switch(ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { | 617 | switch (ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) { |
615 | case USB_ENDPOINT_XFER_BULK: | 618 | case USB_ENDPOINT_XFER_BULK: |
616 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) | 619 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) |
617 | array[i++] = 4; | 620 | array[i++] = 4; |
618 | else { | 621 | else { |
619 | array[i++] = 3; | 622 | array[i++] = 3; |
620 | array[i++] = 5; | 623 | array[i++] = 5; |
621 | } | 624 | } |
622 | break; | 625 | break; |
623 | case USB_ENDPOINT_XFER_INT: | 626 | case USB_ENDPOINT_XFER_INT: |
624 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) { | 627 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) { |
625 | array[i++] = 6; | 628 | array[i++] = 6; |
626 | array[i++] = 7; | 629 | array[i++] = 7; |
627 | array[i++] = 8; | 630 | array[i++] = 8; |
628 | } else | 631 | } else |
629 | array[i++] = 9; | 632 | array[i++] = 9; |
630 | break; | 633 | break; |
631 | case USB_ENDPOINT_XFER_ISOC: | 634 | case USB_ENDPOINT_XFER_ISOC: |
632 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) | 635 | if (ep->bEndpointAddress & USB_ENDPOINT_DIR_MASK) |
633 | array[i++] = 2; | 636 | array[i++] = 2; |
634 | else | 637 | else |
635 | array[i++] = 1; | 638 | array[i++] = 1; |
636 | break; | 639 | break; |
637 | default: | 640 | default: |
638 | err("Illegal type"); | 641 | err("Illegal type"); |
639 | return 0; | 642 | return 0; |
640 | } | 643 | } |
641 | 644 | ||
642 | i = 1; | 645 | i = 1; |
643 | min = array[0]; | 646 | min = array[0]; |
@@ -654,7 +657,7 @@ static u16 get_r8a66597_type(__u8 type) | |||
654 | { | 657 | { |
655 | u16 r8a66597_type; | 658 | u16 r8a66597_type; |
656 | 659 | ||
657 | switch(type) { | 660 | switch (type) { |
658 | case USB_ENDPOINT_XFER_BULK: | 661 | case USB_ENDPOINT_XFER_BULK: |
659 | r8a66597_type = R8A66597_BULK; | 662 | r8a66597_type = R8A66597_BULK; |
660 | break; | 663 | break; |
@@ -874,7 +877,7 @@ static void r8a66597_usb_preconnect(struct r8a66597 *r8a66597, int port) | |||
874 | { | 877 | { |
875 | r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_CONNECTION) | 878 | r8a66597->root_hub[port].port |= (1 << USB_PORT_FEAT_CONNECTION) |
876 | | (1 << USB_PORT_FEAT_C_CONNECTION); | 879 | | (1 << USB_PORT_FEAT_C_CONNECTION); |
877 | r8a66597_write(r8a66597, (u16)~DTCH, get_intsts_reg(port)); | 880 | r8a66597_write(r8a66597, ~DTCH, get_intsts_reg(port)); |
878 | r8a66597_bset(r8a66597, DTCHE, get_intenb_reg(port)); | 881 | r8a66597_bset(r8a66597, DTCHE, get_intenb_reg(port)); |
879 | } | 882 | } |
880 | 883 | ||
@@ -917,7 +920,7 @@ static void prepare_setup_packet(struct r8a66597 *r8a66597, | |||
917 | 920 | ||
918 | r8a66597_write(r8a66597, make_devsel(td->address) | td->maxpacket, | 921 | r8a66597_write(r8a66597, make_devsel(td->address) | td->maxpacket, |
919 | DCPMAXP); | 922 | DCPMAXP); |
920 | r8a66597_write(r8a66597, (u16)~(SIGN | SACK), INTSTS1); | 923 | r8a66597_write(r8a66597, ~(SIGN | SACK), INTSTS1); |
921 | 924 | ||
922 | for (i = 0; i < 4; i++) { | 925 | for (i = 0; i < 4; i++) { |
923 | r8a66597_write(r8a66597, p[i], setup_addr); | 926 | r8a66597_write(r8a66597, p[i], setup_addr); |
@@ -948,19 +951,18 @@ static void prepare_packet_read(struct r8a66597 *r8a66597, | |||
948 | pipe_irq_disable(r8a66597, td->pipenum); | 951 | pipe_irq_disable(r8a66597, td->pipenum); |
949 | pipe_setting(r8a66597, td); | 952 | pipe_setting(r8a66597, td); |
950 | pipe_stop(r8a66597, td->pipe); | 953 | pipe_stop(r8a66597, td->pipe); |
951 | r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), | 954 | r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS); |
952 | BRDYSTS); | ||
953 | 955 | ||
954 | if (td->pipe->pipetre) { | 956 | if (td->pipe->pipetre) { |
955 | r8a66597_write(r8a66597, TRCLR, | 957 | r8a66597_write(r8a66597, TRCLR, |
956 | td->pipe->pipetre); | 958 | td->pipe->pipetre); |
957 | r8a66597_write(r8a66597, | 959 | r8a66597_write(r8a66597, |
958 | (urb->transfer_buffer_length | 960 | (urb->transfer_buffer_length |
959 | + td->maxpacket - 1) | 961 | + td->maxpacket - 1) |
960 | / td->maxpacket, | 962 | / td->maxpacket, |
961 | td->pipe->pipetrn); | 963 | td->pipe->pipetrn); |
962 | r8a66597_bset(r8a66597, TRENB, | 964 | r8a66597_bset(r8a66597, TRENB, |
963 | td->pipe->pipetre); | 965 | td->pipe->pipetre); |
964 | } | 966 | } |
965 | 967 | ||
966 | pipe_start(r8a66597, td->pipe); | 968 | pipe_start(r8a66597, td->pipe); |
@@ -991,7 +993,7 @@ static void prepare_packet_write(struct r8a66597 *r8a66597, | |||
991 | if (td->pipe->pipetre) | 993 | if (td->pipe->pipetre) |
992 | r8a66597_bclr(r8a66597, TRENB, td->pipe->pipetre); | 994 | r8a66597_bclr(r8a66597, TRENB, td->pipe->pipetre); |
993 | } | 995 | } |
994 | r8a66597_write(r8a66597, (u16)~(1 << td->pipenum), BRDYSTS); | 996 | r8a66597_write(r8a66597, ~(1 << td->pipenum), BRDYSTS); |
995 | 997 | ||
996 | fifo_change_from_pipe(r8a66597, td->pipe); | 998 | fifo_change_from_pipe(r8a66597, td->pipe); |
997 | tmp = r8a66597_read(r8a66597, td->pipe->fifoctr); | 999 | tmp = r8a66597_read(r8a66597, td->pipe->fifoctr); |
@@ -1009,21 +1011,21 @@ static void prepare_status_packet(struct r8a66597 *r8a66597, | |||
1009 | struct urb *urb = td->urb; | 1011 | struct urb *urb = td->urb; |
1010 | 1012 | ||
1011 | r8a66597_pipe_toggle(r8a66597, td->pipe, 1); | 1013 | r8a66597_pipe_toggle(r8a66597, td->pipe, 1); |
1014 | pipe_stop(r8a66597, td->pipe); | ||
1012 | 1015 | ||
1013 | if (urb->setup_packet[0] & USB_ENDPOINT_DIR_MASK) { | 1016 | if (urb->setup_packet[0] & USB_ENDPOINT_DIR_MASK) { |
1014 | r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG); | 1017 | r8a66597_bset(r8a66597, R8A66597_DIR, DCPCFG); |
1015 | r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL); | 1018 | r8a66597_mdfy(r8a66597, ISEL, ISEL | CURPIPE, CFIFOSEL); |
1016 | r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); | 1019 | r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); |
1017 | r8a66597_write(r8a66597, BVAL | BCLR, CFIFOCTR); | 1020 | r8a66597_write(r8a66597, ~BEMP0, BEMPSTS); |
1018 | r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS); | 1021 | r8a66597_write(r8a66597, BCLR, CFIFOCTR); |
1022 | r8a66597_write(r8a66597, BVAL, CFIFOCTR); | ||
1019 | enable_irq_empty(r8a66597, 0); | 1023 | enable_irq_empty(r8a66597, 0); |
1020 | } else { | 1024 | } else { |
1021 | r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG); | 1025 | r8a66597_bclr(r8a66597, R8A66597_DIR, DCPCFG); |
1022 | r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL); | 1026 | r8a66597_mdfy(r8a66597, 0, ISEL | CURPIPE, CFIFOSEL); |
1023 | r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); | 1027 | r8a66597_reg_wait(r8a66597, CFIFOSEL, CURPIPE, 0); |
1024 | r8a66597_write(r8a66597, BCLR, CFIFOCTR); | 1028 | r8a66597_write(r8a66597, BCLR, CFIFOCTR); |
1025 | r8a66597_write(r8a66597, (u16)~BRDY0, BRDYSTS); | ||
1026 | r8a66597_write(r8a66597, (u16)~BEMP0, BEMPSTS); | ||
1027 | enable_irq_ready(r8a66597, 0); | 1029 | enable_irq_ready(r8a66597, 0); |
1028 | } | 1030 | } |
1029 | enable_irq_nrdy(r8a66597, 0); | 1031 | enable_irq_nrdy(r8a66597, 0); |
@@ -1269,7 +1271,7 @@ static void packet_write(struct r8a66597 *r8a66597, u16 pipenum) | |||
1269 | 1271 | ||
1270 | /* write fifo */ | 1272 | /* write fifo */ |
1271 | if (pipenum > 0) | 1273 | if (pipenum > 0) |
1272 | r8a66597_write(r8a66597, (u16)~(1 << pipenum), BEMPSTS); | 1274 | r8a66597_write(r8a66597, ~(1 << pipenum), BEMPSTS); |
1273 | if (urb->transfer_buffer) { | 1275 | if (urb->transfer_buffer) { |
1274 | r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size); | 1276 | r8a66597_write_fifo(r8a66597, td->pipe->fifoaddr, buf, size); |
1275 | if (!usb_pipebulk(urb->pipe) || td->maxpacket != size) | 1277 | if (!usb_pipebulk(urb->pipe) || td->maxpacket != size) |
@@ -1362,7 +1364,7 @@ static void irq_pipe_ready(struct r8a66597 *r8a66597) | |||
1362 | 1364 | ||
1363 | mask = r8a66597_read(r8a66597, BRDYSTS) | 1365 | mask = r8a66597_read(r8a66597, BRDYSTS) |
1364 | & r8a66597_read(r8a66597, BRDYENB); | 1366 | & r8a66597_read(r8a66597, BRDYENB); |
1365 | r8a66597_write(r8a66597, (u16)~mask, BRDYSTS); | 1367 | r8a66597_write(r8a66597, ~mask, BRDYSTS); |
1366 | if (mask & BRDY0) { | 1368 | if (mask & BRDY0) { |
1367 | td = r8a66597_get_td(r8a66597, 0); | 1369 | td = r8a66597_get_td(r8a66597, 0); |
1368 | if (td && td->type == USB_PID_IN) | 1370 | if (td && td->type == USB_PID_IN) |
@@ -1397,7 +1399,7 @@ static void irq_pipe_empty(struct r8a66597 *r8a66597) | |||
1397 | 1399 | ||
1398 | mask = r8a66597_read(r8a66597, BEMPSTS) | 1400 | mask = r8a66597_read(r8a66597, BEMPSTS) |
1399 | & r8a66597_read(r8a66597, BEMPENB); | 1401 | & r8a66597_read(r8a66597, BEMPENB); |
1400 | r8a66597_write(r8a66597, (u16)~mask, BEMPSTS); | 1402 | r8a66597_write(r8a66597, ~mask, BEMPSTS); |
1401 | if (mask & BEMP0) { | 1403 | if (mask & BEMP0) { |
1402 | cfifo_change(r8a66597, 0); | 1404 | cfifo_change(r8a66597, 0); |
1403 | td = r8a66597_get_td(r8a66597, 0); | 1405 | td = r8a66597_get_td(r8a66597, 0); |
@@ -1434,7 +1436,7 @@ static void irq_pipe_nrdy(struct r8a66597 *r8a66597) | |||
1434 | 1436 | ||
1435 | mask = r8a66597_read(r8a66597, NRDYSTS) | 1437 | mask = r8a66597_read(r8a66597, NRDYSTS) |
1436 | & r8a66597_read(r8a66597, NRDYENB); | 1438 | & r8a66597_read(r8a66597, NRDYENB); |
1437 | r8a66597_write(r8a66597, (u16)~mask, NRDYSTS); | 1439 | r8a66597_write(r8a66597, ~mask, NRDYSTS); |
1438 | if (mask & NRDY0) { | 1440 | if (mask & NRDY0) { |
1439 | cfifo_change(r8a66597, 0); | 1441 | cfifo_change(r8a66597, 0); |
1440 | set_urb_error(r8a66597, 0); | 1442 | set_urb_error(r8a66597, 0); |
@@ -1488,14 +1490,14 @@ static irqreturn_t r8a66597_irq(struct usb_hcd *hcd) | |||
1488 | mask0 = intsts0 & intenb0 & (BEMP | NRDY | BRDY); | 1490 | mask0 = intsts0 & intenb0 & (BEMP | NRDY | BRDY); |
1489 | if (mask2) { | 1491 | if (mask2) { |
1490 | if (mask2 & ATTCH) { | 1492 | if (mask2 & ATTCH) { |
1491 | r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS2); | 1493 | r8a66597_write(r8a66597, ~ATTCH, INTSTS2); |
1492 | r8a66597_bclr(r8a66597, ATTCHE, INTENB2); | 1494 | r8a66597_bclr(r8a66597, ATTCHE, INTENB2); |
1493 | 1495 | ||
1494 | /* start usb bus sampling */ | 1496 | /* start usb bus sampling */ |
1495 | start_root_hub_sampling(r8a66597, 1); | 1497 | start_root_hub_sampling(r8a66597, 1); |
1496 | } | 1498 | } |
1497 | if (mask2 & DTCH) { | 1499 | if (mask2 & DTCH) { |
1498 | r8a66597_write(r8a66597, (u16)~DTCH, INTSTS2); | 1500 | r8a66597_write(r8a66597, ~DTCH, INTSTS2); |
1499 | r8a66597_bclr(r8a66597, DTCHE, INTENB2); | 1501 | r8a66597_bclr(r8a66597, DTCHE, INTENB2); |
1500 | r8a66597_usb_disconnect(r8a66597, 1); | 1502 | r8a66597_usb_disconnect(r8a66597, 1); |
1501 | } | 1503 | } |
@@ -1503,24 +1505,24 @@ static irqreturn_t r8a66597_irq(struct usb_hcd *hcd) | |||
1503 | 1505 | ||
1504 | if (mask1) { | 1506 | if (mask1) { |
1505 | if (mask1 & ATTCH) { | 1507 | if (mask1 & ATTCH) { |
1506 | r8a66597_write(r8a66597, (u16)~ATTCH, INTSTS1); | 1508 | r8a66597_write(r8a66597, ~ATTCH, INTSTS1); |
1507 | r8a66597_bclr(r8a66597, ATTCHE, INTENB1); | 1509 | r8a66597_bclr(r8a66597, ATTCHE, INTENB1); |
1508 | 1510 | ||
1509 | /* start usb bus sampling */ | 1511 | /* start usb bus sampling */ |
1510 | start_root_hub_sampling(r8a66597, 0); | 1512 | start_root_hub_sampling(r8a66597, 0); |
1511 | } | 1513 | } |
1512 | if (mask1 & DTCH) { | 1514 | if (mask1 & DTCH) { |
1513 | r8a66597_write(r8a66597, (u16)~DTCH, INTSTS1); | 1515 | r8a66597_write(r8a66597, ~DTCH, INTSTS1); |
1514 | r8a66597_bclr(r8a66597, DTCHE, INTENB1); | 1516 | r8a66597_bclr(r8a66597, DTCHE, INTENB1); |
1515 | r8a66597_usb_disconnect(r8a66597, 0); | 1517 | r8a66597_usb_disconnect(r8a66597, 0); |
1516 | } | 1518 | } |
1517 | if (mask1 & SIGN) { | 1519 | if (mask1 & SIGN) { |
1518 | r8a66597_write(r8a66597, (u16)~SIGN, INTSTS1); | 1520 | r8a66597_write(r8a66597, ~SIGN, INTSTS1); |
1519 | set_urb_error(r8a66597, 0); | 1521 | set_urb_error(r8a66597, 0); |
1520 | check_next_phase(r8a66597); | 1522 | check_next_phase(r8a66597); |
1521 | } | 1523 | } |
1522 | if (mask1 & SACK) { | 1524 | if (mask1 & SACK) { |
1523 | r8a66597_write(r8a66597, (u16)~SACK, INTSTS1); | 1525 | r8a66597_write(r8a66597, ~SACK, INTSTS1); |
1524 | check_next_phase(r8a66597); | 1526 | check_next_phase(r8a66597); |
1525 | } | 1527 | } |
1526 | } | 1528 | } |
@@ -1663,13 +1665,9 @@ static int check_pipe_config(struct r8a66597 *r8a66597, struct urb *urb) | |||
1663 | static int r8a66597_start(struct usb_hcd *hcd) | 1665 | static int r8a66597_start(struct usb_hcd *hcd) |
1664 | { | 1666 | { |
1665 | struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd); | 1667 | struct r8a66597 *r8a66597 = hcd_to_r8a66597(hcd); |
1666 | int ret; | ||
1667 | 1668 | ||
1668 | hcd->state = HC_STATE_RUNNING; | 1669 | hcd->state = HC_STATE_RUNNING; |
1669 | if ((ret = enable_controller(r8a66597)) < 0) | 1670 | return enable_controller(r8a66597); |
1670 | return ret; | ||
1671 | |||
1672 | return 0; | ||
1673 | } | 1671 | } |
1674 | 1672 | ||
1675 | static void r8a66597_stop(struct usb_hcd *hcd) | 1673 | static void r8a66597_stop(struct usb_hcd *hcd) |
@@ -1696,13 +1694,12 @@ static void set_address_zero(struct r8a66597 *r8a66597, struct urb *urb) | |||
1696 | 1694 | ||
1697 | static struct r8a66597_td *r8a66597_make_td(struct r8a66597 *r8a66597, | 1695 | static struct r8a66597_td *r8a66597_make_td(struct r8a66597 *r8a66597, |
1698 | struct urb *urb, | 1696 | struct urb *urb, |
1699 | struct usb_host_endpoint *hep, | 1697 | struct usb_host_endpoint *hep) |
1700 | gfp_t mem_flags) | ||
1701 | { | 1698 | { |
1702 | struct r8a66597_td *td; | 1699 | struct r8a66597_td *td; |
1703 | u16 pipenum; | 1700 | u16 pipenum; |
1704 | 1701 | ||
1705 | td = kzalloc(sizeof(struct r8a66597_td), mem_flags); | 1702 | td = kzalloc(sizeof(struct r8a66597_td), GFP_ATOMIC); |
1706 | if (td == NULL) | 1703 | if (td == NULL) |
1707 | return NULL; | 1704 | return NULL; |
1708 | 1705 | ||
@@ -1741,7 +1738,8 @@ static int r8a66597_urb_enqueue(struct usb_hcd *hcd, | |||
1741 | } | 1738 | } |
1742 | 1739 | ||
1743 | if (!hep->hcpriv) { | 1740 | if (!hep->hcpriv) { |
1744 | hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), mem_flags); | 1741 | hep->hcpriv = kzalloc(sizeof(struct r8a66597_pipe), |
1742 | GFP_ATOMIC); | ||
1745 | if (!hep->hcpriv) { | 1743 | if (!hep->hcpriv) { |
1746 | ret = -ENOMEM; | 1744 | ret = -ENOMEM; |
1747 | goto error; | 1745 | goto error; |
@@ -1755,7 +1753,7 @@ static int r8a66597_urb_enqueue(struct usb_hcd *hcd, | |||
1755 | init_pipe_config(r8a66597, urb); | 1753 | init_pipe_config(r8a66597, urb); |
1756 | 1754 | ||
1757 | set_address_zero(r8a66597, urb); | 1755 | set_address_zero(r8a66597, urb); |
1758 | td = r8a66597_make_td(r8a66597, urb, hep, mem_flags); | 1756 | td = r8a66597_make_td(r8a66597, urb, hep); |
1759 | if (td == NULL) { | 1757 | if (td == NULL) { |
1760 | ret = -ENOMEM; | 1758 | ret = -ENOMEM; |
1761 | goto error; | 1759 | goto error; |
diff --git a/drivers/usb/host/r8a66597.h b/drivers/usb/host/r8a66597.h index 97c2a71ac7a1..fe9ceb077d9b 100644 --- a/drivers/usb/host/r8a66597.h +++ b/drivers/usb/host/r8a66597.h | |||
@@ -203,14 +203,14 @@ | |||
203 | #define DTLN 0x0FFF /* b11-0: FIFO received data length */ | 203 | #define DTLN 0x0FFF /* b11-0: FIFO received data length */ |
204 | 204 | ||
205 | /* Interrupt Enable Register 0 */ | 205 | /* Interrupt Enable Register 0 */ |
206 | #define VBSE 0x8000 /* b15: VBUS interrupt */ | 206 | #define VBSE 0x8000 /* b15: VBUS interrupt */ |
207 | #define RSME 0x4000 /* b14: Resume interrupt */ | 207 | #define RSME 0x4000 /* b14: Resume interrupt */ |
208 | #define SOFE 0x2000 /* b13: Frame update interrupt */ | 208 | #define SOFE 0x2000 /* b13: Frame update interrupt */ |
209 | #define DVSE 0x1000 /* b12: Device state transition interrupt */ | 209 | #define DVSE 0x1000 /* b12: Device state transition interrupt */ |
210 | #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ | 210 | #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */ |
211 | #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ | 211 | #define BEMPE 0x0400 /* b10: Buffer empty interrupt */ |
212 | #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ | 212 | #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */ |
213 | #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ | 213 | #define BRDYE 0x0100 /* b8: Buffer ready interrupt */ |
214 | 214 | ||
215 | /* Interrupt Enable Register 1 */ | 215 | /* Interrupt Enable Register 1 */ |
216 | #define OVRCRE 0x8000 /* b15: Over-current interrupt */ | 216 | #define OVRCRE 0x8000 /* b15: Over-current interrupt */ |
@@ -268,16 +268,16 @@ | |||
268 | #define SOF_DISABLE 0x0000 /* SOF OUT Disable */ | 268 | #define SOF_DISABLE 0x0000 /* SOF OUT Disable */ |
269 | 269 | ||
270 | /* Interrupt Status Register 0 */ | 270 | /* Interrupt Status Register 0 */ |
271 | #define VBINT 0x8000 /* b15: VBUS interrupt */ | 271 | #define VBINT 0x8000 /* b15: VBUS interrupt */ |
272 | #define RESM 0x4000 /* b14: Resume interrupt */ | 272 | #define RESM 0x4000 /* b14: Resume interrupt */ |
273 | #define SOFR 0x2000 /* b13: SOF frame update interrupt */ | 273 | #define SOFR 0x2000 /* b13: SOF frame update interrupt */ |
274 | #define DVST 0x1000 /* b12: Device state transition interrupt */ | 274 | #define DVST 0x1000 /* b12: Device state transition interrupt */ |
275 | #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ | 275 | #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */ |
276 | #define BEMP 0x0400 /* b10: Buffer empty interrupt */ | 276 | #define BEMP 0x0400 /* b10: Buffer empty interrupt */ |
277 | #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ | 277 | #define NRDY 0x0200 /* b9: Buffer not ready interrupt */ |
278 | #define BRDY 0x0100 /* b8: Buffer ready interrupt */ | 278 | #define BRDY 0x0100 /* b8: Buffer ready interrupt */ |
279 | #define VBSTS 0x0080 /* b7: VBUS input port */ | 279 | #define VBSTS 0x0080 /* b7: VBUS input port */ |
280 | #define DVSQ 0x0070 /* b6-4: Device state */ | 280 | #define DVSQ 0x0070 /* b6-4: Device state */ |
281 | #define DS_SPD_CNFG 0x0070 /* Suspend Configured */ | 281 | #define DS_SPD_CNFG 0x0070 /* Suspend Configured */ |
282 | #define DS_SPD_ADDR 0x0060 /* Suspend Address */ | 282 | #define DS_SPD_ADDR 0x0060 /* Suspend Address */ |
283 | #define DS_SPD_DFLT 0x0050 /* Suspend Default */ | 283 | #define DS_SPD_DFLT 0x0050 /* Suspend Default */ |
@@ -315,13 +315,10 @@ | |||
315 | /* Micro Frame Number Register */ | 315 | /* Micro Frame Number Register */ |
316 | #define UFRNM 0x0007 /* b2-0: Micro frame number */ | 316 | #define UFRNM 0x0007 /* b2-0: Micro frame number */ |
317 | 317 | ||
318 | /* USB Address / Low Power Status Recovery Register */ | ||
319 | //#define USBADDR 0x007F /* b6-0: USB address */ | ||
320 | |||
321 | /* Default Control Pipe Maxpacket Size Register */ | 318 | /* Default Control Pipe Maxpacket Size Register */ |
322 | /* Pipe Maxpacket Size Register */ | 319 | /* Pipe Maxpacket Size Register */ |
323 | #define DEVSEL 0xF000 /* b15-14: Device address select */ | 320 | #define DEVSEL 0xF000 /* b15-14: Device address select */ |
324 | #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ | 321 | #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */ |
325 | 322 | ||
326 | /* Default Control Pipe Control Register */ | 323 | /* Default Control Pipe Control Register */ |
327 | #define BSTS 0x8000 /* b15: Buffer status */ | 324 | #define BSTS 0x8000 /* b15: Buffer status */ |
@@ -366,21 +363,21 @@ | |||
366 | #define MXPS 0x07FF /* b10-0: Maxpacket size */ | 363 | #define MXPS 0x07FF /* b10-0: Maxpacket size */ |
367 | 364 | ||
368 | /* Pipe Cycle Configuration Register */ | 365 | /* Pipe Cycle Configuration Register */ |
369 | #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ | 366 | #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */ |
370 | #define IITV 0x0007 /* b2-0: Isochronous interval */ | 367 | #define IITV 0x0007 /* b2-0: Isochronous interval */ |
371 | 368 | ||
372 | /* Pipex Control Register */ | 369 | /* Pipex Control Register */ |
373 | #define BSTS 0x8000 /* b15: Buffer status */ | 370 | #define BSTS 0x8000 /* b15: Buffer status */ |
374 | #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ | 371 | #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */ |
375 | #define CSCLR 0x2000 /* b13: complete-split status clear */ | 372 | #define CSCLR 0x2000 /* b13: complete-split status clear */ |
376 | #define CSSTS 0x1000 /* b12: complete-split status */ | 373 | #define CSSTS 0x1000 /* b12: complete-split status */ |
377 | #define ATREPM 0x0400 /* b10: Auto repeat mode */ | 374 | #define ATREPM 0x0400 /* b10: Auto repeat mode */ |
378 | #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ | 375 | #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */ |
379 | #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ | 376 | #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */ |
380 | #define SQSET 0x0080 /* b7: Sequence toggle bit set */ | 377 | #define SQSET 0x0080 /* b7: Sequence toggle bit set */ |
381 | #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ | 378 | #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */ |
382 | #define PBUSY 0x0020 /* b5: pipe busy */ | 379 | #define PBUSY 0x0020 /* b5: pipe busy */ |
383 | #define PID 0x0003 /* b1-0: Response PID */ | 380 | #define PID 0x0003 /* b1-0: Response PID */ |
384 | 381 | ||
385 | /* PIPExTRE */ | 382 | /* PIPExTRE */ |
386 | #define TRENB 0x0200 /* b9: Transaction counter enable */ | 383 | #define TRENB 0x0200 /* b9: Transaction counter enable */ |
@@ -407,15 +404,15 @@ | |||
407 | #define make_devsel(addr) (addr << 12) | 404 | #define make_devsel(addr) (addr << 12) |
408 | 405 | ||
409 | struct r8a66597_pipe_info { | 406 | struct r8a66597_pipe_info { |
410 | u16 pipenum; | 407 | u16 pipenum; |
411 | u16 address; /* R8A66597 HCD usb addres */ | 408 | u16 address; /* R8A66597 HCD usb addres */ |
412 | u16 epnum; | 409 | u16 epnum; |
413 | u16 maxpacket; | 410 | u16 maxpacket; |
414 | u16 type; | 411 | u16 type; |
415 | u16 bufnum; | 412 | u16 bufnum; |
416 | u16 buf_bsize; | 413 | u16 buf_bsize; |
417 | u16 interval; | 414 | u16 interval; |
418 | u16 dir_in; | 415 | u16 dir_in; |
419 | }; | 416 | }; |
420 | 417 | ||
421 | struct r8a66597_pipe { | 418 | struct r8a66597_pipe { |