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authorPaul Mackerras <paulus@samba.org>2014-01-08 05:25:27 -0500
committerAlexander Graf <agraf@suse.de>2014-01-27 10:01:11 -0500
commite0622bd9f2fccc8a801fa7aaf4fa6d7c728c3a78 (patch)
treeb6dc26f27461b4a62c8b016ad6ba6212c7ce06fe
parentaa31e843225769735b79795c955426c9479046a5 (diff)
KVM: PPC: Book3S HV: Handle new LPCR bits on POWER8
POWER8 has a bit in the LPCR to enable or disable the PURR and SPURR registers to count when in the guest. Set this bit. POWER8 has a field in the LPCR called AIL (Alternate Interrupt Location) which is used to enable relocation-on interrupts. Allow userspace to set this field. Signed-off-by: Paul Mackerras <paulus@samba.org> Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--arch/powerpc/include/asm/reg.h2
-rw-r--r--arch/powerpc/kvm/book3s_hv.c6
2 files changed, 8 insertions, 0 deletions
diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h
index 1248b40107ea..05ecb072540c 100644
--- a/arch/powerpc/include/asm/reg.h
+++ b/arch/powerpc/include/asm/reg.h
@@ -305,8 +305,10 @@
305#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */ 305#define LPCR_RMLS 0x1C000000 /* impl dependent rmo limit sel */
306#define LPCR_RMLS_SH (63-37) 306#define LPCR_RMLS_SH (63-37)
307#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */ 307#define LPCR_ILE 0x02000000 /* !HV irqs set MSR:LE */
308#define LPCR_AIL 0x01800000 /* Alternate interrupt location */
308#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */ 309#define LPCR_AIL_0 0x00000000 /* MMU off exception offset 0x0 */
309#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */ 310#define LPCR_AIL_3 0x01800000 /* MMU on exception offset 0xc00...4xxx */
311#define LPCR_ONL 0x00040000 /* online - PURR/SPURR count */
310#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */ 312#define LPCR_PECE 0x0001f000 /* powersave exit cause enable */
311#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */ 313#define LPCR_PECEDP 0x00010000 /* directed priv dbells cause exit */
312#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */ 314#define LPCR_PECEDH 0x00008000 /* directed hyp dbells cause exit */
diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c
index 1e9f4b45432b..d7f2ec6f1419 100644
--- a/arch/powerpc/kvm/book3s_hv.c
+++ b/arch/powerpc/kvm/book3s_hv.c
@@ -789,8 +789,11 @@ static void kvmppc_set_lpcr(struct kvm_vcpu *vcpu, u64 new_lpcr)
789 /* 789 /*
790 * Userspace can only modify DPFD (default prefetch depth), 790 * Userspace can only modify DPFD (default prefetch depth),
791 * ILE (interrupt little-endian) and TC (translation control). 791 * ILE (interrupt little-endian) and TC (translation control).
792 * On POWER8 userspace can also modify AIL (alt. interrupt loc.)
792 */ 793 */
793 mask = LPCR_DPFD | LPCR_ILE | LPCR_TC; 794 mask = LPCR_DPFD | LPCR_ILE | LPCR_TC;
795 if (cpu_has_feature(CPU_FTR_ARCH_207S))
796 mask |= LPCR_AIL;
794 vc->lpcr = (vc->lpcr & ~mask) | (new_lpcr & mask); 797 vc->lpcr = (vc->lpcr & ~mask) | (new_lpcr & mask);
795 spin_unlock(&vc->lock); 798 spin_unlock(&vc->lock);
796} 799}
@@ -2166,6 +2169,9 @@ static int kvmppc_core_init_vm_hv(struct kvm *kvm)
2166 LPCR_VPM0 | LPCR_VPM1; 2169 LPCR_VPM0 | LPCR_VPM1;
2167 kvm->arch.vrma_slb_v = SLB_VSID_B_1T | 2170 kvm->arch.vrma_slb_v = SLB_VSID_B_1T |
2168 (VRMA_VSID << SLB_VSID_SHIFT_1T); 2171 (VRMA_VSID << SLB_VSID_SHIFT_1T);
2172 /* On POWER8 turn on online bit to enable PURR/SPURR */
2173 if (cpu_has_feature(CPU_FTR_ARCH_207S))
2174 lpcr |= LPCR_ONL;
2169 } 2175 }
2170 kvm->arch.lpcr = lpcr; 2176 kvm->arch.lpcr = lpcr;
2171 2177