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authorMohit Kumar <mohit.kumar@st.com>2014-02-19 07:04:35 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-02-19 16:47:13 -0500
commitdbffdd6862e67d60703f2df66c558bf448f81d6e (patch)
tree37daa414bf6e1d4b81f2b0eeee64e2bfca0a7425
parent38dbfb59d1175ef458d006556061adeaa8751b72 (diff)
PCI: designware: Fix RC BAR to be single 64-bit non-prefetchable memory BAR
The Synopsys PCIe core provides one pair of 32-bit BARs (BAR 0 and BAR 1). The BARs can be configured as follows: - One 64-bit BAR: BARs 0 and 1 are combined to form a single 64-bit BAR - Two 32-bit BARs: BARs 0 and 1 are two independent 32-bit BARs This patch corrects 64-bit, non-prefetchable memory BAR configuration implemented in dw driver. Signed-off-by: Mohit Kumar <mohit.kumar@st.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Pratyush Anand <pratyush.anand@st.com> Cc: Jingoo Han <jg1.han@samsung.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: stable@vger.kernel.org # v3.12+
-rw-r--r--drivers/pci/host/pcie-designware.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 17ce88f79d2b..6d23d8c893cd 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -800,7 +800,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
800 800
801 /* setup RC BARs */ 801 /* setup RC BARs */
802 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0); 802 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
803 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1); 803 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
804 804
805 /* setup interrupt pins */ 805 /* setup interrupt pins */
806 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val); 806 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);