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authorKukjin Kim <kgene.kim@samsung.com>2013-01-02 13:47:40 -0500
committerKukjin Kim <kgene.kim@samsung.com>2013-01-10 13:45:37 -0500
commitdb8304edee3f94d8a912cd2419f7ce787e8308da (patch)
treecbccba2eccde1c8a60de2567414b3c3850fa2ca1
parent0afdff5d3017806cdb509330c421907d2271a3d5 (diff)
ARM: S3C24XX: make vr1000-cpld.h, vr1000-irq.h and vr1000-map.h local
The headers can be local in mach-s3c24xx/. Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h18
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h26
-rw-r--r--arch/arm/mach-s3c24xx/include/mach/vr1000-map.h108
-rw-r--r--arch/arm/mach-s3c24xx/mach-vr1000.c33
-rw-r--r--arch/arm/mach-s3c24xx/vr1000.h118
5 files changed, 133 insertions, 170 deletions
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
deleted file mode 100644
index e4119913d7c5..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-cpld.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
2 *
3 * Copyright (c) 2003 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * VR1000 - CPLD control constants
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000CPLD_H
14#define __ASM_ARCH_VR1000CPLD_H
15
16#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
17
18#endif /* __ASM_ARCH_VR1000CPLD_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
deleted file mode 100644
index 47add133b8ee..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-irq.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-irq.h
2 *
3 * Copyright (c) 2003-2004 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - IRQ Number definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_VR1000IRQ_H
14#define __ASM_ARCH_VR1000IRQ_H
15
16/* irq numbers to onboard peripherals */
17
18#define IRQ_USBOC IRQ_EINT19
19#define IRQ_IDE0 IRQ_EINT16
20#define IRQ_IDE1 IRQ_EINT17
21#define IRQ_VR1000_SERIAL IRQ_EINT12
22#define IRQ_VR1000_DM9000A IRQ_EINT10
23#define IRQ_VR1000_DM9000N IRQ_EINT9
24#define IRQ_SMALERT IRQ_EINT8
25
26#endif /* __ASM_ARCH_VR1000IRQ_H */
diff --git a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h b/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
deleted file mode 100644
index 5f836a73cda3..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/vr1000-map.h
+++ /dev/null
@@ -1,108 +0,0 @@
1/* arch/arm/mach-s3c2410/include/mach/vr1000-map.h
2 *
3 * Copyright (c) 2003-2005 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
5 *
6 * Machine VR1000 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13/* needs arch/map.h including with this */
14
15/* ok, we've used up to 0x13000000, now we need to find space for the
16 * peripherals that live in the nGCS[x] areas, which are quite numerous
17 * in their space. We also have the board's CPLD to find register space
18 * for.
19 */
20
21#ifndef __ASM_ARCH_VR1000MAP_H
22#define __ASM_ARCH_VR1000MAP_H
23
24#define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
25
26/* we put the CPLD registers next, to get them out of the way */
27
28#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
29#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
30
31#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
32#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
33
34#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
35#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
36
37#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
38#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
39
40/* next, we have the PC104 ISA interrupt registers */
41
42#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
43#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
44
45#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
46#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
47
48#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
49#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
50
51/* 0xE0000000 contains the IO space that is split by speed and
52 * whether the access is for 8 or 16bit IO... this ensures that
53 * the correct access is made
54 *
55 * 0x10000000 of space, partitioned as so:
56 *
57 * 0x00000000 to 0x04000000 8bit, slow
58 * 0x04000000 to 0x08000000 16bit, slow
59 * 0x08000000 to 0x0C000000 16bit, net
60 * 0x0C000000 to 0x10000000 16bit, fast
61 *
62 * each of these spaces has the following in:
63 *
64 * 0x02000000 to 0x02100000 1MB IDE primary channel
65 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
66 * 0x02200000 to 0x02400000 1MB IDE secondary channel
67 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
68 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
69 * 0x02600000 to 0x02700000 1MB
70 *
71 * the phyiscal layout of the zones are:
72 * nGCS2 - 8bit, slow
73 * nGCS3 - 16bit, slow
74 * nGCS4 - 16bit, net
75 * nGCS5 - 16bit, fast
76 */
77
78#define VR1000_VA_MULTISPACE (0xE0000000)
79
80#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
81#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
82#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
83#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
84#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
85#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
86#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
87#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
88#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
89
90/* physical offset addresses for the peripherals */
91
92#define VR1000_PA_IDEPRI (0x02000000)
93#define VR1000_PA_IDEPRIAUX (0x02800000)
94#define VR1000_PA_IDESEC (0x03000000)
95#define VR1000_PA_IDESECAUX (0x03800000)
96#define VR1000_PA_DM9000 (0x05000000)
97
98#define VR1000_PA_SERIAL (0x11800000)
99#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
100
101/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
102#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
103
104/* some configurations for the peripherals */
105
106#define VR1000_DM9000_CS VR1000_VAM_CS4
107
108#endif /* __ASM_ARCH_VR1000MAP_H */
diff --git a/arch/arm/mach-s3c24xx/mach-vr1000.c b/arch/arm/mach-s3c24xx/mach-vr1000.c
index 80cffbffb826..d4db3853ae79 100644
--- a/arch/arm/mach-s3c24xx/mach-vr1000.c
+++ b/arch/arm/mach-s3c24xx/mach-vr1000.c
@@ -1,5 +1,4 @@
1/* linux/arch/arm/mach-s3c2410/mach-vr1000.c 1/*
2 *
3 * Copyright (c) 2003-2008 Simtec Electronics 2 * Copyright (c) 2003-2008 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk> 3 * Ben Dooks <ben@simtec.co.uk>
5 * 4 *
@@ -32,27 +31,25 @@
32#include <asm/mach/map.h> 31#include <asm/mach/map.h>
33#include <asm/mach/irq.h> 32#include <asm/mach/irq.h>
34 33
35#include <mach/vr1000-map.h>
36#include <mach/vr1000-irq.h>
37#include <mach/vr1000-cpld.h>
38
39#include <mach/hardware.h>
40#include <asm/irq.h> 34#include <asm/irq.h>
41#include <asm/mach-types.h> 35#include <asm/mach-types.h>
42 36
43#include <plat/regs-serial.h>
44#include <mach/regs-gpio.h>
45#include <linux/platform_data/leds-s3c24xx.h> 37#include <linux/platform_data/leds-s3c24xx.h>
38#include <linux/platform_data/i2c-s3c2410.h>
39#include <linux/platform_data/asoc-s3c24xx_simtec.h>
40
41#include <mach/hardware.h>
42#include <mach/regs-gpio.h>
46 43
47#include <plat/clock.h> 44#include <plat/clock.h>
48#include <plat/devs.h>
49#include <plat/cpu.h> 45#include <plat/cpu.h>
50#include <linux/platform_data/i2c-s3c2410.h> 46#include <plat/devs.h>
51#include <linux/platform_data/asoc-s3c24xx_simtec.h> 47#include <plat/regs-serial.h>
52 48
53#include "bast.h" 49#include "bast.h"
54#include "common.h" 50#include "common.h"
55#include "simtec.h" 51#include "simtec.h"
52#include "vr1000.h"
56 53
57/* macros for virtual address mods for the io space entries */ 54/* macros for virtual address mods for the io space entries */
58#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5) 55#define VA_C5(item) ((unsigned long)(item) + BAST_VAM_CS5)
@@ -143,7 +140,7 @@ static struct s3c2410_uartcfg vr1000_uartcfgs[] __initdata = {
143static struct plat_serial8250_port serial_platform_data[] = { 140static struct plat_serial8250_port serial_platform_data[] = {
144 [0] = { 141 [0] = {
145 .mapbase = VR1000_SERIAL_MAPBASE(0), 142 .mapbase = VR1000_SERIAL_MAPBASE(0),
146 .irq = IRQ_VR1000_SERIAL + 0, 143 .irq = VR1000_IRQ_SERIAL + 0,
147 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 144 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
148 .iotype = UPIO_MEM, 145 .iotype = UPIO_MEM,
149 .regshift = 0, 146 .regshift = 0,
@@ -151,7 +148,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
151 }, 148 },
152 [1] = { 149 [1] = {
153 .mapbase = VR1000_SERIAL_MAPBASE(1), 150 .mapbase = VR1000_SERIAL_MAPBASE(1),
154 .irq = IRQ_VR1000_SERIAL + 1, 151 .irq = VR1000_IRQ_SERIAL + 1,
155 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 152 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
156 .iotype = UPIO_MEM, 153 .iotype = UPIO_MEM,
157 .regshift = 0, 154 .regshift = 0,
@@ -159,7 +156,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
159 }, 156 },
160 [2] = { 157 [2] = {
161 .mapbase = VR1000_SERIAL_MAPBASE(2), 158 .mapbase = VR1000_SERIAL_MAPBASE(2),
162 .irq = IRQ_VR1000_SERIAL + 2, 159 .irq = VR1000_IRQ_SERIAL + 2,
163 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 160 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
164 .iotype = UPIO_MEM, 161 .iotype = UPIO_MEM,
165 .regshift = 0, 162 .regshift = 0,
@@ -167,7 +164,7 @@ static struct plat_serial8250_port serial_platform_data[] = {
167 }, 164 },
168 [3] = { 165 [3] = {
169 .mapbase = VR1000_SERIAL_MAPBASE(3), 166 .mapbase = VR1000_SERIAL_MAPBASE(3),
170 .irq = IRQ_VR1000_SERIAL + 3, 167 .irq = VR1000_IRQ_SERIAL + 3,
171 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP, 168 .flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP,
172 .iotype = UPIO_MEM, 169 .iotype = UPIO_MEM,
173 .regshift = 0, 170 .regshift = 0,
@@ -189,14 +186,14 @@ static struct platform_device serial_device = {
189static struct resource vr1000_dm9k0_resource[] = { 186static struct resource vr1000_dm9k0_resource[] = {
190 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4), 187 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000, 4),
191 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40), 188 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x40, 0x40),
192 [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000A, 1, NULL, IORESOURCE_IRQ \ 189 [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000A, 1, NULL, IORESOURCE_IRQ \
193 | IORESOURCE_IRQ_HIGHLEVEL), 190 | IORESOURCE_IRQ_HIGHLEVEL),
194}; 191};
195 192
196static struct resource vr1000_dm9k1_resource[] = { 193static struct resource vr1000_dm9k1_resource[] = {
197 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4), 194 [0] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0x80, 4),
198 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40), 195 [1] = DEFINE_RES_MEM(S3C2410_CS5 + VR1000_PA_DM9000 + 0xC0, 0x40),
199 [2] = DEFINE_RES_NAMED(IRQ_VR1000_DM9000N, 1, NULL, IORESOURCE_IRQ \ 196 [2] = DEFINE_RES_NAMED(VR1000_IRQ_DM9000N, 1, NULL, IORESOURCE_IRQ \
200 | IORESOURCE_IRQ_HIGHLEVEL), 197 | IORESOURCE_IRQ_HIGHLEVEL),
201}; 198};
202 199
diff --git a/arch/arm/mach-s3c24xx/vr1000.h b/arch/arm/mach-s3c24xx/vr1000.h
new file mode 100644
index 000000000000..7fcd2c2f183c
--- /dev/null
+++ b/arch/arm/mach-s3c24xx/vr1000.h
@@ -0,0 +1,118 @@
1
2/* arch/arm/mach-s3c2410/include/mach/vr1000-cpld.h
3 *
4 * Copyright (c) 2003 Simtec Electronics
5 * Ben Dooks <ben@simtec.co.uk>
6 *
7 * VR1000 - CPLD control constants
8 * Machine VR1000 - IRQ Number definitions
9 * Machine VR1000 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __MACH_S3C24XX_VR1000_H
17#define __MACH_S3C24XX_VR1000_H __FILE__
18
19#define VR1000_CPLD_CTRL2_RAMWEN (0x04) /* SRAM Write Enable */
20
21/* irq numbers to onboard peripherals */
22
23#define VR1000_IRQ_USBOC IRQ_EINT19
24#define VR1000_IRQ_IDE0 IRQ_EINT16
25#define VR1000_IRQ_IDE1 IRQ_EINT17
26#define VR1000_IRQ_SERIAL IRQ_EINT12
27#define VR1000_IRQ_DM9000A IRQ_EINT10
28#define VR1000_IRQ_DM9000N IRQ_EINT9
29#define VR1000_IRQ_SMALERT IRQ_EINT8
30
31/* map */
32
33#define VR1000_IOADDR(x) (S3C2410_ADDR((x) + 0x01300000))
34
35/* we put the CPLD registers next, to get them out of the way */
36
37#define VR1000_VA_CTRL1 VR1000_IOADDR(0x00000000) /* 0x01300000 */
38#define VR1000_PA_CTRL1 (S3C2410_CS5 | 0x7800000)
39
40#define VR1000_VA_CTRL2 VR1000_IOADDR(0x00100000) /* 0x01400000 */
41#define VR1000_PA_CTRL2 (S3C2410_CS1 | 0x6000000)
42
43#define VR1000_VA_CTRL3 VR1000_IOADDR(0x00200000) /* 0x01500000 */
44#define VR1000_PA_CTRL3 (S3C2410_CS1 | 0x6800000)
45
46#define VR1000_VA_CTRL4 VR1000_IOADDR(0x00300000) /* 0x01600000 */
47#define VR1000_PA_CTRL4 (S3C2410_CS1 | 0x7000000)
48
49/* next, we have the PC104 ISA interrupt registers */
50
51#define VR1000_PA_PC104_IRQREQ (S3C2410_CS5 | 0x6000000) /* 0x01700000 */
52#define VR1000_VA_PC104_IRQREQ VR1000_IOADDR(0x00400000)
53
54#define VR1000_PA_PC104_IRQRAW (S3C2410_CS5 | 0x6800000) /* 0x01800000 */
55#define VR1000_VA_PC104_IRQRAW VR1000_IOADDR(0x00500000)
56
57#define VR1000_PA_PC104_IRQMASK (S3C2410_CS5 | 0x7000000) /* 0x01900000 */
58#define VR1000_VA_PC104_IRQMASK VR1000_IOADDR(0x00600000)
59
60/*
61 * 0xE0000000 contains the IO space that is split by speed and
62 * whether the access is for 8 or 16bit IO... this ensures that
63 * the correct access is made
64 *
65 * 0x10000000 of space, partitioned as so:
66 *
67 * 0x00000000 to 0x04000000 8bit, slow
68 * 0x04000000 to 0x08000000 16bit, slow
69 * 0x08000000 to 0x0C000000 16bit, net
70 * 0x0C000000 to 0x10000000 16bit, fast
71 *
72 * each of these spaces has the following in:
73 *
74 * 0x02000000 to 0x02100000 1MB IDE primary channel
75 * 0x02100000 to 0x02200000 1MB IDE primary channel aux
76 * 0x02200000 to 0x02400000 1MB IDE secondary channel
77 * 0x02300000 to 0x02400000 1MB IDE secondary channel aux
78 * 0x02500000 to 0x02600000 1MB Davicom DM9000 ethernet controllers
79 * 0x02600000 to 0x02700000 1MB
80 *
81 * the phyiscal layout of the zones are:
82 * nGCS2 - 8bit, slow
83 * nGCS3 - 16bit, slow
84 * nGCS4 - 16bit, net
85 * nGCS5 - 16bit, fast
86 */
87
88#define VR1000_VA_MULTISPACE (0xE0000000)
89
90#define VR1000_VA_ISAIO (VR1000_VA_MULTISPACE + 0x00000000)
91#define VR1000_VA_ISAMEM (VR1000_VA_MULTISPACE + 0x01000000)
92#define VR1000_VA_IDEPRI (VR1000_VA_MULTISPACE + 0x02000000)
93#define VR1000_VA_IDEPRIAUX (VR1000_VA_MULTISPACE + 0x02100000)
94#define VR1000_VA_IDESEC (VR1000_VA_MULTISPACE + 0x02200000)
95#define VR1000_VA_IDESECAUX (VR1000_VA_MULTISPACE + 0x02300000)
96#define VR1000_VA_ASIXNET (VR1000_VA_MULTISPACE + 0x02400000)
97#define VR1000_VA_DM9000 (VR1000_VA_MULTISPACE + 0x02500000)
98#define VR1000_VA_SUPERIO (VR1000_VA_MULTISPACE + 0x02600000)
99
100/* physical offset addresses for the peripherals */
101
102#define VR1000_PA_IDEPRI (0x02000000)
103#define VR1000_PA_IDEPRIAUX (0x02800000)
104#define VR1000_PA_IDESEC (0x03000000)
105#define VR1000_PA_IDESECAUX (0x03800000)
106#define VR1000_PA_DM9000 (0x05000000)
107
108#define VR1000_PA_SERIAL (0x11800000)
109#define VR1000_VA_SERIAL (VR1000_IOADDR(0x00700000))
110
111/* VR1000 ram is in CS1, with A26..A24 = 2_101 */
112#define VR1000_PA_SRAM (S3C2410_CS1 | 0x05000000)
113
114/* some configurations for the peripherals */
115
116#define VR1000_DM9000_CS VR1000_VAM_CS4
117
118#endif /* __MACH_S3C24XX_VR1000_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-21 01:01:43 -0400