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authorOlof Johansson <olof@lixom.net>2014-07-13 00:20:47 -0400
committerOlof Johansson <olof@lixom.net>2014-07-13 00:20:47 -0400
commitdb6d842b8443ebac7b7b37264f992ce49dfb5208 (patch)
tree302e771043ca9fda2a5f7dc50cc54f26faa2d441
parentc3df51333444b7404a5b62f3e96f7a5d5b4fd2db (diff)
parentf86e0add813a3cc0e338089fa6c0928f5f6dc52d (diff)
Merge tag 's5p-cleanup-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
Merge "Samsung cleanup 2nd version for S5P SoCs for 3.17" from Kukjin Kim: Cleanup S5P SoCs for 3.17 - removing s5p64x0 SoCs and s5pc100 SoC in mainline because no more user and if it is required next time, it will be supported with DT. * tag 's5p-cleanup-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: video: fbdev: s3c-fb: remove s5pc100 related fimd and fb codes mtd: onenand: remove s5pc100 related onenand codes spi: s3c64xx: remove s5pc100 related spi codes gpio: samsung: remov s5pc100 related gpio codes ARM: S5PC100: no more support S5PC100 SoC video: fbdev: s3c-fb: remove s5p64x0 related fimd codes spi: s3c64xx: remove s5p64x0 related spi codes gpio: samsung: remove s5p64x0 related gpio codes ARM: S5P64X0: no more support S5P6440 and S5P6450 SoCs Signed-off-by: Olof Johansson <olof@lixom.net>
Diffstat
-rw-r--r--Documentation/arm/Samsung/Overview.txt11
-rwxr-xr-xDocumentation/arm/Samsung/clksrc-change-registers.awk1
-rw-r--r--Documentation/devicetree/bindings/spi/spi-samsung.txt1
-rw-r--r--Documentation/devicetree/bindings/video/samsung-fimd.txt2
-rw-r--r--arch/arm/Kconfig43
-rw-r--r--arch/arm/Makefile2
-rw-r--r--arch/arm/configs/s5p64x0_defconfig68
-rw-r--r--arch/arm/configs/s5pc100_defconfig49
-rw-r--r--arch/arm/mach-s5p64x0/Kconfig102
-rw-r--r--arch/arm/mach-s5p64x0/Makefile36
-rw-r--r--arch/arm/mach-s5p64x0/Makefile.boot2
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6440.c632
-rw-r--r--arch/arm/mach-s5p64x0/clock-s5p6450.c701
-rw-r--r--arch/arm/mach-s5p64x0/clock.c236
-rw-r--r--arch/arm/mach-s5p64x0/clock.h38
-rw-r--r--arch/arm/mach-s5p64x0/common.c490
-rw-r--r--arch/arm/mach-s5p64x0/common.h56
-rw-r--r--arch/arm/mach-s5p64x0/dev-audio.c176
-rw-r--r--arch/arm/mach-s5p64x0/dma.c128
-rw-r--r--arch/arm/mach-s5p64x0/i2c.h16
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/debug-macro.S32
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/gpio.h132
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/hardware.h18
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/irqs.h148
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/map.h96
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/pm-core.h119
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-clock.h98
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-gpio.h68
-rw-r--r--arch/arm/mach-s5p64x0/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5p64x0/irq-pm.c98
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6440.c280
-rw-r--r--arch/arm/mach-s5p64x0/mach-smdk6450.c299
-rw-r--r--arch/arm/mach-s5p64x0/pm.c202
-rw-r--r--arch/arm/mach-s5p64x0/setup-fb-24bpp.c29
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c0.c38
-rw-r--r--arch/arm/mach-s5p64x0/setup-i2c1.c38
-rw-r--r--arch/arm/mach-s5p64x0/setup-sdhci-gpio.c104
-rw-r--r--arch/arm/mach-s5p64x0/setup-spi.c38
-rw-r--r--arch/arm/mach-s5pc100/Kconfig81
-rw-r--r--arch/arm/mach-s5pc100/Makefile32
-rw-r--r--arch/arm/mach-s5pc100/Makefile.boot2
-rw-r--r--arch/arm/mach-s5pc100/clock.c1361
-rw-r--r--arch/arm/mach-s5pc100/common.c255
-rw-r--r--arch/arm/mach-s5pc100/common.h30
-rw-r--r--arch/arm/mach-s5pc100/dev-audio.c239
-rw-r--r--arch/arm/mach-s5pc100/dma.c130
-rw-r--r--arch/arm/mach-s5pc100/include/mach/debug-macro.S39
-rw-r--r--arch/arm/mach-s5pc100/include/mach/dma.h26
-rw-r--r--arch/arm/mach-s5pc100/include/mach/entry-macro.S19
-rw-r--r--arch/arm/mach-s5pc100/include/mach/gpio.h144
-rw-r--r--arch/arm/mach-s5pc100/include/mach/hardware.h14
-rw-r--r--arch/arm/mach-s5pc100/include/mach/irqs.h115
-rw-r--r--arch/arm/mach-s5pc100/include/mach/map.h137
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-clock.h80
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-gpio.h38
-rw-r--r--arch/arm/mach-s5pc100/include/mach/regs-irq.h18
-rw-r--r--arch/arm/mach-s5pc100/mach-smdkc100.c264
-rw-r--r--arch/arm/mach-s5pc100/setup-fb-24bpp.c35
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c0.c28
-rw-r--r--arch/arm/mach-s5pc100/setup-i2c1.c28
-rw-r--r--arch/arm/mach-s5pc100/setup-ide.c57
-rw-r--r--arch/arm/mach-s5pc100/setup-keypad.c23
-rw-r--r--arch/arm/mach-s5pc100/setup-sdhci-gpio.c70
-rw-r--r--arch/arm/mach-s5pc100/setup-spi.c41
-rw-r--r--arch/arm/plat-samsung/Kconfig14
-rw-r--r--arch/arm/plat-samsung/adc.c2
-rw-r--r--arch/arm/plat-samsung/include/plat/cpu.h29
-rw-r--r--arch/arm/plat-samsung/include/plat/devs.h17
-rw-r--r--arch/arm/plat-samsung/include/plat/fb.h14
-rw-r--r--arch/arm/plat-samsung/include/plat/s5p-clock.h2
-rw-r--r--arch/arm/plat-samsung/include/plat/sdhci.h77
-rw-r--r--drivers/gpio/gpio-samsung.c722
-rw-r--r--drivers/irqchip/Kconfig1
-rw-r--r--drivers/mtd/onenand/Kconfig4
-rw-r--r--drivers/mtd/onenand/samsung.c25
-rw-r--r--drivers/spi/spi-s3c64xx.c22
-rw-r--r--drivers/video/fbdev/Kconfig4
-rw-r--r--drivers/video/fbdev/s3c-fb.c65
-rw-r--r--include/video/samsung_fimd.h2
80 files changed, 15 insertions, 8962 deletions
diff --git a/Documentation/arm/Samsung/Overview.txt b/Documentation/arm/Samsung/Overview.txt
index 658abb258cef..8f7309bad460 100644
--- a/Documentation/arm/Samsung/Overview.txt
+++ b/Documentation/arm/Samsung/Overview.txt
@@ -13,8 +13,6 @@ Introduction
13 13
14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list 14 - S3C24XX: See Documentation/arm/Samsung-S3C24XX/Overview.txt for full list
15 - S3C64XX: S3C6400 and S3C6410 15 - S3C64XX: S3C6400 and S3C6410
16 - S5P6440
17 - S5PC100
18 - S5PC110 / S5PV210 16 - S5PC110 / S5PV210
19 17
20 18
@@ -34,8 +32,6 @@ Configuration
34 A number of configurations are supplied, as there is no current way of 32 A number of configurations are supplied, as there is no current way of
35 unifying all the SoCs into one kernel. 33 unifying all the SoCs into one kernel.
36 34
37 s5p6440_defconfig - S5P6440 specific default configuration
38 s5pc100_defconfig - S5PC100 specific default configuration
39 s5pc110_defconfig - S5PC110 specific default configuration 35 s5pc110_defconfig - S5PC110 specific default configuration
40 s5pv210_defconfig - S5PV210 specific default configuration 36 s5pv210_defconfig - S5PV210 specific default configuration
41 37
@@ -67,13 +63,6 @@ Layout changes
67 where to simplify the include and dependency issues involved with having 63 where to simplify the include and dependency issues involved with having
68 so many different platform directories. 64 so many different platform directories.
69 65
70 It was decided to remove plat-s5pc1xx as some of the support was already
71 in plat-s5p or plat-samsung, with the S5PC110 support added with S5PV210
72 the only user was the S5PC100. The S5PC100 specific items where moved to
73 arch/arm/mach-s5pc100.
74
75
76
77 66
78Port Contributors 67Port Contributors
79----------------- 68-----------------
diff --git a/Documentation/arm/Samsung/clksrc-change-registers.awk b/Documentation/arm/Samsung/clksrc-change-registers.awk
index 0c50220851fb..d9174fabe37e 100755
--- a/Documentation/arm/Samsung/clksrc-change-registers.awk
+++ b/Documentation/arm/Samsung/clksrc-change-registers.awk
@@ -68,7 +68,6 @@ BEGIN {
68 68
69 while (getline line < ARGV[1] > 0) { 69 while (getline line < ARGV[1] > 0) {
70 if (line ~ /\#define.*_MASK/ && 70 if (line ~ /\#define.*_MASK/ &&
71 !(line ~ /S5PC100_EPLL_MASK/) &&
72 !(line ~ /USB_SIG_MASK/)) { 71 !(line ~ /USB_SIG_MASK/)) {
73 splitdefine(line, fields) 72 splitdefine(line, fields)
74 name = fields[0] 73 name = fields[0]
diff --git a/Documentation/devicetree/bindings/spi/spi-samsung.txt b/Documentation/devicetree/bindings/spi/spi-samsung.txt
index 86aa061f069f..fe6f9037b561 100644
--- a/Documentation/devicetree/bindings/spi/spi-samsung.txt
+++ b/Documentation/devicetree/bindings/spi/spi-samsung.txt
@@ -8,7 +8,6 @@ Required SoC Specific Properties:
8- compatible: should be one of the following. 8- compatible: should be one of the following.
9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms 9 - samsung,s3c2443-spi: for s3c2443, s3c2416 and s3c2450 platforms
10 - samsung,s3c6410-spi: for s3c6410 platforms 10 - samsung,s3c6410-spi: for s3c6410 platforms
11 - samsung,s5p6440-spi: for s5p6440 and s5p6450 platforms
12 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms 11 - samsung,s5pv210-spi: for s5pv210 and s5pc110 platforms
13 - samsung,exynos4210-spi: for exynos4 and exynos5 platforms 12 - samsung,exynos4210-spi: for exynos4 and exynos5 platforms
14 13
diff --git a/Documentation/devicetree/bindings/video/samsung-fimd.txt b/Documentation/devicetree/bindings/video/samsung-fimd.txt
index 2dad41b689af..77942607f77f 100644
--- a/Documentation/devicetree/bindings/video/samsung-fimd.txt
+++ b/Documentation/devicetree/bindings/video/samsung-fimd.txt
@@ -8,8 +8,6 @@ Required properties:
8- compatible: value should be one of the following 8- compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */ 9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */ 10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5p6440-fimd"; /* for S5P64X0 SoCs */
12 "samsung,s5pc100-fimd"; /* for S5PC100 SoC */
13 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */ 11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
14 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */ 12 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
15 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */ 13 "samsung,exynos5250-fimd"; /* for Exynos5 SoCs */
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 06aab1024305..ea73acc1280d 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -757,42 +757,6 @@ config ARCH_S3C64XX
757 help 757 help
758 Samsung S3C64XX series based systems 758 Samsung S3C64XX series based systems
759 759
760config ARCH_S5P64X0
761 bool "Samsung S5P6440 S5P6450"
762 select ATAGS
763 select CLKDEV_LOOKUP
764 select CLKSRC_SAMSUNG_PWM
765 select CPU_V6
766 select GENERIC_CLOCKEVENTS
767 select GPIO_SAMSUNG
768 select HAVE_S3C2410_I2C if I2C
769 select HAVE_S3C2410_WATCHDOG if WATCHDOG
770 select HAVE_S3C_RTC if RTC_CLASS
771 select NEED_MACH_GPIO_H
772 select SAMSUNG_ATAGS
773 select SAMSUNG_WDT_RESET
774 help
775 Samsung S5P64X0 CPU based systems, such as the Samsung SMDK6440,
776 SMDK6450.
777
778config ARCH_S5PC100
779 bool "Samsung S5PC100"
780 select ARCH_REQUIRE_GPIOLIB
781 select ATAGS
782 select CLKDEV_LOOKUP
783 select CLKSRC_SAMSUNG_PWM
784 select CPU_V7
785 select GENERIC_CLOCKEVENTS
786 select GPIO_SAMSUNG
787 select HAVE_S3C2410_I2C if I2C
788 select HAVE_S3C2410_WATCHDOG if WATCHDOG
789 select HAVE_S3C_RTC if RTC_CLASS
790 select NEED_MACH_GPIO_H
791 select SAMSUNG_ATAGS
792 select SAMSUNG_WDT_RESET
793 help
794 Samsung S5PC100 series based systems
795
796config ARCH_S5PV210 760config ARCH_S5PV210
797 bool "Samsung S5PV210/S5PC110" 761 bool "Samsung S5PV210/S5PC110"
798 select ARCH_HAS_HOLES_MEMORYMODEL 762 select ARCH_HAS_HOLES_MEMORYMODEL
@@ -1003,10 +967,6 @@ source "arch/arm/mach-s3c24xx/Kconfig"
1003 967
1004source "arch/arm/mach-s3c64xx/Kconfig" 968source "arch/arm/mach-s3c64xx/Kconfig"
1005 969
1006source "arch/arm/mach-s5p64x0/Kconfig"
1007
1008source "arch/arm/mach-s5pc100/Kconfig"
1009
1010source "arch/arm/mach-s5pv210/Kconfig" 970source "arch/arm/mach-s5pv210/Kconfig"
1011 971
1012source "arch/arm/mach-exynos/Kconfig" 972source "arch/arm/mach-exynos/Kconfig"
@@ -1568,7 +1528,7 @@ source kernel/Kconfig.preempt
1568 1528
1569config HZ_FIXED 1529config HZ_FIXED
1570 int 1530 int
1571 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || ARCH_S5P64X0 || \ 1531 default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1572 ARCH_S5PV210 || ARCH_EXYNOS4 1532 ARCH_S5PV210 || ARCH_EXYNOS4
1573 default AT91_TIMER_HZ if ARCH_AT91 1533 default AT91_TIMER_HZ if ARCH_AT91
1574 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY 1534 default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
@@ -2193,7 +2153,6 @@ menu "Power management options"
2193source "kernel/power/Kconfig" 2153source "kernel/power/Kconfig"
2194 2154
2195config ARCH_SUSPEND_POSSIBLE 2155config ARCH_SUSPEND_POSSIBLE
2196 depends on !ARCH_S5PC100
2197 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \ 2156 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2198 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK 2157 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2199 def_bool y 2158 def_bool y
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 6721fab13734..d3f470c2201b 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -187,8 +187,6 @@ machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
187machine-$(CONFIG_ARCH_RPC) += rpc 187machine-$(CONFIG_ARCH_RPC) += rpc
188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx 188machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx 189machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
190machine-$(CONFIG_ARCH_S5P64X0) += s5p64x0
191machine-$(CONFIG_ARCH_S5PC100) += s5pc100
192machine-$(CONFIG_ARCH_S5PV210) += s5pv210 190machine-$(CONFIG_ARCH_S5PV210) += s5pv210
193machine-$(CONFIG_ARCH_SA1100) += sa1100 191machine-$(CONFIG_ARCH_SA1100) += sa1100
194machine-$(CONFIG_ARCH_SHMOBILE) += shmobile 192machine-$(CONFIG_ARCH_SHMOBILE) += shmobile
diff --git a/arch/arm/configs/s5p64x0_defconfig b/arch/arm/configs/s5p64x0_defconfig
deleted file mode 100644
index ad6b61b0bd11..000000000000
--- a/arch/arm/configs/s5p64x0_defconfig
+++ /dev/null
@@ -1,68 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSFS_DEPRECATED_V2=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5P64X0=y
9CONFIG_S3C_BOOT_ERROR_RESET=y
10CONFIG_S3C_LOWLEVEL_UART_PORT=1
11CONFIG_MACH_SMDK6440=y
12CONFIG_MACH_SMDK6450=y
13CONFIG_NO_HZ=y
14CONFIG_HIGH_RES_TIMERS=y
15CONFIG_CPU_32v6K=y
16CONFIG_AEABI=y
17CONFIG_CMDLINE="root=/dev/ram0 rw ramdisk=8192 initrd=0x20800000,8M console=ttySAC1,115200 init=/linuxrc"
18CONFIG_FPE_NWFPE=y
19CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
20# CONFIG_PREVENT_FIRMWARE_BUILD is not set
21CONFIG_BLK_DEV_RAM=y
22CONFIG_BLK_DEV_RAM_SIZE=8192
23# CONFIG_MISC_DEVICES is not set
24CONFIG_SCSI=y
25CONFIG_BLK_DEV_SD=y
26CONFIG_CHR_DEV_SG=y
27CONFIG_INPUT_EVDEV=y
28CONFIG_INPUT_TOUCHSCREEN=y
29CONFIG_SERIAL_8250=y
30CONFIG_SERIAL_8250_NR_UARTS=3
31CONFIG_SERIAL_SAMSUNG=y
32CONFIG_SERIAL_SAMSUNG_CONSOLE=y
33CONFIG_HW_RANDOM=y
34# CONFIG_HWMON is not set
35CONFIG_DISPLAY_SUPPORT=y
36# CONFIG_VGA_CONSOLE is not set
37# CONFIG_HID_SUPPORT is not set
38# CONFIG_USB_SUPPORT is not set
39CONFIG_EXT2_FS=y
40CONFIG_EXT3_FS=y
41CONFIG_EXT3_FS_POSIX_ACL=y
42CONFIG_EXT3_FS_SECURITY=y
43CONFIG_INOTIFY=y
44CONFIG_MSDOS_FS=y
45CONFIG_VFAT_FS=y
46CONFIG_TMPFS=y
47CONFIG_TMPFS_POSIX_ACL=y
48CONFIG_CRAMFS=y
49CONFIG_ROMFS_FS=y
50CONFIG_NLS_CODEPAGE_437=y
51CONFIG_NLS_ASCII=y
52CONFIG_NLS_ISO8859_1=y
53CONFIG_MAGIC_SYSRQ=y
54CONFIG_DEBUG_KERNEL=y
55CONFIG_DEBUG_RT_MUTEXES=y
56CONFIG_DEBUG_SPINLOCK=y
57CONFIG_DEBUG_MUTEXES=y
58CONFIG_DEBUG_SPINLOCK_SLEEP=y
59CONFIG_DEBUG_INFO=y
60# CONFIG_RCU_CPU_STALL_DETECTOR is not set
61CONFIG_SYSCTL_SYSCALL_CHECK=y
62CONFIG_DEBUG_USER=y
63CONFIG_DEBUG_ERRORS=y
64CONFIG_DEBUG_LL=y
65CONFIG_DEBUG_S3C_UART=1
66CONFIG_CRYPTO=y
67# CONFIG_CRYPTO_ANSI_CPRNG is not set
68CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/s5pc100_defconfig b/arch/arm/configs/s5pc100_defconfig
deleted file mode 100644
index 41bafc94dd85..000000000000
--- a/arch/arm/configs/s5pc100_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSFS_DEPRECATED_V2=y
3CONFIG_BLK_DEV_INITRD=y
4CONFIG_KALLSYMS_ALL=y
5CONFIG_MODULES=y
6CONFIG_MODULE_UNLOAD=y
7# CONFIG_BLK_DEV_BSG is not set
8CONFIG_ARCH_S5PC100=y
9CONFIG_MACH_SMDKC100=y
10CONFIG_AEABI=y
11CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M"
12CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
13CONFIG_BLK_DEV_LOOP=y
14CONFIG_BLK_DEV_RAM=y
15CONFIG_BLK_DEV_RAM_SIZE=8192
16CONFIG_EEPROM_AT24=y
17CONFIG_SERIAL_8250=y
18CONFIG_SERIAL_SAMSUNG=y
19CONFIG_SERIAL_SAMSUNG_CONSOLE=y
20CONFIG_HW_RANDOM=y
21CONFIG_I2C=y
22CONFIG_I2C_CHARDEV=y
23# CONFIG_VGA_CONSOLE is not set
24CONFIG_MMC=y
25CONFIG_MMC_DEBUG=y
26CONFIG_MMC_UNSAFE_RESUME=y
27CONFIG_SDIO_UART=y
28CONFIG_MMC_SDHCI=y
29CONFIG_EXT2_FS=y
30CONFIG_EXT3_FS=y
31CONFIG_EXT3_FS_POSIX_ACL=y
32CONFIG_EXT3_FS_SECURITY=y
33CONFIG_INOTIFY=y
34CONFIG_TMPFS=y
35CONFIG_TMPFS_POSIX_ACL=y
36CONFIG_CRAMFS=y
37CONFIG_ROMFS_FS=y
38CONFIG_MAGIC_SYSRQ=y
39CONFIG_DEBUG_KERNEL=y
40CONFIG_DEBUG_RT_MUTEXES=y
41CONFIG_DEBUG_SPINLOCK=y
42CONFIG_DEBUG_MUTEXES=y
43CONFIG_DEBUG_SPINLOCK_SLEEP=y
44CONFIG_DEBUG_INFO=y
45# CONFIG_RCU_CPU_STALL_DETECTOR is not set
46CONFIG_SYSCTL_SYSCALL_CHECK=y
47CONFIG_DEBUG_USER=y
48CONFIG_DEBUG_ERRORS=y
49CONFIG_DEBUG_LL=y
diff --git a/arch/arm/mach-s5p64x0/Kconfig b/arch/arm/mach-s5p64x0/Kconfig
deleted file mode 100644
index 26003e23796d..000000000000
--- a/arch/arm/mach-s5p64x0/Kconfig
+++ /dev/null
@@ -1,102 +0,0 @@
1# arch/arm/mach-s5p64x0/Kconfig
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com/
5#
6# Licensed under GPLv2
7
8if ARCH_S5P64X0
9
10config CPU_S5P6440
11 bool
12 select ARM_AMBA
13 select PL330_DMA if DMADEVICES
14 select S5P_SLEEP if PM
15 select SAMSUNG_WAKEMASK if PM
16 help
17 Enable S5P6440 CPU support
18
19config CPU_S5P6450
20 bool
21 select ARM_AMBA
22 select PL330_DMA if DMADEVICES
23 select S5P_SLEEP if PM
24 select SAMSUNG_WAKEMASK if PM
25 help
26 Enable S5P6450 CPU support
27
28config S5P64X0_SETUP_FB_24BPP
29 bool
30 help
31 Common setup code for S5P64X0 based boards with a LCD display
32 through RGB interface.
33
34config S5P64X0_SETUP_I2C1
35 bool
36 help
37 Common setup code for i2c bus 1.
38
39config S5P64X0_SETUP_SPI
40 bool
41 help
42 Common setup code for SPI GPIO configurations
43
44config S5P64X0_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
49# machine support
50
51config MACH_SMDK6440
52 bool "SMDK6440"
53 select CPU_S5P6440
54 select S3C_DEV_FB
55 select S3C_DEV_HSMMC
56 select S3C_DEV_HSMMC1
57 select S3C_DEV_HSMMC2
58 select S3C_DEV_I2C1
59 select S3C_DEV_RTC
60 select S3C_DEV_WDT
61 select S5P64X0_SETUP_FB_24BPP
62 select S5P64X0_SETUP_I2C1
63 select S5P64X0_SETUP_SDHCI_GPIO
64 select SAMSUNG_DEV_ADC
65 select SAMSUNG_DEV_BACKLIGHT
66 select SAMSUNG_DEV_PWM
67 select SAMSUNG_DEV_TS
68 help
69 Machine support for the Samsung SMDK6440
70
71config MACH_SMDK6450
72 bool "SMDK6450"
73 select CPU_S5P6450
74 select S3C_DEV_FB
75 select S3C_DEV_HSMMC
76 select S3C_DEV_HSMMC1
77 select S3C_DEV_HSMMC2
78 select S3C_DEV_I2C1
79 select S3C_DEV_RTC
80 select S3C_DEV_WDT
81 select S5P64X0_SETUP_FB_24BPP
82 select S5P64X0_SETUP_I2C1
83 select S5P64X0_SETUP_SDHCI_GPIO
84 select SAMSUNG_DEV_ADC
85 select SAMSUNG_DEV_BACKLIGHT
86 select SAMSUNG_DEV_PWM
87 select SAMSUNG_DEV_TS
88 help
89 Machine support for the Samsung SMDK6450
90
91menu "Use 8-bit SDHCI bus width"
92
93config S5P64X0_SD_CH1_8BIT
94 bool "SDHCI Channel 1 (Slot 1)"
95 depends on MACH_SMDK6450 || MACH_SMDK6440
96 help
97 Support SDHCI Channel 1 8-bit bus.
98 If selected, Channel 2 is disabled.
99
100endmenu
101
102endif
diff --git a/arch/arm/mach-s5p64x0/Makefile b/arch/arm/mach-s5p64x0/Makefile
deleted file mode 100644
index 12bb951187a4..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile
+++ /dev/null
@@ -1,36 +0,0 @@
1# arch/arm/mach-s5p64x0/Makefile
2#
3# Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4# http://www.samsung.com
5#
6# Licensed under GPLv2
7
8obj-y :=
9obj-m :=
10obj-n :=
11obj- :=
12
13# Core
14
15obj-y += common.o clock.o
16obj-$(CONFIG_CPU_S5P6440) += clock-s5p6440.o
17obj-$(CONFIG_CPU_S5P6450) += clock-s5p6450.o
18
19obj-$(CONFIG_PM) += pm.o irq-pm.o
20
21obj-y += dma.o
22
23# machine support
24
25obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
26obj-$(CONFIG_MACH_SMDK6450) += mach-smdk6450.o
27
28# device support
29
30obj-y += dev-audio.o
31
32obj-y += setup-i2c0.o
33obj-$(CONFIG_S5P64X0_SETUP_I2C1) += setup-i2c1.o
34obj-$(CONFIG_S5P64X0_SETUP_FB_24BPP) += setup-fb-24bpp.o
35obj-$(CONFIG_S5P64X0_SETUP_SPI) += setup-spi.o
36obj-$(CONFIG_S5P64X0_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
diff --git a/arch/arm/mach-s5p64x0/Makefile.boot b/arch/arm/mach-s5p64x0/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5p64x0/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6440.c b/arch/arm/mach-s5p64x0/clock-s5p6440.c
deleted file mode 100644
index ae34a1d5e10a..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6440.c
+++ /dev/null
@@ -1,632 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6440 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "clock.h"
35#include "common.h"
36
37static u32 epll_div[][5] = {
38 { 36000000, 0, 48, 1, 4 },
39 { 48000000, 0, 32, 1, 3 },
40 { 60000000, 0, 40, 1, 3 },
41 { 72000000, 0, 48, 1, 3 },
42 { 84000000, 0, 28, 1, 2 },
43 { 96000000, 0, 32, 1, 2 },
44 { 32768000, 45264, 43, 1, 4 },
45 { 45158000, 6903, 30, 1, 3 },
46 { 49152000, 50332, 32, 1, 3 },
47 { 67738000, 10398, 45, 1, 3 },
48 { 73728000, 9961, 49, 1, 3 }
49};
50
51static int s5p6440_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
84 clk->rate, rate);
85
86 clk->rate = rate;
87
88 return 0;
89}
90
91static struct clk_ops s5p6440_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6440_epll_set_rate,
94};
95
96static struct clksrc_clk clk_hclk = {
97 .clk = {
98 .name = "clk_hclk",
99 .parent = &clk_armclk.clk,
100 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
102};
103
104static struct clksrc_clk clk_pclk = {
105 .clk = {
106 .name = "clk_pclk",
107 .parent = &clk_hclk.clk,
108 },
109 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
110};
111static struct clksrc_clk clk_hclk_low = {
112 .clk = {
113 .name = "clk_hclk_low",
114 },
115 .sources = &clkset_hclk_low,
116 .reg_src = { .reg = S5P64X0_SYS_OTHERS, .shift = 6, .size = 1 },
117 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
118};
119
120static struct clksrc_clk clk_pclk_low = {
121 .clk = {
122 .name = "clk_pclk_low",
123 .parent = &clk_hclk_low.clk,
124 },
125 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
126};
127
128/*
129 * The following clocks will be disabled during clock initialization. It is
130 * recommended to keep the following clocks disabled until the driver requests
131 * for enabling the clock.
132 */
133static struct clk init_clocks_off[] = {
134 {
135 .name = "nand",
136 .parent = &clk_hclk.clk,
137 .enable = s5p64x0_mem_ctrl,
138 .ctrlbit = (1 << 2),
139 }, {
140 .name = "post",
141 .parent = &clk_hclk_low.clk,
142 .enable = s5p64x0_hclk0_ctrl,
143 .ctrlbit = (1 << 5)
144 }, {
145 .name = "2d",
146 .parent = &clk_hclk.clk,
147 .enable = s5p64x0_hclk0_ctrl,
148 .ctrlbit = (1 << 8),
149 }, {
150 .name = "dma",
151 .devname = "dma-pl330",
152 .parent = &clk_hclk_low.clk,
153 .enable = s5p64x0_hclk0_ctrl,
154 .ctrlbit = (1 << 12),
155 }, {
156 .name = "hsmmc",
157 .devname = "s3c-sdhci.0",
158 .parent = &clk_hclk_low.clk,
159 .enable = s5p64x0_hclk0_ctrl,
160 .ctrlbit = (1 << 17),
161 }, {
162 .name = "hsmmc",
163 .devname = "s3c-sdhci.1",
164 .parent = &clk_hclk_low.clk,
165 .enable = s5p64x0_hclk0_ctrl,
166 .ctrlbit = (1 << 18),
167 }, {
168 .name = "hsmmc",
169 .devname = "s3c-sdhci.2",
170 .parent = &clk_hclk_low.clk,
171 .enable = s5p64x0_hclk0_ctrl,
172 .ctrlbit = (1 << 19),
173 }, {
174 .name = "otg",
175 .parent = &clk_hclk_low.clk,
176 .enable = s5p64x0_hclk0_ctrl,
177 .ctrlbit = (1 << 20)
178 }, {
179 .name = "irom",
180 .parent = &clk_hclk.clk,
181 .enable = s5p64x0_hclk0_ctrl,
182 .ctrlbit = (1 << 25),
183 }, {
184 .name = "lcd",
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk1_ctrl,
187 .ctrlbit = (1 << 1),
188 }, {
189 .name = "hclk_fimgvg",
190 .parent = &clk_hclk.clk,
191 .enable = s5p64x0_hclk1_ctrl,
192 .ctrlbit = (1 << 2),
193 }, {
194 .name = "tsi",
195 .parent = &clk_hclk_low.clk,
196 .enable = s5p64x0_hclk1_ctrl,
197 .ctrlbit = (1 << 0),
198 }, {
199 .name = "watchdog",
200 .parent = &clk_pclk_low.clk,
201 .enable = s5p64x0_pclk_ctrl,
202 .ctrlbit = (1 << 5),
203 }, {
204 .name = "rtc",
205 .parent = &clk_pclk_low.clk,
206 .enable = s5p64x0_pclk_ctrl,
207 .ctrlbit = (1 << 6),
208 }, {
209 .name = "timers",
210 .parent = &clk_pclk_low.clk,
211 .enable = s5p64x0_pclk_ctrl,
212 .ctrlbit = (1 << 7),
213 }, {
214 .name = "pcm",
215 .parent = &clk_pclk_low.clk,
216 .enable = s5p64x0_pclk_ctrl,
217 .ctrlbit = (1 << 8),
218 }, {
219 .name = "adc",
220 .parent = &clk_pclk_low.clk,
221 .enable = s5p64x0_pclk_ctrl,
222 .ctrlbit = (1 << 12),
223 }, {
224 .name = "i2c",
225 .parent = &clk_pclk_low.clk,
226 .enable = s5p64x0_pclk_ctrl,
227 .ctrlbit = (1 << 17),
228 }, {
229 .name = "spi",
230 .devname = "s5p64x0-spi.0",
231 .parent = &clk_pclk_low.clk,
232 .enable = s5p64x0_pclk_ctrl,
233 .ctrlbit = (1 << 21),
234 }, {
235 .name = "spi",
236 .devname = "s5p64x0-spi.1",
237 .parent = &clk_pclk_low.clk,
238 .enable = s5p64x0_pclk_ctrl,
239 .ctrlbit = (1 << 22),
240 }, {
241 .name = "gps",
242 .parent = &clk_pclk_low.clk,
243 .enable = s5p64x0_pclk_ctrl,
244 .ctrlbit = (1 << 25),
245 }, {
246 .name = "dsim",
247 .parent = &clk_pclk_low.clk,
248 .enable = s5p64x0_pclk_ctrl,
249 .ctrlbit = (1 << 28),
250 }, {
251 .name = "etm",
252 .parent = &clk_pclk.clk,
253 .enable = s5p64x0_pclk_ctrl,
254 .ctrlbit = (1 << 29),
255 }, {
256 .name = "dmc0",
257 .parent = &clk_pclk.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 30),
260 }, {
261 .name = "pclk_fimgvg",
262 .parent = &clk_pclk.clk,
263 .enable = s5p64x0_pclk_ctrl,
264 .ctrlbit = (1 << 31),
265 }, {
266 .name = "mmc_48m",
267 .devname = "s3c-sdhci.0",
268 .parent = &clk_48m,
269 .enable = s5p64x0_sclk_ctrl,
270 .ctrlbit = (1 << 27),
271 }, {
272 .name = "mmc_48m",
273 .devname = "s3c-sdhci.1",
274 .parent = &clk_48m,
275 .enable = s5p64x0_sclk_ctrl,
276 .ctrlbit = (1 << 28),
277 }, {
278 .name = "mmc_48m",
279 .devname = "s3c-sdhci.2",
280 .parent = &clk_48m,
281 .enable = s5p64x0_sclk_ctrl,
282 .ctrlbit = (1 << 29),
283 },
284};
285
286/*
287 * The following clocks will be enabled during clock initialization.
288 */
289static struct clk init_clocks[] = {
290 {
291 .name = "intc",
292 .parent = &clk_hclk.clk,
293 .enable = s5p64x0_hclk0_ctrl,
294 .ctrlbit = (1 << 1),
295 }, {
296 .name = "mem",
297 .parent = &clk_hclk.clk,
298 .enable = s5p64x0_hclk0_ctrl,
299 .ctrlbit = (1 << 21),
300 }, {
301 .name = "uart",
302 .devname = "s3c6400-uart.0",
303 .parent = &clk_pclk_low.clk,
304 .enable = s5p64x0_pclk_ctrl,
305 .ctrlbit = (1 << 1),
306 }, {
307 .name = "uart",
308 .devname = "s3c6400-uart.1",
309 .parent = &clk_pclk_low.clk,
310 .enable = s5p64x0_pclk_ctrl,
311 .ctrlbit = (1 << 2),
312 }, {
313 .name = "uart",
314 .devname = "s3c6400-uart.2",
315 .parent = &clk_pclk_low.clk,
316 .enable = s5p64x0_pclk_ctrl,
317 .ctrlbit = (1 << 3),
318 }, {
319 .name = "uart",
320 .devname = "s3c6400-uart.3",
321 .parent = &clk_pclk_low.clk,
322 .enable = s5p64x0_pclk_ctrl,
323 .ctrlbit = (1 << 4),
324 }, {
325 .name = "gpio",
326 .parent = &clk_pclk_low.clk,
327 .enable = s5p64x0_pclk_ctrl,
328 .ctrlbit = (1 << 18),
329 },
330};
331
332static struct clk clk_iis_cd_v40 = {
333 .name = "iis_cdclk_v40",
334};
335
336static struct clk clk_pcm_cd = {
337 .name = "pcm_cdclk",
338};
339
340static struct clk *clkset_group1_list[] = {
341 &clk_mout_epll.clk,
342 &clk_dout_mpll.clk,
343 &clk_fin_epll,
344};
345
346static struct clksrc_sources clkset_group1 = {
347 .sources = clkset_group1_list,
348 .nr_sources = ARRAY_SIZE(clkset_group1_list),
349};
350
351static struct clk *clkset_uart_list[] = {
352 &clk_mout_epll.clk,
353 &clk_dout_mpll.clk,
354};
355
356static struct clksrc_sources clkset_uart = {
357 .sources = clkset_uart_list,
358 .nr_sources = ARRAY_SIZE(clkset_uart_list),
359};
360
361static struct clk *clkset_audio_list[] = {
362 &clk_mout_epll.clk,
363 &clk_dout_mpll.clk,
364 &clk_fin_epll,
365 &clk_iis_cd_v40,
366 &clk_pcm_cd,
367};
368
369static struct clksrc_sources clkset_audio = {
370 .sources = clkset_audio_list,
371 .nr_sources = ARRAY_SIZE(clkset_audio_list),
372};
373
374static struct clksrc_clk clksrcs[] = {
375 {
376 .clk = {
377 .name = "sclk_post",
378 .ctrlbit = (1 << 10),
379 .enable = s5p64x0_sclk_ctrl,
380 },
381 .sources = &clkset_group1,
382 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
383 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
384 }, {
385 .clk = {
386 .name = "sclk_dispcon",
387 .ctrlbit = (1 << 1),
388 .enable = s5p64x0_sclk1_ctrl,
389 },
390 .sources = &clkset_group1,
391 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
392 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
393 }, {
394 .clk = {
395 .name = "sclk_fimgvg",
396 .ctrlbit = (1 << 2),
397 .enable = s5p64x0_sclk1_ctrl,
398 },
399 .sources = &clkset_group1,
400 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
401 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
402 },
403};
404
405static struct clksrc_clk clk_sclk_mmc0 = {
406 .clk = {
407 .name = "sclk_mmc",
408 .devname = "s3c-sdhci.0",
409 .ctrlbit = (1 << 24),
410 .enable = s5p64x0_sclk_ctrl,
411 },
412 .sources = &clkset_group1,
413 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
414 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
415};
416
417static struct clksrc_clk clk_sclk_mmc1 = {
418 .clk = {
419 .name = "sclk_mmc",
420 .devname = "s3c-sdhci.1",
421 .ctrlbit = (1 << 25),
422 .enable = s5p64x0_sclk_ctrl,
423 },
424 .sources = &clkset_group1,
425 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
426 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
427};
428
429static struct clksrc_clk clk_sclk_mmc2 = {
430 .clk = {
431 .name = "sclk_mmc",
432 .devname = "s3c-sdhci.2",
433 .ctrlbit = (1 << 26),
434 .enable = s5p64x0_sclk_ctrl,
435 },
436 .sources = &clkset_group1,
437 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
438 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
439};
440
441static struct clksrc_clk clk_sclk_uclk = {
442 .clk = {
443 .name = "uclk1",
444 .ctrlbit = (1 << 5),
445 .enable = s5p64x0_sclk_ctrl,
446 },
447 .sources = &clkset_uart,
448 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
449 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
450};
451
452static struct clk clk_i2s0 = {
453 .name = "iis",
454 .devname = "samsung-i2s.0",
455 .parent = &clk_pclk_low.clk,
456 .enable = s5p64x0_pclk_ctrl,
457 .ctrlbit = (1 << 26),
458};
459
460static struct clksrc_clk clk_audio_bus2 = {
461 .clk = {
462 .name = "sclk_audio2",
463 .devname = "samsung-i2s.0",
464 .ctrlbit = (1 << 11),
465 .enable = s5p64x0_sclk_ctrl,
466 },
467 .sources = &clkset_audio,
468 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 0, .size = 3 },
469 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 24, .size = 4 },
470};
471
472static struct clksrc_clk clk_sclk_spi0 = {
473 .clk = {
474 .name = "sclk_spi",
475 .devname = "s5p64x0-spi.0",
476 .ctrlbit = (1 << 20),
477 .enable = s5p64x0_sclk_ctrl,
478 },
479 .sources = &clkset_group1,
480 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
481 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
482};
483
484static struct clksrc_clk clk_sclk_spi1 = {
485 .clk = {
486 .name = "sclk_spi",
487 .devname = "s5p64x0-spi.1",
488 .ctrlbit = (1 << 21),
489 .enable = s5p64x0_sclk_ctrl,
490 },
491 .sources = &clkset_group1,
492 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
493 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
494};
495
496/* Clock initialization code */
497static struct clksrc_clk *sysclks[] = {
498 &clk_mout_apll,
499 &clk_mout_epll,
500 &clk_mout_mpll,
501 &clk_dout_mpll,
502 &clk_armclk,
503 &clk_hclk,
504 &clk_pclk,
505 &clk_hclk_low,
506 &clk_pclk_low,
507};
508
509static struct clk dummy_apb_pclk = {
510 .name = "apb_pclk",
511 .id = -1,
512};
513
514static struct clk *clk_cdev[] = {
515 &clk_i2s0,
516};
517
518static struct clksrc_clk *clksrc_cdev[] = {
519 &clk_sclk_uclk,
520 &clk_sclk_spi0,
521 &clk_sclk_spi1,
522 &clk_sclk_mmc0,
523 &clk_sclk_mmc1,
524 &clk_sclk_mmc2,
525 &clk_audio_bus2,
526};
527
528static struct clk_lookup s5p6440_clk_lookup[] = {
529 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
530 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
531 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
532 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
533 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
534 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
535 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
536 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
537 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
538 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_audio_bus2.clk),
539};
540
541void __init_or_cpufreq s5p6440_setup_clocks(void)
542{
543 struct clk *xtal_clk;
544
545 unsigned long xtal;
546 unsigned long fclk;
547 unsigned long hclk;
548 unsigned long hclk_low;
549 unsigned long pclk;
550 unsigned long pclk_low;
551
552 unsigned long apll;
553 unsigned long mpll;
554 unsigned long epll;
555 unsigned int ptr;
556
557 /* Set S5P6440 functions for clk_fout_epll */
558
559 clk_fout_epll.enable = s5p_epll_enable;
560 clk_fout_epll.ops = &s5p6440_epll_ops;
561
562 clk_48m.enable = s5p64x0_clk48m_ctrl;
563
564 xtal_clk = clk_get(NULL, "ext_xtal");
565 BUG_ON(IS_ERR(xtal_clk));
566
567 xtal = clk_get_rate(xtal_clk);
568 clk_put(xtal_clk);
569
570 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
571 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
572 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
573 __raw_readl(S5P64X0_EPLL_CON_K));
574
575 clk_fout_apll.rate = apll;
576 clk_fout_mpll.rate = mpll;
577 clk_fout_epll.rate = epll;
578
579 printk(KERN_INFO "S5P6440: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
580 " E=%ld.%ldMHz\n",
581 print_mhz(apll), print_mhz(mpll), print_mhz(epll));
582
583 fclk = clk_get_rate(&clk_armclk.clk);
584 hclk = clk_get_rate(&clk_hclk.clk);
585 pclk = clk_get_rate(&clk_pclk.clk);
586 hclk_low = clk_get_rate(&clk_hclk_low.clk);
587 pclk_low = clk_get_rate(&clk_pclk_low.clk);
588
589 printk(KERN_INFO "S5P6440: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
590 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
591 print_mhz(hclk), print_mhz(hclk_low),
592 print_mhz(pclk), print_mhz(pclk_low));
593
594 clk_f.rate = fclk;
595 clk_h.rate = hclk;
596 clk_p.rate = pclk;
597
598 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
599 s3c_set_clksrc(&clksrcs[ptr], true);
600}
601
602static struct clk *clks[] __initdata = {
603 &clk_ext,
604 &clk_iis_cd_v40,
605 &clk_pcm_cd,
606};
607
608void __init s5p6440_register_clocks(void)
609{
610 int ptr;
611 unsigned int cnt;
612
613 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
614
615 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
616 s3c_register_clksrc(sysclks[ptr], 1);
617
618 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
619 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
620 s3c_disable_clocks(clk_cdev[cnt], 1);
621
622 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
623 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
624 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
625 s3c_register_clksrc(clksrc_cdev[ptr], 1);
626
627 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
628 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
629 clkdev_add_table(s5p6440_clk_lookup, ARRAY_SIZE(s5p6440_clk_lookup));
630
631 s3c24xx_register_clock(&dummy_apb_pclk);
632}
diff --git a/arch/arm/mach-s5p64x0/clock-s5p6450.c b/arch/arm/mach-s5p64x0/clock-s5p6450.c
deleted file mode 100644
index 0b3ca2ed53e9..000000000000
--- a/arch/arm/mach-s5p64x0/clock-s5p6450.c
+++ /dev/null
@@ -1,701 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock-s5p6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P6450 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "clock.h"
35#include "common.h"
36
37static struct clksrc_clk clk_mout_dpll = {
38 .clk = {
39 .name = "mout_dpll",
40 },
41 .sources = &clk_src_dpll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 5, .size = 1 },
43};
44
45static u32 epll_div[][5] = {
46 { 133000000, 27307, 55, 2, 2 },
47 { 100000000, 43691, 41, 2, 2 },
48 { 480000000, 0, 80, 2, 0 },
49};
50
51static int s5p6450_epll_set_rate(struct clk *clk, unsigned long rate)
52{
53 unsigned int epll_con, epll_con_k;
54 unsigned int i;
55
56 if (clk->rate == rate) /* Return if nothing changed */
57 return 0;
58
59 epll_con = __raw_readl(S5P64X0_EPLL_CON);
60 epll_con_k = __raw_readl(S5P64X0_EPLL_CON_K);
61
62 epll_con_k &= ~(PLL90XX_KDIV_MASK);
63 epll_con &= ~(PLL90XX_MDIV_MASK | PLL90XX_PDIV_MASK | PLL90XX_SDIV_MASK);
64
65 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
66 if (epll_div[i][0] == rate) {
67 epll_con_k |= (epll_div[i][1] << PLL90XX_KDIV_SHIFT);
68 epll_con |= (epll_div[i][2] << PLL90XX_MDIV_SHIFT) |
69 (epll_div[i][3] << PLL90XX_PDIV_SHIFT) |
70 (epll_div[i][4] << PLL90XX_SDIV_SHIFT);
71 break;
72 }
73 }
74
75 if (i == ARRAY_SIZE(epll_div)) {
76 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
77 return -EINVAL;
78 }
79
80 __raw_writel(epll_con, S5P64X0_EPLL_CON);
81 __raw_writel(epll_con_k, S5P64X0_EPLL_CON_K);
82
83 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
84 clk->rate, rate);
85
86 clk->rate = rate;
87
88 return 0;
89}
90
91static struct clk_ops s5p6450_epll_ops = {
92 .get_rate = s5p_epll_get_rate,
93 .set_rate = s5p6450_epll_set_rate,
94};
95
96static struct clksrc_clk clk_dout_epll = {
97 .clk = {
98 .name = "dout_epll",
99 .parent = &clk_mout_epll.clk,
100 },
101 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 24, .size = 4 },
102};
103
104static struct clksrc_clk clk_mout_hclk_sel = {
105 .clk = {
106 .name = "mout_hclk_sel",
107 },
108 .sources = &clkset_hclk_low,
109 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 15, .size = 1 },
110};
111
112static struct clk *clkset_hclk_list[] = {
113 &clk_mout_hclk_sel.clk,
114 &clk_armclk.clk,
115};
116
117static struct clksrc_sources clkset_hclk = {
118 .sources = clkset_hclk_list,
119 .nr_sources = ARRAY_SIZE(clkset_hclk_list),
120};
121
122static struct clksrc_clk clk_hclk = {
123 .clk = {
124 .name = "clk_hclk",
125 },
126 .sources = &clkset_hclk,
127 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 14, .size = 1 },
128 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 8, .size = 4 },
129};
130
131static struct clksrc_clk clk_pclk = {
132 .clk = {
133 .name = "clk_pclk",
134 .parent = &clk_hclk.clk,
135 },
136 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 12, .size = 4 },
137};
138static struct clksrc_clk clk_dout_pwm_ratio0 = {
139 .clk = {
140 .name = "clk_dout_pwm_ratio0",
141 .parent = &clk_mout_hclk_sel.clk,
142 },
143 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 16, .size = 4 },
144};
145
146static struct clksrc_clk clk_pclk_to_wdt_pwm = {
147 .clk = {
148 .name = "clk_pclk_to_wdt_pwm",
149 .parent = &clk_dout_pwm_ratio0.clk,
150 },
151 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 20, .size = 4 },
152};
153
154static struct clksrc_clk clk_hclk_low = {
155 .clk = {
156 .name = "clk_hclk_low",
157 },
158 .sources = &clkset_hclk_low,
159 .reg_src = { .reg = S5P64X0_OTHERS, .shift = 6, .size = 1 },
160 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 8, .size = 4 },
161};
162
163static struct clksrc_clk clk_pclk_low = {
164 .clk = {
165 .name = "clk_pclk_low",
166 .parent = &clk_hclk_low.clk,
167 },
168 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 12, .size = 4 },
169};
170
171/*
172 * The following clocks will be disabled during clock initialization. It is
173 * recommended to keep the following clocks disabled until the driver requests
174 * for enabling the clock.
175 */
176static struct clk init_clocks_off[] = {
177 {
178 .name = "usbhost",
179 .parent = &clk_hclk_low.clk,
180 .enable = s5p64x0_hclk0_ctrl,
181 .ctrlbit = (1 << 3),
182 }, {
183 .name = "dma",
184 .devname = "dma-pl330",
185 .parent = &clk_hclk_low.clk,
186 .enable = s5p64x0_hclk0_ctrl,
187 .ctrlbit = (1 << 12),
188 }, {
189 .name = "hsmmc",
190 .devname = "s3c-sdhci.0",
191 .parent = &clk_hclk_low.clk,
192 .enable = s5p64x0_hclk0_ctrl,
193 .ctrlbit = (1 << 17),
194 }, {
195 .name = "hsmmc",
196 .devname = "s3c-sdhci.1",
197 .parent = &clk_hclk_low.clk,
198 .enable = s5p64x0_hclk0_ctrl,
199 .ctrlbit = (1 << 18),
200 }, {
201 .name = "hsmmc",
202 .devname = "s3c-sdhci.2",
203 .parent = &clk_hclk_low.clk,
204 .enable = s5p64x0_hclk0_ctrl,
205 .ctrlbit = (1 << 19),
206 }, {
207 .name = "usbotg",
208 .parent = &clk_hclk_low.clk,
209 .enable = s5p64x0_hclk0_ctrl,
210 .ctrlbit = (1 << 20),
211 }, {
212 .name = "lcd",
213 .parent = &clk_h,
214 .enable = s5p64x0_hclk1_ctrl,
215 .ctrlbit = (1 << 1),
216 }, {
217 .name = "watchdog",
218 .parent = &clk_pclk_low.clk,
219 .enable = s5p64x0_pclk_ctrl,
220 .ctrlbit = (1 << 5),
221 }, {
222 .name = "rtc",
223 .parent = &clk_pclk_low.clk,
224 .enable = s5p64x0_pclk_ctrl,
225 .ctrlbit = (1 << 6),
226 }, {
227 .name = "adc",
228 .parent = &clk_pclk_low.clk,
229 .enable = s5p64x0_pclk_ctrl,
230 .ctrlbit = (1 << 12),
231 }, {
232 .name = "i2c",
233 .devname = "s3c2440-i2c.0",
234 .parent = &clk_pclk_low.clk,
235 .enable = s5p64x0_pclk_ctrl,
236 .ctrlbit = (1 << 17),
237 }, {
238 .name = "spi",
239 .devname = "s5p64x0-spi.0",
240 .parent = &clk_pclk_low.clk,
241 .enable = s5p64x0_pclk_ctrl,
242 .ctrlbit = (1 << 21),
243 }, {
244 .name = "spi",
245 .devname = "s5p64x0-spi.1",
246 .parent = &clk_pclk_low.clk,
247 .enable = s5p64x0_pclk_ctrl,
248 .ctrlbit = (1 << 22),
249 }, {
250 .name = "i2c",
251 .devname = "s3c2440-i2c.1",
252 .parent = &clk_pclk_low.clk,
253 .enable = s5p64x0_pclk_ctrl,
254 .ctrlbit = (1 << 27),
255 }, {
256 .name = "dmc0",
257 .parent = &clk_pclk.clk,
258 .enable = s5p64x0_pclk_ctrl,
259 .ctrlbit = (1 << 30),
260 }
261};
262
263/*
264 * The following clocks will be enabled during clock initialization.
265 */
266static struct clk init_clocks[] = {
267 {
268 .name = "intc",
269 .parent = &clk_hclk.clk,
270 .enable = s5p64x0_hclk0_ctrl,
271 .ctrlbit = (1 << 1),
272 }, {
273 .name = "mem",
274 .parent = &clk_hclk.clk,
275 .enable = s5p64x0_hclk0_ctrl,
276 .ctrlbit = (1 << 21),
277 }, {
278 .name = "uart",
279 .devname = "s3c6400-uart.0",
280 .parent = &clk_pclk_low.clk,
281 .enable = s5p64x0_pclk_ctrl,
282 .ctrlbit = (1 << 1),
283 }, {
284 .name = "uart",
285 .devname = "s3c6400-uart.1",
286 .parent = &clk_pclk_low.clk,
287 .enable = s5p64x0_pclk_ctrl,
288 .ctrlbit = (1 << 2),
289 }, {
290 .name = "uart",
291 .devname = "s3c6400-uart.2",
292 .parent = &clk_pclk_low.clk,
293 .enable = s5p64x0_pclk_ctrl,
294 .ctrlbit = (1 << 3),
295 }, {
296 .name = "uart",
297 .devname = "s3c6400-uart.3",
298 .parent = &clk_pclk_low.clk,
299 .enable = s5p64x0_pclk_ctrl,
300 .ctrlbit = (1 << 4),
301 }, {
302 .name = "timers",
303 .parent = &clk_pclk_to_wdt_pwm.clk,
304 .enable = s5p64x0_pclk_ctrl,
305 .ctrlbit = (1 << 7),
306 }, {
307 .name = "gpio",
308 .parent = &clk_pclk_low.clk,
309 .enable = s5p64x0_pclk_ctrl,
310 .ctrlbit = (1 << 18),
311 },
312};
313
314static struct clk *clkset_uart_list[] = {
315 &clk_dout_epll.clk,
316 &clk_dout_mpll.clk,
317};
318
319static struct clksrc_sources clkset_uart = {
320 .sources = clkset_uart_list,
321 .nr_sources = ARRAY_SIZE(clkset_uart_list),
322};
323
324static struct clk *clkset_mali_list[] = {
325 &clk_mout_epll.clk,
326 &clk_mout_apll.clk,
327 &clk_mout_mpll.clk,
328};
329
330static struct clksrc_sources clkset_mali = {
331 .sources = clkset_mali_list,
332 .nr_sources = ARRAY_SIZE(clkset_mali_list),
333};
334
335static struct clk *clkset_group2_list[] = {
336 &clk_dout_epll.clk,
337 &clk_dout_mpll.clk,
338 &clk_ext_xtal_mux,
339};
340
341static struct clksrc_sources clkset_group2 = {
342 .sources = clkset_group2_list,
343 .nr_sources = ARRAY_SIZE(clkset_group2_list),
344};
345
346static struct clk *clkset_dispcon_list[] = {
347 &clk_dout_epll.clk,
348 &clk_dout_mpll.clk,
349 &clk_ext_xtal_mux,
350 &clk_mout_dpll.clk,
351};
352
353static struct clksrc_sources clkset_dispcon = {
354 .sources = clkset_dispcon_list,
355 .nr_sources = ARRAY_SIZE(clkset_dispcon_list),
356};
357
358static struct clk *clkset_hsmmc44_list[] = {
359 &clk_dout_epll.clk,
360 &clk_dout_mpll.clk,
361 &clk_ext_xtal_mux,
362 &s5p_clk_27m,
363 &clk_48m,
364};
365
366static struct clksrc_sources clkset_hsmmc44 = {
367 .sources = clkset_hsmmc44_list,
368 .nr_sources = ARRAY_SIZE(clkset_hsmmc44_list),
369};
370
371static struct clk *clkset_sclk_audio0_list[] = {
372 [0] = &clk_dout_epll.clk,
373 [1] = &clk_dout_mpll.clk,
374 [2] = &clk_ext_xtal_mux,
375 [3] = NULL,
376 [4] = NULL,
377};
378
379static struct clksrc_sources clkset_sclk_audio0 = {
380 .sources = clkset_sclk_audio0_list,
381 .nr_sources = ARRAY_SIZE(clkset_sclk_audio0_list),
382};
383
384static struct clksrc_clk clk_sclk_audio0 = {
385 .clk = {
386 .name = "audio-bus",
387 .devname = "samsung-i2s.0",
388 .enable = s5p64x0_sclk_ctrl,
389 .ctrlbit = (1 << 8),
390 .parent = &clk_dout_epll.clk,
391 },
392 .sources = &clkset_sclk_audio0,
393 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 10, .size = 3 },
394 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 8, .size = 4 },
395};
396
397static struct clksrc_clk clksrcs[] = {
398 {
399 .clk = {
400 .name = "sclk_fimc",
401 .ctrlbit = (1 << 10),
402 .enable = s5p64x0_sclk_ctrl,
403 },
404 .sources = &clkset_group2,
405 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 26, .size = 2 },
406 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 12, .size = 4 },
407 }, {
408 .clk = {
409 .name = "aclk_mali",
410 .ctrlbit = (1 << 2),
411 .enable = s5p64x0_sclk1_ctrl,
412 },
413 .sources = &clkset_mali,
414 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 8, .size = 2 },
415 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 4, .size = 4 },
416 }, {
417 .clk = {
418 .name = "sclk_2d",
419 .ctrlbit = (1 << 12),
420 .enable = s5p64x0_sclk_ctrl,
421 },
422 .sources = &clkset_mali,
423 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 30, .size = 2 },
424 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 20, .size = 4 },
425 }, {
426 .clk = {
427 .name = "sclk_usi",
428 .ctrlbit = (1 << 7),
429 .enable = s5p64x0_sclk_ctrl,
430 },
431 .sources = &clkset_group2,
432 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 10, .size = 2 },
433 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 16, .size = 4 },
434 }, {
435 .clk = {
436 .name = "sclk_camif",
437 .ctrlbit = (1 << 6),
438 .enable = s5p64x0_sclk_ctrl,
439 },
440 .sources = &clkset_group2,
441 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 28, .size = 2 },
442 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 20, .size = 4 },
443 }, {
444 .clk = {
445 .name = "sclk_dispcon",
446 .ctrlbit = (1 << 1),
447 .enable = s5p64x0_sclk1_ctrl,
448 },
449 .sources = &clkset_dispcon,
450 .reg_src = { .reg = S5P64X0_CLK_SRC1, .shift = 4, .size = 2 },
451 .reg_div = { .reg = S5P64X0_CLK_DIV3, .shift = 0, .size = 4 },
452 }, {
453 .clk = {
454 .name = "sclk_hsmmc44",
455 .ctrlbit = (1 << 30),
456 .enable = s5p64x0_sclk_ctrl,
457 },
458 .sources = &clkset_hsmmc44,
459 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 6, .size = 3 },
460 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 28, .size = 4 },
461 },
462};
463
464static struct clksrc_clk clk_sclk_mmc0 = {
465 .clk = {
466 .name = "sclk_mmc",
467 .devname = "s3c-sdhci.0",
468 .ctrlbit = (1 << 24),
469 .enable = s5p64x0_sclk_ctrl,
470 },
471 .sources = &clkset_group2,
472 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 18, .size = 2 },
473 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 0, .size = 4 },
474};
475
476static struct clksrc_clk clk_sclk_mmc1 = {
477 .clk = {
478 .name = "sclk_mmc",
479 .devname = "s3c-sdhci.1",
480 .ctrlbit = (1 << 25),
481 .enable = s5p64x0_sclk_ctrl,
482 },
483 .sources = &clkset_group2,
484 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 20, .size = 2 },
485 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 4, .size = 4 },
486};
487
488static struct clksrc_clk clk_sclk_mmc2 = {
489 .clk = {
490 .name = "sclk_mmc",
491 .devname = "s3c-sdhci.2",
492 .ctrlbit = (1 << 26),
493 .enable = s5p64x0_sclk_ctrl,
494 },
495 .sources = &clkset_group2,
496 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 22, .size = 2 },
497 .reg_div = { .reg = S5P64X0_CLK_DIV1, .shift = 8, .size = 4 },
498};
499
500static struct clksrc_clk clk_sclk_uclk = {
501 .clk = {
502 .name = "uclk1",
503 .ctrlbit = (1 << 5),
504 .enable = s5p64x0_sclk_ctrl,
505 },
506 .sources = &clkset_uart,
507 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 13, .size = 1 },
508 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 16, .size = 4 },
509};
510
511static struct clksrc_clk clk_sclk_spi0 = {
512 .clk = {
513 .name = "sclk_spi",
514 .devname = "s5p64x0-spi.0",
515 .ctrlbit = (1 << 20),
516 .enable = s5p64x0_sclk_ctrl,
517 },
518 .sources = &clkset_group2,
519 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 14, .size = 2 },
520 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 0, .size = 4 },
521};
522
523static struct clksrc_clk clk_sclk_spi1 = {
524 .clk = {
525 .name = "sclk_spi",
526 .devname = "s5p64x0-spi.1",
527 .ctrlbit = (1 << 21),
528 .enable = s5p64x0_sclk_ctrl,
529 },
530 .sources = &clkset_group2,
531 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 16, .size = 2 },
532 .reg_div = { .reg = S5P64X0_CLK_DIV2, .shift = 4, .size = 4 },
533};
534
535static struct clk clk_i2s0 = {
536 .name = "iis",
537 .devname = "samsung-i2s.0",
538 .parent = &clk_pclk_low.clk,
539 .enable = s5p64x0_pclk_ctrl,
540 .ctrlbit = (1 << 26),
541};
542
543static struct clk clk_i2s1 = {
544 .name = "iis",
545 .devname = "samsung-i2s.1",
546 .parent = &clk_pclk_low.clk,
547 .enable = s5p64x0_pclk_ctrl,
548 .ctrlbit = (1 << 15),
549};
550
551static struct clk clk_i2s2 = {
552 .name = "iis",
553 .devname = "samsung-i2s.2",
554 .parent = &clk_pclk_low.clk,
555 .enable = s5p64x0_pclk_ctrl,
556 .ctrlbit = (1 << 16),
557};
558
559static struct clk *clk_cdev[] = {
560 &clk_i2s0,
561 &clk_i2s1,
562 &clk_i2s2,
563};
564
565static struct clksrc_clk *clksrc_cdev[] = {
566 &clk_sclk_uclk,
567 &clk_sclk_spi0,
568 &clk_sclk_spi1,
569 &clk_sclk_mmc0,
570 &clk_sclk_mmc1,
571 &clk_sclk_mmc2,
572 &clk_sclk_audio0,
573};
574
575static struct clk_lookup s5p6450_clk_lookup[] = {
576 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_pclk_low.clk),
577 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uclk.clk),
578 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
579 CLKDEV_INIT("s5p64x0-spi.0", "spi_busclk1", &clk_sclk_spi0.clk),
580 CLKDEV_INIT("s5p64x0-spi.1", "spi_busclk1", &clk_sclk_spi1.clk),
581 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
582 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
583 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
584 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
585 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk1", &clk_sclk_audio0.clk),
586 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
587 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
588};
589
590/* Clock initialization code */
591static struct clksrc_clk *sysclks[] = {
592 &clk_mout_apll,
593 &clk_mout_epll,
594 &clk_dout_epll,
595 &clk_mout_mpll,
596 &clk_dout_mpll,
597 &clk_armclk,
598 &clk_mout_hclk_sel,
599 &clk_dout_pwm_ratio0,
600 &clk_pclk_to_wdt_pwm,
601 &clk_hclk,
602 &clk_pclk,
603 &clk_hclk_low,
604 &clk_pclk_low,
605};
606
607static struct clk dummy_apb_pclk = {
608 .name = "apb_pclk",
609 .id = -1,
610};
611
612void __init_or_cpufreq s5p6450_setup_clocks(void)
613{
614 struct clk *xtal_clk;
615
616 unsigned long xtal;
617 unsigned long fclk;
618 unsigned long hclk;
619 unsigned long hclk_low;
620 unsigned long pclk;
621 unsigned long pclk_low;
622
623 unsigned long apll;
624 unsigned long mpll;
625 unsigned long epll;
626 unsigned long dpll;
627 unsigned int ptr;
628
629 /* Set S5P6450 functions for clk_fout_epll */
630
631 clk_fout_epll.enable = s5p_epll_enable;
632 clk_fout_epll.ops = &s5p6450_epll_ops;
633
634 clk_48m.enable = s5p64x0_clk48m_ctrl;
635
636 xtal_clk = clk_get(NULL, "ext_xtal");
637 BUG_ON(IS_ERR(xtal_clk));
638
639 xtal = clk_get_rate(xtal_clk);
640 clk_put(xtal_clk);
641
642 apll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_APLL_CON), pll_4502);
643 mpll = s5p_get_pll45xx(xtal, __raw_readl(S5P64X0_MPLL_CON), pll_4502);
644 epll = s5p_get_pll90xx(xtal, __raw_readl(S5P64X0_EPLL_CON),
645 __raw_readl(S5P64X0_EPLL_CON_K));
646 dpll = s5p_get_pll46xx(xtal, __raw_readl(S5P6450_DPLL_CON),
647 __raw_readl(S5P6450_DPLL_CON_K), pll_4650c);
648
649 clk_fout_apll.rate = apll;
650 clk_fout_mpll.rate = mpll;
651 clk_fout_epll.rate = epll;
652 clk_fout_dpll.rate = dpll;
653
654 printk(KERN_INFO "S5P6450: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz," \
655 " E=%ld.%ldMHz, D=%ld.%ldMHz\n",
656 print_mhz(apll), print_mhz(mpll), print_mhz(epll),
657 print_mhz(dpll));
658
659 fclk = clk_get_rate(&clk_armclk.clk);
660 hclk = clk_get_rate(&clk_hclk.clk);
661 pclk = clk_get_rate(&clk_pclk.clk);
662 hclk_low = clk_get_rate(&clk_hclk_low.clk);
663 pclk_low = clk_get_rate(&clk_pclk_low.clk);
664
665 printk(KERN_INFO "S5P6450: HCLK=%ld.%ldMHz, HCLK_LOW=%ld.%ldMHz," \
666 " PCLK=%ld.%ldMHz, PCLK_LOW=%ld.%ldMHz\n",
667 print_mhz(hclk), print_mhz(hclk_low),
668 print_mhz(pclk), print_mhz(pclk_low));
669
670 clk_f.rate = fclk;
671 clk_h.rate = hclk;
672 clk_p.rate = pclk;
673
674 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
675 s3c_set_clksrc(&clksrcs[ptr], true);
676}
677
678void __init s5p6450_register_clocks(void)
679{
680 int ptr;
681 unsigned int cnt;
682
683 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
684 s3c_register_clksrc(sysclks[ptr], 1);
685
686
687 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
688 for (cnt = 0; cnt < ARRAY_SIZE(clk_cdev); cnt++)
689 s3c_disable_clocks(clk_cdev[cnt], 1);
690
691 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
692 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
693 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
694 s3c_register_clksrc(clksrc_cdev[ptr], 1);
695
696 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
697 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
698 clkdev_add_table(s5p6450_clk_lookup, ARRAY_SIZE(s5p6450_clk_lookup));
699
700 s3c24xx_register_clock(&dummy_apb_pclk);
701}
diff --git a/arch/arm/mach-s5p64x0/clock.c b/arch/arm/mach-s5p64x0/clock.c
deleted file mode 100644
index 57e718957ef3..000000000000
--- a/arch/arm/mach-s5p64x0/clock.c
+++ /dev/null
@@ -1,236 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/errno.h>
18#include <linux/err.h>
19#include <linux/clk.h>
20#include <linux/device.h>
21#include <linux/io.h>
22
23#include <mach/hardware.h>
24#include <mach/map.h>
25#include <mach/regs-clock.h>
26
27#include <plat/cpu-freq.h>
28#include <plat/clock.h>
29#include <plat/cpu.h>
30#include <plat/pll.h>
31#include <plat/s5p-clock.h>
32#include <plat/clock-clksrc.h>
33
34#include "common.h"
35
36struct clksrc_clk clk_mout_apll = {
37 .clk = {
38 .name = "mout_apll",
39 .id = -1,
40 },
41 .sources = &clk_src_apll,
42 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 0, .size = 1 },
43};
44
45struct clksrc_clk clk_mout_mpll = {
46 .clk = {
47 .name = "mout_mpll",
48 .id = -1,
49 },
50 .sources = &clk_src_mpll,
51 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 1, .size = 1 },
52};
53
54struct clksrc_clk clk_mout_epll = {
55 .clk = {
56 .name = "mout_epll",
57 .id = -1,
58 },
59 .sources = &clk_src_epll,
60 .reg_src = { .reg = S5P64X0_CLK_SRC0, .shift = 2, .size = 1 },
61};
62
63enum perf_level {
64 L0 = 532*1000,
65 L1 = 266*1000,
66 L2 = 133*1000,
67};
68
69static const u32 clock_table[][3] = {
70 /*{ARM_CLK, DIVarm, DIVhclk}*/
71 {L0 * 1000, (0 << ARM_DIV_RATIO_SHIFT), (3 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
72 {L1 * 1000, (1 << ARM_DIV_RATIO_SHIFT), (1 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
73 {L2 * 1000, (3 << ARM_DIV_RATIO_SHIFT), (0 << S5P64X0_CLKDIV0_HCLK_SHIFT)},
74};
75
76static unsigned long s5p64x0_armclk_get_rate(struct clk *clk)
77{
78 unsigned long rate = clk_get_rate(clk->parent);
79 u32 clkdiv;
80
81 /* divisor mask starts at bit0, so no need to shift */
82 clkdiv = __raw_readl(ARM_CLK_DIV) & ARM_DIV_MASK;
83
84 return rate / (clkdiv + 1);
85}
86
87static unsigned long s5p64x0_armclk_round_rate(struct clk *clk,
88 unsigned long rate)
89{
90 u32 iter;
91
92 for (iter = 1 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
93 if (rate > clock_table[iter][0])
94 return clock_table[iter-1][0];
95 }
96
97 return clock_table[ARRAY_SIZE(clock_table) - 1][0];
98}
99
100static int s5p64x0_armclk_set_rate(struct clk *clk, unsigned long rate)
101{
102 u32 round_tmp;
103 u32 iter;
104 u32 clk_div0_tmp;
105 u32 cur_rate = clk->ops->get_rate(clk);
106 unsigned long flags;
107
108 round_tmp = clk->ops->round_rate(clk, rate);
109 if (round_tmp == cur_rate)
110 return 0;
111
112
113 for (iter = 0 ; iter < ARRAY_SIZE(clock_table) ; iter++) {
114 if (round_tmp == clock_table[iter][0])
115 break;
116 }
117
118 if (iter >= ARRAY_SIZE(clock_table))
119 iter = ARRAY_SIZE(clock_table) - 1;
120
121 local_irq_save(flags);
122 if (cur_rate > round_tmp) {
123 /* Frequency Down */
124 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
125 clk_div0_tmp |= clock_table[iter][1];
126 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
127
128 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
129 ~(S5P64X0_CLKDIV0_HCLK_MASK);
130 clk_div0_tmp |= clock_table[iter][2];
131 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
132
133
134 } else {
135 /* Frequency Up */
136 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) &
137 ~(S5P64X0_CLKDIV0_HCLK_MASK);
138 clk_div0_tmp |= clock_table[iter][2];
139 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
140
141 clk_div0_tmp = __raw_readl(ARM_CLK_DIV) & ~(ARM_DIV_MASK);
142 clk_div0_tmp |= clock_table[iter][1];
143 __raw_writel(clk_div0_tmp, ARM_CLK_DIV);
144 }
145 local_irq_restore(flags);
146
147 clk->rate = clock_table[iter][0];
148
149 return 0;
150}
151
152static struct clk_ops s5p64x0_clkarm_ops = {
153 .get_rate = s5p64x0_armclk_get_rate,
154 .set_rate = s5p64x0_armclk_set_rate,
155 .round_rate = s5p64x0_armclk_round_rate,
156};
157
158struct clksrc_clk clk_armclk = {
159 .clk = {
160 .name = "armclk",
161 .id = 1,
162 .parent = &clk_mout_apll.clk,
163 .ops = &s5p64x0_clkarm_ops,
164 },
165 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 0, .size = 4 },
166};
167
168struct clksrc_clk clk_dout_mpll = {
169 .clk = {
170 .name = "dout_mpll",
171 .id = -1,
172 .parent = &clk_mout_mpll.clk,
173 },
174 .reg_div = { .reg = S5P64X0_CLK_DIV0, .shift = 4, .size = 1 },
175};
176
177static struct clk *clkset_hclk_low_list[] = {
178 &clk_mout_apll.clk,
179 &clk_mout_mpll.clk,
180};
181
182struct clksrc_sources clkset_hclk_low = {
183 .sources = clkset_hclk_low_list,
184 .nr_sources = ARRAY_SIZE(clkset_hclk_low_list),
185};
186
187int s5p64x0_pclk_ctrl(struct clk *clk, int enable)
188{
189 return s5p_gatectrl(S5P64X0_CLK_GATE_PCLK, clk, enable);
190}
191
192int s5p64x0_hclk0_ctrl(struct clk *clk, int enable)
193{
194 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK0, clk, enable);
195}
196
197int s5p64x0_hclk1_ctrl(struct clk *clk, int enable)
198{
199 return s5p_gatectrl(S5P64X0_CLK_GATE_HCLK1, clk, enable);
200}
201
202int s5p64x0_sclk_ctrl(struct clk *clk, int enable)
203{
204 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK0, clk, enable);
205}
206
207int s5p64x0_sclk1_ctrl(struct clk *clk, int enable)
208{
209 return s5p_gatectrl(S5P64X0_CLK_GATE_SCLK1, clk, enable);
210}
211
212int s5p64x0_mem_ctrl(struct clk *clk, int enable)
213{
214 return s5p_gatectrl(S5P64X0_CLK_GATE_MEM0, clk, enable);
215}
216
217int s5p64x0_clk48m_ctrl(struct clk *clk, int enable)
218{
219 unsigned long flags;
220 u32 val;
221
222 /* can't rely on clock lock, this register has other usages */
223 local_irq_save(flags);
224
225 val = __raw_readl(S5P64X0_OTHERS);
226 if (enable)
227 val |= S5P64X0_OTHERS_USB_SIG_MASK;
228 else
229 val &= ~S5P64X0_OTHERS_USB_SIG_MASK;
230
231 __raw_writel(val, S5P64X0_OTHERS);
232
233 local_irq_restore(flags);
234
235 return 0;
236}
diff --git a/arch/arm/mach-s5p64x0/clock.h b/arch/arm/mach-s5p64x0/clock.h
deleted file mode 100644
index 28b8e3c6bd24..000000000000
--- a/arch/arm/mach-s5p64x0/clock.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Header file for s5p64x0 clock support
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#ifndef __MACH_S5P64X0_CLOCK_H
13#define __MACH_S5P64X0_CLOCK_H __FILE__
14
15#include <linux/clk.h>
16
17extern struct clksrc_clk clk_mout_apll;
18extern struct clksrc_clk clk_mout_mpll;
19extern struct clksrc_clk clk_mout_epll;
20
21extern int s5p64x0_epll_enable(struct clk *clk, int enable);
22extern unsigned long s5p64x0_epll_get_rate(struct clk *clk);
23
24extern struct clksrc_clk clk_armclk;
25extern struct clksrc_clk clk_dout_mpll;
26
27extern struct clksrc_sources clkset_hclk_low;
28
29extern int s5p64x0_pclk_ctrl(struct clk *clk, int enable);
30extern int s5p64x0_hclk0_ctrl(struct clk *clk, int enable);
31extern int s5p64x0_hclk1_ctrl(struct clk *clk, int enable);
32extern int s5p64x0_sclk_ctrl(struct clk *clk, int enable);
33extern int s5p64x0_sclk1_ctrl(struct clk *clk, int enable);
34extern int s5p64x0_mem_ctrl(struct clk *clk, int enable);
35
36extern int s5p64x0_clk48m_ctrl(struct clk *clk, int enable);
37
38#endif /* __MACH_S5P64X0_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/common.c b/arch/arm/mach-s5p64x0/common.c
deleted file mode 100644
index 9a43be002d78..000000000000
--- a/arch/arm/mach-s5p64x0/common.c
+++ /dev/null
@@ -1,490 +0,0 @@
1/*
2 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Codes for S5P64X0 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20#include <linux/device.h>
21#include <linux/serial_core.h>
22#include <linux/serial_s3c.h>
23#include <clocksource/samsung_pwm.h>
24#include <linux/platform_device.h>
25#include <linux/sched.h>
26#include <linux/dma-mapping.h>
27#include <linux/gpio.h>
28#include <linux/irq.h>
29#include <linux/reboot.h>
30
31#include <asm/irq.h>
32#include <asm/proc-fns.h>
33#include <asm/system_misc.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/map.h>
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/cpu.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/pm.h>
47#include <plat/sdhci.h>
48#include <plat/adc-core.h>
49#include <plat/fb-core.h>
50#include <plat/spi-core.h>
51#include <plat/gpio-cfg.h>
52#include <plat/pwm-core.h>
53#include <plat/regs-irqtype.h>
54#include <plat/watchdog-reset.h>
55
56#include "common.h"
57
58static const char name_s5p6440[] = "S5P6440";
59static const char name_s5p6450[] = "S5P6450";
60
61static struct cpu_table cpu_ids[] __initdata = {
62 {
63 .idcode = S5P6440_CPU_ID,
64 .idmask = S5P64XX_CPU_MASK,
65 .map_io = s5p6440_map_io,
66 .init_clocks = s5p6440_init_clocks,
67 .init_uarts = s5p6440_init_uarts,
68 .init = s5p64x0_init,
69 .name = name_s5p6440,
70 }, {
71 .idcode = S5P6450_CPU_ID,
72 .idmask = S5P64XX_CPU_MASK,
73 .map_io = s5p6450_map_io,
74 .init_clocks = s5p6450_init_clocks,
75 .init_uarts = s5p6450_init_uarts,
76 .init = s5p64x0_init,
77 .name = name_s5p6450,
78 },
79};
80
81/* Initial IO mappings */
82
83static struct map_desc s5p64x0_iodesc[] __initdata = {
84 {
85 .virtual = (unsigned long)S5P_VA_CHIPID,
86 .pfn = __phys_to_pfn(S5P64X0_PA_CHIPID),
87 .length = SZ_4K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_SYS,
91 .pfn = __phys_to_pfn(S5P64X0_PA_SYSCON),
92 .length = SZ_64K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S3C_VA_TIMER,
96 .pfn = __phys_to_pfn(S5P64X0_PA_TIMER),
97 .length = SZ_16K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S3C_VA_WATCHDOG,
101 .pfn = __phys_to_pfn(S5P64X0_PA_WDT),
102 .length = SZ_4K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_SROMC,
106 .pfn = __phys_to_pfn(S5P64X0_PA_SROMC),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)S5P_VA_GPIO,
111 .pfn = __phys_to_pfn(S5P64X0_PA_GPIO),
112 .length = SZ_4K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)VA_VIC0,
116 .pfn = __phys_to_pfn(S5P64X0_PA_VIC0),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)VA_VIC1,
121 .pfn = __phys_to_pfn(S5P64X0_PA_VIC1),
122 .length = SZ_16K,
123 .type = MT_DEVICE,
124 },
125};
126
127static struct map_desc s5p6440_iodesc[] __initdata = {
128 {
129 .virtual = (unsigned long)S3C_VA_UART,
130 .pfn = __phys_to_pfn(S5P6440_PA_UART(0)),
131 .length = SZ_4K,
132 .type = MT_DEVICE,
133 },
134};
135
136static struct map_desc s5p6450_iodesc[] __initdata = {
137 {
138 .virtual = (unsigned long)S3C_VA_UART,
139 .pfn = __phys_to_pfn(S5P6450_PA_UART(0)),
140 .length = SZ_512K,
141 .type = MT_DEVICE,
142 }, {
143 .virtual = (unsigned long)S3C_VA_UART + SZ_512K,
144 .pfn = __phys_to_pfn(S5P6450_PA_UART(5)),
145 .length = SZ_4K,
146 .type = MT_DEVICE,
147 },
148};
149
150static void s5p64x0_idle(void)
151{
152 unsigned long val;
153
154 val = __raw_readl(S5P64X0_PWR_CFG);
155 val &= ~(0x3 << 5);
156 val |= (0x1 << 5);
157 __raw_writel(val, S5P64X0_PWR_CFG);
158
159 cpu_do_idle();
160}
161
162static struct samsung_pwm_variant s5p64x0_pwm_variant = {
163 .bits = 32,
164 .div_base = 0,
165 .has_tint_cstat = true,
166 .tclk_mask = 0,
167};
168
169void __init samsung_set_timer_source(unsigned int event, unsigned int source)
170{
171 s5p64x0_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
172 s5p64x0_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
173}
174
175void __init samsung_timer_init(void)
176{
177 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
178 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
179 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
180 };
181
182 samsung_pwm_clocksource_init(S3C_VA_TIMER,
183 timer_irqs, &s5p64x0_pwm_variant);
184}
185
186/*
187 * s5p64x0_map_io
188 *
189 * register the standard CPU IO areas
190 */
191
192void __init s5p64x0_init_io(struct map_desc *mach_desc, int size)
193{
194 /* initialize the io descriptors we need for initialization */
195 iotable_init(s5p64x0_iodesc, ARRAY_SIZE(s5p64x0_iodesc));
196 if (mach_desc)
197 iotable_init(mach_desc, size);
198
199 /* detect cpu id and rev. */
200 s5p_init_cpu(S5P64X0_SYS_ID);
201
202 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
203 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
204
205 samsung_pwm_set_platdata(&s5p64x0_pwm_variant);
206}
207
208#ifdef CONFIG_CPU_S5P6440
209void __init s5p6440_map_io(void)
210{
211 /* initialize any device information early */
212 s3c_adc_setname("s3c64xx-adc");
213 s3c_fb_setname("s5p64x0-fb");
214 s3c64xx_spi_setname("s5p64x0-spi");
215
216 s5p64x0_default_sdhci0();
217 s5p64x0_default_sdhci1();
218 s5p6440_default_sdhci2();
219
220 iotable_init(s5p6440_iodesc, ARRAY_SIZE(s5p6440_iodesc));
221}
222#endif
223
224#ifdef CONFIG_CPU_S5P6450
225void __init s5p6450_map_io(void)
226{
227 /* initialize any device information early */
228 s3c_adc_setname("s3c64xx-adc");
229 s3c_fb_setname("s5p64x0-fb");
230 s3c64xx_spi_setname("s5p64x0-spi");
231
232 s5p64x0_default_sdhci0();
233 s5p64x0_default_sdhci1();
234 s5p6450_default_sdhci2();
235
236 iotable_init(s5p6450_iodesc, ARRAY_SIZE(s5p6450_iodesc));
237}
238#endif
239
240/*
241 * s5p64x0_init_clocks
242 *
243 * register and setup the CPU clocks
244 */
245#ifdef CONFIG_CPU_S5P6440
246void __init s5p6440_init_clocks(int xtal)
247{
248 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
249
250 s3c24xx_register_baseclocks(xtal);
251 s5p_register_clocks(xtal);
252 s5p6440_register_clocks();
253 s5p6440_setup_clocks();
254}
255#endif
256
257#ifdef CONFIG_CPU_S5P6450
258void __init s5p6450_init_clocks(int xtal)
259{
260 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
261
262 s3c24xx_register_baseclocks(xtal);
263 s5p_register_clocks(xtal);
264 s5p6450_register_clocks();
265 s5p6450_setup_clocks();
266}
267#endif
268
269/*
270 * s5p64x0_init_irq
271 *
272 * register the CPU interrupts
273 */
274#ifdef CONFIG_CPU_S5P6440
275void __init s5p6440_init_irq(void)
276{
277 /* S5P6440 supports 2 VIC */
278 u32 vic[2];
279
280 /*
281 * VIC0 is missing IRQ_VIC0[3, 4, 8, 10, (12-22)]
282 * VIC1 is missing IRQ VIC1[1, 3, 4, 10, 11, 12, 14, 15, 22]
283 */
284 vic[0] = 0xff800ae7;
285 vic[1] = 0xffbf23e5;
286
287 s5p_init_irq(vic, ARRAY_SIZE(vic));
288}
289#endif
290
291#ifdef CONFIG_CPU_S5P6450
292void __init s5p6450_init_irq(void)
293{
294 /* S5P6450 supports only 2 VIC */
295 u32 vic[2];
296
297 /*
298 * VIC0 is missing IRQ_VIC0[(13-15), (21-22)]
299 * VIC1 is missing IRQ VIC1[12, 14, 23]
300 */
301 vic[0] = 0xff9f1fff;
302 vic[1] = 0xff7fafff;
303
304 s5p_init_irq(vic, ARRAY_SIZE(vic));
305}
306#endif
307
308struct bus_type s5p64x0_subsys = {
309 .name = "s5p64x0-core",
310 .dev_name = "s5p64x0-core",
311};
312
313static struct device s5p64x0_dev = {
314 .bus = &s5p64x0_subsys,
315};
316
317static int __init s5p64x0_core_init(void)
318{
319 return subsys_system_register(&s5p64x0_subsys, NULL);
320}
321core_initcall(s5p64x0_core_init);
322
323int __init s5p64x0_init(void)
324{
325 printk(KERN_INFO "S5P64X0(S5P6440/S5P6450): Initializing architecture\n");
326
327 /* set idle function */
328 arm_pm_idle = s5p64x0_idle;
329
330 return device_register(&s5p64x0_dev);
331}
332
333/* uart registration process */
334#ifdef CONFIG_CPU_S5P6440
335void __init s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no)
336{
337 int uart;
338
339 for (uart = 0; uart < no; uart++) {
340 s5p_uart_resources[uart].resources->start = S5P6440_PA_UART(uart);
341 s5p_uart_resources[uart].resources->end = S5P6440_PA_UART(uart) + S5P_SZ_UART;
342 }
343
344 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
345}
346#endif
347
348#ifdef CONFIG_CPU_S5P6450
349void __init s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no)
350{
351 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
352}
353#endif
354
355#define eint_offset(irq) ((irq) - IRQ_EINT(0))
356
357static int s5p64x0_irq_eint_set_type(struct irq_data *data, unsigned int type)
358{
359 int offs = eint_offset(data->irq);
360 int shift;
361 u32 ctrl, mask;
362 u32 newvalue = 0;
363
364 if (offs > 15)
365 return -EINVAL;
366
367 switch (type) {
368 case IRQ_TYPE_NONE:
369 printk(KERN_WARNING "No edge setting!\n");
370 break;
371 case IRQ_TYPE_EDGE_RISING:
372 newvalue = S3C2410_EXTINT_RISEEDGE;
373 break;
374 case IRQ_TYPE_EDGE_FALLING:
375 newvalue = S3C2410_EXTINT_FALLEDGE;
376 break;
377 case IRQ_TYPE_EDGE_BOTH:
378 newvalue = S3C2410_EXTINT_BOTHEDGE;
379 break;
380 case IRQ_TYPE_LEVEL_LOW:
381 newvalue = S3C2410_EXTINT_LOWLEV;
382 break;
383 case IRQ_TYPE_LEVEL_HIGH:
384 newvalue = S3C2410_EXTINT_HILEV;
385 break;
386 default:
387 printk(KERN_ERR "No such irq type %d", type);
388 return -EINVAL;
389 }
390
391 shift = (offs / 2) * 4;
392 mask = 0x7 << shift;
393
394 ctrl = __raw_readl(S5P64X0_EINT0CON0) & ~mask;
395 ctrl |= newvalue << shift;
396 __raw_writel(ctrl, S5P64X0_EINT0CON0);
397
398 /* Configure the GPIO pin for 6450 or 6440 based on CPU ID */
399 if (soc_is_s5p6450())
400 s3c_gpio_cfgpin(S5P6450_GPN(offs), S3C_GPIO_SFN(2));
401 else
402 s3c_gpio_cfgpin(S5P6440_GPN(offs), S3C_GPIO_SFN(2));
403
404 return 0;
405}
406
407/*
408 * s5p64x0_irq_demux_eint
409 *
410 * This function demuxes the IRQ from the group0 external interrupts,
411 * from IRQ_EINT(0) to IRQ_EINT(15). It is designed to be inlined into
412 * the specific handlers s5p64x0_irq_demux_eintX_Y.
413 */
414static inline void s5p64x0_irq_demux_eint(unsigned int start, unsigned int end)
415{
416 u32 status = __raw_readl(S5P64X0_EINT0PEND);
417 u32 mask = __raw_readl(S5P64X0_EINT0MASK);
418 unsigned int irq;
419
420 status &= ~mask;
421 status >>= start;
422 status &= (1 << (end - start + 1)) - 1;
423
424 for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
425 if (status & 1)
426 generic_handle_irq(irq);
427 status >>= 1;
428 }
429}
430
431static void s5p64x0_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
432{
433 s5p64x0_irq_demux_eint(0, 3);
434}
435
436static void s5p64x0_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
437{
438 s5p64x0_irq_demux_eint(4, 11);
439}
440
441static void s5p64x0_irq_demux_eint12_15(unsigned int irq,
442 struct irq_desc *desc)
443{
444 s5p64x0_irq_demux_eint(12, 15);
445}
446
447static int s5p64x0_alloc_gc(void)
448{
449 struct irq_chip_generic *gc;
450 struct irq_chip_type *ct;
451
452 gc = irq_alloc_generic_chip("s5p64x0-eint", 1, S5P_IRQ_EINT_BASE,
453 S5P_VA_GPIO, handle_level_irq);
454 if (!gc) {
455 printk(KERN_ERR "%s: irq_alloc_generic_chip for group 0"
456 "external interrupts failed\n", __func__);
457 return -EINVAL;
458 }
459
460 ct = gc->chip_types;
461 ct->chip.irq_ack = irq_gc_ack_set_bit;
462 ct->chip.irq_mask = irq_gc_mask_set_bit;
463 ct->chip.irq_unmask = irq_gc_mask_clr_bit;
464 ct->chip.irq_set_type = s5p64x0_irq_eint_set_type;
465 ct->chip.irq_set_wake = s3c_irqext_wake;
466 ct->regs.ack = EINT0PEND_OFFSET;
467 ct->regs.mask = EINT0MASK_OFFSET;
468 irq_setup_generic_chip(gc, IRQ_MSK(16), IRQ_GC_INIT_MASK_CACHE,
469 IRQ_NOREQUEST | IRQ_NOPROBE, 0);
470 return 0;
471}
472
473static int __init s5p64x0_init_irq_eint(void)
474{
475 int ret = s5p64x0_alloc_gc();
476 irq_set_chained_handler(IRQ_EINT0_3, s5p64x0_irq_demux_eint0_3);
477 irq_set_chained_handler(IRQ_EINT4_11, s5p64x0_irq_demux_eint4_11);
478 irq_set_chained_handler(IRQ_EINT12_15, s5p64x0_irq_demux_eint12_15);
479
480 return ret;
481}
482arch_initcall(s5p64x0_init_irq_eint);
483
484void s5p64x0_restart(enum reboot_mode mode, const char *cmd)
485{
486 if (mode != REBOOT_SOFT)
487 samsung_wdt_reset();
488
489 soft_restart(0);
490}
diff --git a/arch/arm/mach-s5p64x0/common.h b/arch/arm/mach-s5p64x0/common.h
deleted file mode 100644
index cbe7f3d731d0..000000000000
--- a/arch/arm/mach-s5p64x0/common.h
+++ /dev/null
@@ -1,56 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for S5P64X0 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_S5P64X0_COMMON_H
13#define __ARCH_ARM_MACH_S5P64X0_COMMON_H
14
15#include <linux/reboot.h>
16
17void s5p6440_init_irq(void);
18void s5p6450_init_irq(void);
19void s5p64x0_init_io(struct map_desc *mach_desc, int size);
20
21void s5p6440_register_clocks(void);
22void s5p6440_setup_clocks(void);
23
24void s5p6450_register_clocks(void);
25void s5p6450_setup_clocks(void);
26
27void s5p64x0_restart(enum reboot_mode mode, const char *cmd);
28extern int s5p64x0_init(void);
29
30#ifdef CONFIG_CPU_S5P6440
31
32extern void s5p6440_map_io(void);
33extern void s5p6440_init_clocks(int xtal);
34
35extern void s5p6440_init_uarts(struct s3c2410_uartcfg *cfg, int no);
36
37#else
38#define s5p6440_init_clocks NULL
39#define s5p6440_init_uarts NULL
40#define s5p6440_map_io NULL
41#endif
42
43#ifdef CONFIG_CPU_S5P6450
44
45extern void s5p6450_map_io(void);
46extern void s5p6450_init_clocks(int xtal);
47
48extern void s5p6450_init_uarts(struct s3c2410_uartcfg *cfg, int no);
49
50#else
51#define s5p6450_init_clocks NULL
52#define s5p6450_init_uarts NULL
53#define s5p6450_map_io NULL
54#endif
55
56#endif /* __ARCH_ARM_MACH_S5P64X0_COMMON_H */
diff --git a/arch/arm/mach-s5p64x0/dev-audio.c b/arch/arm/mach-s5p64x0/dev-audio.c
deleted file mode 100644
index 723d4773c323..000000000000
--- a/arch/arm/mach-s5p64x0/dev-audio.c
+++ /dev/null
@@ -1,176 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5p6440_cfg_i2s(struct platform_device *pdev)
23{
24 switch (pdev->id) {
25 case 0:
26 s3c_gpio_cfgpin_range(S5P6440_GPC(4), 2, S3C_GPIO_SFN(5));
27 s3c_gpio_cfgpin(S5P6440_GPC(7), S3C_GPIO_SFN(5));
28 s3c_gpio_cfgpin_range(S5P6440_GPH(6), 4, S3C_GPIO_SFN(5));
29 break;
30 default:
31 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
32 return -EINVAL;
33 }
34
35 return 0;
36}
37
38static struct s3c_audio_pdata s5p6440_i2s_pdata = {
39 .cfg_gpio = s5p6440_cfg_i2s,
40 .type = {
41 .i2s = {
42 .quirks = QUIRK_PRI_6CHAN,
43 },
44 },
45};
46
47static struct resource s5p64x0_i2s0_resource[] = {
48 [0] = DEFINE_RES_MEM(S5P64X0_PA_I2S, SZ_256),
49 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
50 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
51};
52
53struct platform_device s5p6440_device_iis = {
54 .name = "samsung-i2s",
55 .id = 0,
56 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
57 .resource = s5p64x0_i2s0_resource,
58 .dev = {
59 .platform_data = &s5p6440_i2s_pdata,
60 },
61};
62
63static int s5p6450_cfg_i2s(struct platform_device *pdev)
64{
65 switch (pdev->id) {
66 case 0:
67 s3c_gpio_cfgpin_range(S5P6450_GPR(4), 5, S3C_GPIO_SFN(5));
68 s3c_gpio_cfgpin_range(S5P6450_GPR(13), 2, S3C_GPIO_SFN(5));
69 break;
70 case 1:
71 s3c_gpio_cfgpin(S5P6440_GPB(4), S3C_GPIO_SFN(5));
72 s3c_gpio_cfgpin_range(S5P6450_GPC(0), 4, S3C_GPIO_SFN(5));
73 break;
74 case 2:
75 s3c_gpio_cfgpin_range(S5P6450_GPK(0), 5, S3C_GPIO_SFN(5));
76 break;
77 default:
78 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
79 return -EINVAL;
80 }
81
82 return 0;
83}
84
85static struct s3c_audio_pdata s5p6450_i2s0_pdata = {
86 .cfg_gpio = s5p6450_cfg_i2s,
87 .type = {
88 .i2s = {
89 .quirks = QUIRK_PRI_6CHAN,
90 },
91 },
92};
93
94struct platform_device s5p6450_device_iis0 = {
95 .name = "samsung-i2s",
96 .id = 0,
97 .num_resources = ARRAY_SIZE(s5p64x0_i2s0_resource),
98 .resource = s5p64x0_i2s0_resource,
99 .dev = {
100 .platform_data = &s5p6450_i2s0_pdata,
101 },
102};
103
104static struct s3c_audio_pdata s5p6450_i2s_pdata = {
105 .cfg_gpio = s5p6450_cfg_i2s,
106};
107
108static struct resource s5p6450_i2s1_resource[] = {
109 [0] = DEFINE_RES_MEM(S5P6450_PA_I2S1, SZ_256),
110 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
111 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
112};
113
114struct platform_device s5p6450_device_iis1 = {
115 .name = "samsung-i2s",
116 .id = 1,
117 .num_resources = ARRAY_SIZE(s5p6450_i2s1_resource),
118 .resource = s5p6450_i2s1_resource,
119 .dev = {
120 .platform_data = &s5p6450_i2s_pdata,
121 },
122};
123
124static struct resource s5p6450_i2s2_resource[] = {
125 [0] = DEFINE_RES_MEM(S5P6450_PA_I2S2, SZ_256),
126 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
127 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
128};
129
130struct platform_device s5p6450_device_iis2 = {
131 .name = "samsung-i2s",
132 .id = 2,
133 .num_resources = ARRAY_SIZE(s5p6450_i2s2_resource),
134 .resource = s5p6450_i2s2_resource,
135 .dev = {
136 .platform_data = &s5p6450_i2s_pdata,
137 },
138};
139
140/* PCM Controller platform_devices */
141
142static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
143{
144 switch (pdev->id) {
145 case 0:
146 s3c_gpio_cfgpin_range(S5P6440_GPR(6), 3, S3C_GPIO_SFN(2));
147 s3c_gpio_cfgpin_range(S5P6440_GPR(13), 2, S3C_GPIO_SFN(2));
148 break;
149
150 default:
151 printk(KERN_DEBUG "Invalid PCM Controller number!");
152 return -EINVAL;
153 }
154
155 return 0;
156}
157
158static struct s3c_audio_pdata s5p6440_pcm_pdata = {
159 .cfg_gpio = s5p6440_pcm_cfg_gpio,
160};
161
162static struct resource s5p6440_pcm0_resource[] = {
163 [0] = DEFINE_RES_MEM(S5P64X0_PA_PCM, SZ_256),
164 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
165 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
166};
167
168struct platform_device s5p6440_device_pcm = {
169 .name = "samsung-pcm",
170 .id = 0,
171 .num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
172 .resource = s5p6440_pcm0_resource,
173 .dev = {
174 .platform_data = &s5p6440_pcm_pdata,
175 },
176};
diff --git a/arch/arm/mach-s5p64x0/dma.c b/arch/arm/mach-s5p64x0/dma.c
deleted file mode 100644
index 9c4ce085f585..000000000000
--- a/arch/arm/mach-s5p64x0/dma.c
+++ /dev/null
@@ -1,128 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/dma.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22*/
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29
30#include <mach/map.h>
31#include <mach/irqs.h>
32#include <mach/regs-clock.h>
33#include <mach/dma.h>
34
35#include <plat/cpu.h>
36#include <plat/devs.h>
37#include <plat/irqs.h>
38
39static u8 s5p6440_pdma_peri[] = {
40 DMACH_UART0_RX,
41 DMACH_UART0_TX,
42 DMACH_UART1_RX,
43 DMACH_UART1_TX,
44 DMACH_UART2_RX,
45 DMACH_UART2_TX,
46 DMACH_UART3_RX,
47 DMACH_UART3_TX,
48 DMACH_MAX,
49 DMACH_MAX,
50 DMACH_PCM0_TX,
51 DMACH_PCM0_RX,
52 DMACH_I2S0_TX,
53 DMACH_I2S0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI0_RX,
56 DMACH_MAX,
57 DMACH_MAX,
58 DMACH_MAX,
59 DMACH_MAX,
60 DMACH_SPI1_TX,
61 DMACH_SPI1_RX,
62};
63
64static struct dma_pl330_platdata s5p6440_pdma_pdata = {
65 .nr_valid_peri = ARRAY_SIZE(s5p6440_pdma_peri),
66 .peri_id = s5p6440_pdma_peri,
67};
68
69static u8 s5p6450_pdma_peri[] = {
70 DMACH_UART0_RX,
71 DMACH_UART0_TX,
72 DMACH_UART1_RX,
73 DMACH_UART1_TX,
74 DMACH_UART2_RX,
75 DMACH_UART2_TX,
76 DMACH_UART3_RX,
77 DMACH_UART3_TX,
78 DMACH_UART4_RX,
79 DMACH_UART4_TX,
80 DMACH_PCM0_TX,
81 DMACH_PCM0_RX,
82 DMACH_I2S0_TX,
83 DMACH_I2S0_RX,
84 DMACH_SPI0_TX,
85 DMACH_SPI0_RX,
86 DMACH_PCM1_TX,
87 DMACH_PCM1_RX,
88 DMACH_PCM2_TX,
89 DMACH_PCM2_RX,
90 DMACH_SPI1_TX,
91 DMACH_SPI1_RX,
92 DMACH_USI_TX,
93 DMACH_USI_RX,
94 DMACH_MAX,
95 DMACH_I2S1_TX,
96 DMACH_I2S1_RX,
97 DMACH_I2S2_TX,
98 DMACH_I2S2_RX,
99 DMACH_PWM,
100 DMACH_UART5_RX,
101 DMACH_UART5_TX,
102};
103
104static struct dma_pl330_platdata s5p6450_pdma_pdata = {
105 .nr_valid_peri = ARRAY_SIZE(s5p6450_pdma_peri),
106 .peri_id = s5p6450_pdma_peri,
107};
108
109static AMBA_AHB_DEVICE(s5p64x0_pdma, "dma-pl330", 0x00041330,
110 S5P64X0_PA_PDMA, {IRQ_DMA0}, NULL);
111
112static int __init s5p64x0_dma_init(void)
113{
114 if (soc_is_s5p6450()) {
115 dma_cap_set(DMA_SLAVE, s5p6450_pdma_pdata.cap_mask);
116 dma_cap_set(DMA_CYCLIC, s5p6450_pdma_pdata.cap_mask);
117 s5p64x0_pdma_device.dev.platform_data = &s5p6450_pdma_pdata;
118 } else {
119 dma_cap_set(DMA_SLAVE, s5p6440_pdma_pdata.cap_mask);
120 dma_cap_set(DMA_CYCLIC, s5p6440_pdma_pdata.cap_mask);
121 s5p64x0_pdma_device.dev.platform_data = &s5p6440_pdma_pdata;
122 }
123
124 amba_device_register(&s5p64x0_pdma_device, &iomem_resource);
125
126 return 0;
127}
128arch_initcall(s5p64x0_dma_init);
diff --git a/arch/arm/mach-s5p64x0/i2c.h b/arch/arm/mach-s5p64x0/i2c.h
deleted file mode 100644
index 1e5bb4ea200d..000000000000
--- a/arch/arm/mach-s5p64x0/i2c.h
+++ /dev/null
@@ -1,16 +0,0 @@
1/*
2 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * S5P64X0 I2C configuration
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12extern void s5p6440_i2c0_cfg_gpio(struct platform_device *dev);
13extern void s5p6440_i2c1_cfg_gpio(struct platform_device *dev);
14
15extern void s5p6450_i2c0_cfg_gpio(struct platform_device *dev);
16extern void s5p6450_i2c1_cfg_gpio(struct platform_device *dev);
diff --git a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S b/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
deleted file mode 100644
index 8759e7882bcb..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
+++ /dev/null
@@ -1,32 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/debug-macro.S
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11/* pull in the relevant register and map files. */
12
13#include <linux/serial_s3c.h>
14#include <plat/map-base.h>
15#include <plat/map-s5p.h>
16
17 .macro addruart, rp, rv, tmp
18 mov \rp, #0xE0000000
19 orr \rp, \rp, #0x00100000
20 ldr \rp, [\rp, #0x118 ]
21 and \rp, \rp, #0xff000
22 teq \rp, #0x50000 @@ S5P6450
23 ldreq \rp, =0xEC800000
24 movne \rp, #0xEC000000 @@ S5P6440
25 ldrne \rv, = S3C_VA_UART
26#if CONFIG_DEBUG_S3C_UART != 0
27 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
28 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
29#endif
30 .endm
31
32#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5p64x0/include/mach/dma.h b/arch/arm/mach-s5p64x0/include/mach/dma.h
deleted file mode 100644
index 5a622af461d7..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/gpio.h b/arch/arm/mach-s5p64x0/include/mach/gpio.h
deleted file mode 100644
index 06cd3c9b16ac..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/gpio.h
+++ /dev/null
@@ -1,132 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO lib support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_GPIO_H
14#define __ASM_ARCH_GPIO_H __FILE__
15
16/* GPIO bank sizes */
17
18#define S5P6440_GPIO_A_NR (6)
19#define S5P6440_GPIO_B_NR (7)
20#define S5P6440_GPIO_C_NR (8)
21#define S5P6440_GPIO_F_NR (16)
22#define S5P6440_GPIO_G_NR (7)
23#define S5P6440_GPIO_H_NR (10)
24#define S5P6440_GPIO_I_NR (16)
25#define S5P6440_GPIO_J_NR (12)
26#define S5P6440_GPIO_N_NR (16)
27#define S5P6440_GPIO_P_NR (8)
28#define S5P6440_GPIO_R_NR (15)
29
30#define S5P6450_GPIO_A_NR (6)
31#define S5P6450_GPIO_B_NR (7)
32#define S5P6450_GPIO_C_NR (8)
33#define S5P6450_GPIO_D_NR (8)
34#define S5P6450_GPIO_F_NR (16)
35#define S5P6450_GPIO_G_NR (14)
36#define S5P6450_GPIO_H_NR (10)
37#define S5P6450_GPIO_I_NR (16)
38#define S5P6450_GPIO_J_NR (12)
39#define S5P6450_GPIO_K_NR (5)
40#define S5P6450_GPIO_N_NR (16)
41#define S5P6450_GPIO_P_NR (11)
42#define S5P6450_GPIO_Q_NR (14)
43#define S5P6450_GPIO_R_NR (15)
44#define S5P6450_GPIO_S_NR (8)
45
46/* GPIO bank numbers */
47
48/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
49 * space for debugging purposes so that any accidental
50 * change from one gpio bank to another can be caught.
51*/
52
53#define S5P64X0_GPIO_NEXT(__gpio) \
54 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
55
56enum s5p6440_gpio_number {
57 S5P6440_GPIO_A_START = 0,
58 S5P6440_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_A),
59 S5P6440_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_B),
60 S5P6440_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_C),
61 S5P6440_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_F),
62 S5P6440_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_G),
63 S5P6440_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_H),
64 S5P6440_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_I),
65 S5P6440_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_J),
66 S5P6440_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_N),
67 S5P6440_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6440_GPIO_P),
68};
69
70enum s5p6450_gpio_number {
71 S5P6450_GPIO_A_START = 0,
72 S5P6450_GPIO_B_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_A),
73 S5P6450_GPIO_C_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_B),
74 S5P6450_GPIO_D_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_C),
75 S5P6450_GPIO_F_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_D),
76 S5P6450_GPIO_G_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_F),
77 S5P6450_GPIO_H_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_G),
78 S5P6450_GPIO_I_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_H),
79 S5P6450_GPIO_J_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_I),
80 S5P6450_GPIO_K_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_J),
81 S5P6450_GPIO_N_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_K),
82 S5P6450_GPIO_P_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_N),
83 S5P6450_GPIO_Q_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_P),
84 S5P6450_GPIO_R_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_Q),
85 S5P6450_GPIO_S_START = S5P64X0_GPIO_NEXT(S5P6450_GPIO_R),
86};
87
88/* GPIO number definitions */
89
90#define S5P6440_GPA(_nr) (S5P6440_GPIO_A_START + (_nr))
91#define S5P6440_GPB(_nr) (S5P6440_GPIO_B_START + (_nr))
92#define S5P6440_GPC(_nr) (S5P6440_GPIO_C_START + (_nr))
93#define S5P6440_GPF(_nr) (S5P6440_GPIO_F_START + (_nr))
94#define S5P6440_GPG(_nr) (S5P6440_GPIO_G_START + (_nr))
95#define S5P6440_GPH(_nr) (S5P6440_GPIO_H_START + (_nr))
96#define S5P6440_GPI(_nr) (S5P6440_GPIO_I_START + (_nr))
97#define S5P6440_GPJ(_nr) (S5P6440_GPIO_J_START + (_nr))
98#define S5P6440_GPN(_nr) (S5P6440_GPIO_N_START + (_nr))
99#define S5P6440_GPP(_nr) (S5P6440_GPIO_P_START + (_nr))
100#define S5P6440_GPR(_nr) (S5P6440_GPIO_R_START + (_nr))
101
102#define S5P6450_GPA(_nr) (S5P6450_GPIO_A_START + (_nr))
103#define S5P6450_GPB(_nr) (S5P6450_GPIO_B_START + (_nr))
104#define S5P6450_GPC(_nr) (S5P6450_GPIO_C_START + (_nr))
105#define S5P6450_GPD(_nr) (S5P6450_GPIO_D_START + (_nr))
106#define S5P6450_GPF(_nr) (S5P6450_GPIO_F_START + (_nr))
107#define S5P6450_GPG(_nr) (S5P6450_GPIO_G_START + (_nr))
108#define S5P6450_GPH(_nr) (S5P6450_GPIO_H_START + (_nr))
109#define S5P6450_GPI(_nr) (S5P6450_GPIO_I_START + (_nr))
110#define S5P6450_GPJ(_nr) (S5P6450_GPIO_J_START + (_nr))
111#define S5P6450_GPK(_nr) (S5P6450_GPIO_K_START + (_nr))
112#define S5P6450_GPN(_nr) (S5P6450_GPIO_N_START + (_nr))
113#define S5P6450_GPP(_nr) (S5P6450_GPIO_P_START + (_nr))
114#define S5P6450_GPQ(_nr) (S5P6450_GPIO_Q_START + (_nr))
115#define S5P6450_GPR(_nr) (S5P6450_GPIO_R_START + (_nr))
116#define S5P6450_GPS(_nr) (S5P6450_GPIO_S_START + (_nr))
117
118/* the end of the S5P64X0 specific gpios */
119
120#define S5P6440_GPIO_END (S5P6440_GPR(S5P6440_GPIO_R_NR) + 1)
121#define S5P6450_GPIO_END (S5P6450_GPS(S5P6450_GPIO_S_NR) + 1)
122
123#define S5P64X0_GPIO_END (S5P6440_GPIO_END > S5P6450_GPIO_END ? \
124 S5P6440_GPIO_END : S5P6450_GPIO_END)
125
126#define S3C_GPIO_END S5P64X0_GPIO_END
127
128/* define the number of gpios we need to the one after the last GPIO range */
129
130#define ARCH_NR_GPIOS (S5P64X0_GPIO_END + CONFIG_SAMSUNG_GPIO_EXTRA)
131
132#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/hardware.h b/arch/arm/mach-s5p64x0/include/mach/hardware.h
deleted file mode 100644
index d3e87996dd9a..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/hardware.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/hardware.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Hardware support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_HARDWARE_H
14#define __ASM_ARCH_HARDWARE_H __FILE__
15
16/* currently nothing here, placeholder */
17
18#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/irqs.h b/arch/arm/mach-s5p64x0/include/mach/irqs.h
deleted file mode 100644
index 53982db9d259..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/irqs.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/irqs.h
2 *
3 * Copyright 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_IRQS_H
14#define __ASM_ARCH_IRQS_H __FILE__
15
16#include <plat/irqs.h>
17
18/* VIC0 */
19
20#define IRQ_EINT0_3 S5P_IRQ_VIC0(0)
21#define IRQ_EINT4_11 S5P_IRQ_VIC0(1)
22#define IRQ_RTC_TIC S5P_IRQ_VIC0(2)
23#define IRQ_IIS1 S5P_IRQ_VIC0(3) /* for only S5P6450 */
24#define IRQ_IIS2 S5P_IRQ_VIC0(4) /* for only S5P6450 */
25#define IRQ_IIC1 S5P_IRQ_VIC0(5)
26#define IRQ_I2SV40 S5P_IRQ_VIC0(6)
27#define IRQ_GPS S5P_IRQ_VIC0(7) /* for only S5P6450 */
28
29#define IRQ_2D S5P_IRQ_VIC0(11)
30#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(23)
31#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(24)
32#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(25)
33#define IRQ_WDT S5P_IRQ_VIC0(26)
34#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(27)
35#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(28)
36#define IRQ_DISPCON0 S5P_IRQ_VIC0(29)
37#define IRQ_DISPCON1 S5P_IRQ_VIC0(30)
38#define IRQ_DISPCON2 S5P_IRQ_VIC0(31)
39
40/* VIC1 */
41
42#define IRQ_EINT12_15 S5P_IRQ_VIC1(0)
43#define IRQ_PCM0 S5P_IRQ_VIC1(2)
44#define IRQ_PCM1 S5P_IRQ_VIC1(3) /* for only S5P6450 */
45#define IRQ_PCM2 S5P_IRQ_VIC1(4) /* for only S5P6450 */
46#define IRQ_UART0 S5P_IRQ_VIC1(5)
47#define IRQ_UART1 S5P_IRQ_VIC1(6)
48#define IRQ_UART2 S5P_IRQ_VIC1(7)
49#define IRQ_UART3 S5P_IRQ_VIC1(8)
50#define IRQ_DMA0 S5P_IRQ_VIC1(9)
51#define IRQ_UART4 S5P_IRQ_VIC1(10) /* S5P6450 */
52#define IRQ_UART5 S5P_IRQ_VIC1(11) /* S5P6450 */
53#define IRQ_NFC S5P_IRQ_VIC1(13)
54#define IRQ_USI S5P_IRQ_VIC1(15) /* S5P6450 */
55#define IRQ_SPI0 S5P_IRQ_VIC1(16)
56#define IRQ_SPI1 S5P_IRQ_VIC1(17)
57#define IRQ_HSMMC2 S5P_IRQ_VIC1(17) /* Shared */
58#define IRQ_IIC S5P_IRQ_VIC1(18)
59#define IRQ_DISPCON3 S5P_IRQ_VIC1(19)
60#define IRQ_EINT_GROUPS S5P_IRQ_VIC1(21)
61#define IRQ_PMU S5P_IRQ_VIC1(23) /* S5P6440 */
62#define IRQ_HSMMC0 S5P_IRQ_VIC1(24)
63#define IRQ_HSMMC1 S5P_IRQ_VIC1(25)
64#define IRQ_OTG S5P_IRQ_VIC1(26)
65#define IRQ_DSI S5P_IRQ_VIC1(27)
66#define IRQ_RTC_ALARM S5P_IRQ_VIC1(28)
67#define IRQ_TSI S5P_IRQ_VIC1(29)
68#define IRQ_PENDN S5P_IRQ_VIC1(30)
69#define IRQ_TC IRQ_PENDN
70#define IRQ_ADC S5P_IRQ_VIC1(31)
71
72/* UART interrupts, S5P6450 has 5 UARTs */
73#define IRQ_S5P_UART_BASE4 (96)
74#define IRQ_S5P_UART_BASE5 (100)
75
76#define IRQ_S5P_UART_RX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_RXD)
77#define IRQ_S5P_UART_TX4 (IRQ_S5P_UART_BASE4 + UART_IRQ_TXD)
78#define IRQ_S5P_UART_ERR4 (IRQ_S5P_UART_BASE4 + UART_IRQ_ERR)
79
80#define IRQ_S5P_UART_RX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_RXD)
81#define IRQ_S5P_UART_TX5 (IRQ_S5P_UART_BASE5 + UART_IRQ_TXD)
82#define IRQ_S5P_UART_ERR5 (IRQ_S5P_UART_BASE5 + UART_IRQ_ERR)
83
84/* S3C compatibilty defines */
85#define IRQ_S3CUART_RX4 IRQ_S5P_UART_RX4
86#define IRQ_S3CUART_RX5 IRQ_S5P_UART_RX5
87
88#define IRQ_I2S0 IRQ_I2SV40
89
90#define IRQ_LCD_FIFO IRQ_DISPCON0
91#define IRQ_LCD_VSYNC IRQ_DISPCON1
92#define IRQ_LCD_SYSTEM IRQ_DISPCON2
93
94/* S5P6450 EINT feature will be added */
95
96/*
97 * Since the IRQ_EINT(x) are a linear mapping on s5p6440 we just defined
98 * them as an IRQ_EINT(x) macro from S5P_IRQ_EINT_BASE which we place
99 * after the pair of VICs.
100 */
101
102#define S5P_IRQ_EINT_BASE (S5P_IRQ_VIC1(31) + 6)
103
104#define S5P_EINT(x) ((x) + S5P_IRQ_EINT_BASE)
105
106#define S5P_EINT_BASE1 (S5P_IRQ_EINT_BASE)
107/*
108 * S5P6440 has 0-15 external interrupts in group 0. Only these can be used
109 * to wake up from sleep. If request is beyond this range, by mistake, a large
110 * return value for an irq number should be indication of something amiss.
111 */
112#define S5P_EINT_BASE2 (0xf0000000)
113
114/*
115 * Next the external interrupt groups. These are similar to the IRQ_EINT(x)
116 * that they are sourced from the GPIO pins but with a different scheme for
117 * priority and source indication.
118 *
119 * The IRQ_EINT(x) can be thought of as 'group 0' of the available GPIO
120 * interrupts, but for historical reasons they are kept apart from these
121 * next interrupts.
122 *
123 * Use IRQ_EINT_GROUP(group, offset) to get the number for use in the
124 * machine specific support files.
125 */
126
127/* Actually, #6 and #7 are missing in the EINT_GROUP1 */
128#define IRQ_EINT_GROUP1_NR (15)
129#define IRQ_EINT_GROUP2_NR (8)
130#define IRQ_EINT_GROUP5_NR (7)
131#define IRQ_EINT_GROUP6_NR (10)
132/* Actually, #0, #1 and #2 are missing in the EINT_GROUP8 */
133#define IRQ_EINT_GROUP8_NR (11)
134
135#define IRQ_EINT_GROUP_BASE S5P_EINT(16)
136#define IRQ_EINT_GROUP1_BASE (IRQ_EINT_GROUP_BASE + 0)
137#define IRQ_EINT_GROUP2_BASE (IRQ_EINT_GROUP1_BASE + IRQ_EINT_GROUP1_NR)
138#define IRQ_EINT_GROUP5_BASE (IRQ_EINT_GROUP2_BASE + IRQ_EINT_GROUP2_NR)
139#define IRQ_EINT_GROUP6_BASE (IRQ_EINT_GROUP5_BASE + IRQ_EINT_GROUP5_NR)
140#define IRQ_EINT_GROUP8_BASE (IRQ_EINT_GROUP6_BASE + IRQ_EINT_GROUP6_NR)
141
142#define IRQ_EINT_GROUP(grp, x) (IRQ_EINT_GROUP##grp##_BASE + (x))
143
144/* Set the default NR_IRQS */
145
146#define NR_IRQS (IRQ_EINT_GROUP8_BASE + IRQ_EINT_GROUP8_NR + 1)
147
148#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/map.h b/arch/arm/mach-s5p64x0/include/mach/map.h
deleted file mode 100644
index 50a6e96d6389..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/map.h
+++ /dev/null
@@ -1,96 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/map.h
2 *
3 * Copyright (c) 2009-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Memory map definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_MAP_H
14#define __ASM_ARCH_MAP_H __FILE__
15
16#include <plat/map-base.h>
17#include <plat/map-s5p.h>
18
19#define S5P64X0_PA_SDRAM 0x20000000
20
21#define S5P64X0_PA_CHIPID 0xE0000000
22
23#define S5P64X0_PA_SYSCON 0xE0100000
24
25#define S5P64X0_PA_GPIO 0xE0308000
26
27#define S5P64X0_PA_VIC0 0xE4000000
28#define S5P64X0_PA_VIC1 0xE4100000
29
30#define S5P64X0_PA_SROMC 0xE7000000
31
32#define S5P64X0_PA_PDMA 0xE9000000
33
34#define S5P64X0_PA_TIMER 0xEA000000
35#define S5P64X0_PA_RTC 0xEA100000
36#define S5P64X0_PA_WDT 0xEA200000
37
38#define S5P6440_PA_IIC0 0xEC104000
39#define S5P6440_PA_IIC1 0xEC20F000
40#define S5P6450_PA_IIC0 0xEC100000
41#define S5P6450_PA_IIC1 0xEC200000
42
43#define S5P64X0_PA_SPI0 0xEC400000
44#define S5P64X0_PA_SPI1 0xEC500000
45
46#define S5P64X0_PA_HSOTG 0xED100000
47
48#define S5P64X0_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
49
50#define S5P64X0_PA_FB 0xEE000000
51
52#define S5P64X0_PA_I2S 0xF2000000
53#define S5P6450_PA_I2S1 0xF2800000
54#define S5P6450_PA_I2S2 0xF2900000
55
56#define S5P64X0_PA_PCM 0xF2100000
57
58#define S5P64X0_PA_ADC 0xF3000000
59
60/* Compatibiltiy Defines */
61
62#define S3C_PA_HSMMC0 S5P64X0_PA_HSMMC(0)
63#define S3C_PA_HSMMC1 S5P64X0_PA_HSMMC(1)
64#define S3C_PA_HSMMC2 S5P64X0_PA_HSMMC(2)
65#define S3C_PA_IIC S5P6440_PA_IIC0
66#define S3C_PA_IIC1 S5P6440_PA_IIC1
67#define S3C_PA_RTC S5P64X0_PA_RTC
68#define S3C_PA_WDT S5P64X0_PA_WDT
69#define S3C_PA_FB S5P64X0_PA_FB
70#define S3C_PA_SPI0 S5P64X0_PA_SPI0
71#define S3C_PA_SPI1 S5P64X0_PA_SPI1
72
73#define S5P_PA_CHIPID S5P64X0_PA_CHIPID
74#define S5P_PA_SROMC S5P64X0_PA_SROMC
75#define S5P_PA_SYSCON S5P64X0_PA_SYSCON
76#define S5P_PA_TIMER S5P64X0_PA_TIMER
77
78#define SAMSUNG_PA_ADC S5P64X0_PA_ADC
79#define SAMSUNG_PA_TIMER S5P64X0_PA_TIMER
80
81/* UART */
82
83#define S5P6440_PA_UART(x) (0xEC000000 + ((x) * S3C_UART_OFFSET))
84#define S5P6450_PA_UART(x) ((x < 5) ? (0xEC800000 + ((x) * S3C_UART_OFFSET)) : (0xEC000000))
85
86#define S5P_PA_UART0 S5P6450_PA_UART(0)
87#define S5P_PA_UART1 S5P6450_PA_UART(1)
88#define S5P_PA_UART2 S5P6450_PA_UART(2)
89#define S5P_PA_UART3 S5P6450_PA_UART(3)
90#define S5P_PA_UART4 S5P6450_PA_UART(4)
91#define S5P_PA_UART5 S5P6450_PA_UART(5)
92
93#define S5P_SZ_UART SZ_256
94#define S3C_VA_UARTx(x) (S3C_VA_UART + ((x) * S3C_UART_OFFSET))
95
96#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/pm-core.h b/arch/arm/mach-s5p64x0/include/mach/pm-core.h
deleted file mode 100644
index 1e0eb65b2b82..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/pm-core.h
+++ /dev/null
@@ -1,119 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/pm-core.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - PM core support for arch/arm/plat-samsung/pm.c
7 *
8 * Based on PM core support for S3C64XX by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/serial_s3c.h>
16
17#include <mach/regs-gpio.h>
18
19static inline void s3c_pm_debug_init_uart(void)
20{
21 u32 tmp = __raw_readl(S5P64X0_CLK_GATE_PCLK);
22
23 /*
24 * As a note, since the S5P64X0 UARTs generally have multiple
25 * clock sources, we simply enable PCLK at the moment and hope
26 * that the resume settings for the UART are suitable for the
27 * use with PCLK.
28 */
29 tmp |= S5P64X0_CLK_GATE_PCLK_UART0;
30 tmp |= S5P64X0_CLK_GATE_PCLK_UART1;
31 tmp |= S5P64X0_CLK_GATE_PCLK_UART2;
32 tmp |= S5P64X0_CLK_GATE_PCLK_UART3;
33
34 __raw_writel(tmp, S5P64X0_CLK_GATE_PCLK);
35 udelay(10);
36}
37
38static inline void s3c_pm_arch_prepare_irqs(void)
39{
40 /* VIC should have already been taken care of */
41
42 /* clear any pending EINT0 interrupts */
43 __raw_writel(__raw_readl(S5P64X0_EINT0PEND), S5P64X0_EINT0PEND);
44}
45
46static inline void s3c_pm_arch_stop_clocks(void) { }
47static inline void s3c_pm_arch_show_resume_irqs(void) { }
48
49/*
50 * make these defines, we currently do not have any need to change
51 * the IRQ wake controls depending on the CPU we are running on
52 */
53#define s3c_irqwake_eintallow ((1 << 16) - 1)
54#define s3c_irqwake_intallow (~0)
55
56static inline void s3c_pm_arch_update_uart(void __iomem *regs,
57 struct pm_uart_save *save)
58{
59 u32 ucon = __raw_readl(regs + S3C2410_UCON);
60 u32 ucon_clk = ucon & S3C6400_UCON_CLKMASK;
61 u32 save_clk = save->ucon & S3C6400_UCON_CLKMASK;
62 u32 new_ucon;
63 u32 delta;
64
65 /*
66 * S5P64X0 UART blocks only support level interrupts, so ensure that
67 * when we restore unused UART blocks we force the level interrupt
68 * settings.
69 */
70 save->ucon |= S3C2410_UCON_TXILEVEL | S3C2410_UCON_RXILEVEL;
71
72 /*
73 * We have a constraint on changing the clock type of the UART
74 * between UCLKx and PCLK, so ensure that when we restore UCON
75 * that the CLK field is correctly modified if the bootloader
76 * has changed anything.
77 */
78 if (ucon_clk != save_clk) {
79 new_ucon = save->ucon;
80 delta = ucon_clk ^ save_clk;
81
82 /*
83 * change from UCLKx => wrong PCLK,
84 * either UCLK can be tested for by a bit-test
85 * with UCLK0
86 */
87 if (ucon_clk & S3C6400_UCON_UCLK0 &&
88 !(save_clk & S3C6400_UCON_UCLK0) &&
89 delta & S3C6400_UCON_PCLK2) {
90 new_ucon &= ~S3C6400_UCON_UCLK0;
91 } else if (delta == S3C6400_UCON_PCLK2) {
92 /*
93 * as a precaution, don't change from
94 * PCLK2 => PCLK or vice-versa
95 */
96 new_ucon ^= S3C6400_UCON_PCLK2;
97 }
98
99 S3C_PMDBG("ucon change %04x => %04x (save=%04x)\n",
100 ucon, new_ucon, save->ucon);
101 save->ucon = new_ucon;
102 }
103}
104
105static inline void s3c_pm_restored_gpios(void)
106{
107 /* ensure sleep mode has been cleared from the system */
108 __raw_writel(0, S5P64X0_SLPEN);
109}
110
111static inline void samsung_pm_saved_gpios(void)
112{
113 /*
114 * turn on the sleep mode and keep it there, as it seems that during
115 * suspend the xCON registers get re-set and thus you can end up with
116 * problems between going to sleep and resuming.
117 */
118 __raw_writel(S5P64X0_SLPEN_USE_xSLP, S5P64X0_SLPEN);
119}
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h b/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
deleted file mode 100644
index bd91112c813c..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
+++ /dev/null
@@ -1,98 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5P64X0_APLL_CON S5P_CLKREG(0x0C)
21#define S5P64X0_MPLL_CON S5P_CLKREG(0x10)
22#define S5P64X0_EPLL_CON S5P_CLKREG(0x14)
23#define S5P64X0_EPLL_CON_K S5P_CLKREG(0x18)
24
25#define S5P64X0_CLK_SRC0 S5P_CLKREG(0x1C)
26
27#define S5P64X0_CLK_DIV0 S5P_CLKREG(0x20)
28#define S5P64X0_CLK_DIV1 S5P_CLKREG(0x24)
29#define S5P64X0_CLK_DIV2 S5P_CLKREG(0x28)
30
31#define S5P64X0_CLK_GATE_HCLK0 S5P_CLKREG(0x30)
32#define S5P64X0_CLK_GATE_PCLK S5P_CLKREG(0x34)
33#define S5P64X0_CLK_GATE_SCLK0 S5P_CLKREG(0x38)
34#define S5P64X0_CLK_GATE_MEM0 S5P_CLKREG(0x3C)
35
36#define S5P64X0_CLK_DIV3 S5P_CLKREG(0x40)
37
38#define S5P64X0_CLK_GATE_HCLK1 S5P_CLKREG(0x44)
39#define S5P64X0_CLK_GATE_SCLK1 S5P_CLKREG(0x48)
40
41#define S5P6450_DPLL_CON S5P_CLKREG(0x50)
42#define S5P6450_DPLL_CON_K S5P_CLKREG(0x54)
43
44#define S5P64X0_AHB_CON0 S5P_CLKREG(0x100)
45#define S5P64X0_CLK_SRC1 S5P_CLKREG(0x10C)
46
47#define S5P64X0_SYS_ID S5P_CLKREG(0x118)
48#define S5P64X0_SYS_OTHERS S5P_CLKREG(0x11C)
49
50#define S5P64X0_PWR_CFG S5P_CLKREG(0x804)
51#define S5P64X0_EINT_WAKEUP_MASK S5P_CLKREG(0x808)
52#define S5P64X0_SLEEP_CFG S5P_CLKREG(0x818)
53#define S5P64X0_PWR_STABLE S5P_CLKREG(0x828)
54
55#define S5P64X0_OTHERS S5P_CLKREG(0x900)
56#define S5P64X0_WAKEUP_STAT S5P_CLKREG(0x908)
57
58#define S5P64X0_INFORM0 S5P_CLKREG(0xA00)
59
60#define S5P64X0_CLKDIV0_HCLK_SHIFT (8)
61#define S5P64X0_CLKDIV0_HCLK_MASK (0xF << S5P64X0_CLKDIV0_HCLK_SHIFT)
62
63/* HCLK GATE Registers */
64#define S5P64X0_CLK_GATE_HCLK1_FIMGVG (1 << 2)
65#define S5P64X0_CLK_GATE_SCLK1_FIMGVG (1 << 2)
66
67/* PCLK GATE Registers */
68#define S5P64X0_CLK_GATE_PCLK_UART3 (1 << 4)
69#define S5P64X0_CLK_GATE_PCLK_UART2 (1 << 3)
70#define S5P64X0_CLK_GATE_PCLK_UART1 (1 << 2)
71#define S5P64X0_CLK_GATE_PCLK_UART0 (1 << 1)
72
73#define S5P64X0_PWR_CFG_MMC1_DISABLE (1 << 15)
74#define S5P64X0_PWR_CFG_MMC0_DISABLE (1 << 14)
75#define S5P64X0_PWR_CFG_RTC_TICK_DISABLE (1 << 11)
76#define S5P64X0_PWR_CFG_RTC_ALRM_DISABLE (1 << 10)
77#define S5P64X0_PWR_CFG_WFI_MASK (3 << 5)
78#define S5P64X0_PWR_CFG_WFI_SLEEP (3 << 5)
79
80#define S5P64X0_SLEEP_CFG_OSC_EN (1 << 0)
81
82#define S5P64X0_PWR_STABLE_PWR_CNT_VAL4 (4 << 0)
83
84#define S5P6450_OTHERS_DISABLE_INT (1 << 31)
85#define S5P64X0_OTHERS_RET_UART (1 << 26)
86#define S5P64X0_OTHERS_RET_MMC1 (1 << 25)
87#define S5P64X0_OTHERS_RET_MMC0 (1 << 24)
88#define S5P64X0_OTHERS_USB_SIG_MASK (1 << 16)
89
90/* Compatibility defines */
91
92#define ARM_CLK_DIV S5P64X0_CLK_DIV0
93#define ARM_DIV_RATIO_SHIFT 0
94#define ARM_DIV_MASK (0xF << ARM_DIV_RATIO_SHIFT)
95
96#define S5P_EPLL_CON S5P64X0_EPLL_CON
97
98#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h b/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
deleted file mode 100644
index cfdfa4fdadf2..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,68 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-gpio.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - GPIO register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_GPIO_H
14#define __ASM_ARCH_REGS_GPIO_H __FILE__
15
16#include <mach/map.h>
17
18/* Base addresses for each of the banks */
19
20#define S5P64X0_GPA_BASE (S5P_VA_GPIO + 0x0000)
21#define S5P64X0_GPB_BASE (S5P_VA_GPIO + 0x0020)
22#define S5P64X0_GPC_BASE (S5P_VA_GPIO + 0x0040)
23#define S5P64X0_GPF_BASE (S5P_VA_GPIO + 0x00A0)
24#define S5P64X0_GPG_BASE (S5P_VA_GPIO + 0x00C0)
25#define S5P64X0_GPH_BASE (S5P_VA_GPIO + 0x00E0)
26#define S5P64X0_GPI_BASE (S5P_VA_GPIO + 0x0100)
27#define S5P64X0_GPJ_BASE (S5P_VA_GPIO + 0x0120)
28#define S5P64X0_GPN_BASE (S5P_VA_GPIO + 0x0830)
29#define S5P64X0_GPP_BASE (S5P_VA_GPIO + 0x0160)
30#define S5P64X0_GPR_BASE (S5P_VA_GPIO + 0x0290)
31
32#define S5P6450_GPD_BASE (S5P_VA_GPIO + 0x0060)
33#define S5P6450_GPK_BASE (S5P_VA_GPIO + 0x0140)
34#define S5P6450_GPQ_BASE (S5P_VA_GPIO + 0x0180)
35#define S5P6450_GPS_BASE (S5P_VA_GPIO + 0x0300)
36
37#define S5P64X0_SPCON0 (S5P_VA_GPIO + 0x1A0)
38#define S5P64X0_SPCON0_LCD_SEL_MASK (0x3 << 0)
39#define S5P64X0_SPCON0_LCD_SEL_RGB (0x1 << 0)
40#define S5P64X0_SPCON1 (S5P_VA_GPIO + 0x2B0)
41
42#define S5P64X0_MEM0CONSLP0 (S5P_VA_GPIO + 0x1C0)
43#define S5P64X0_MEM0CONSLP1 (S5P_VA_GPIO + 0x1C4)
44#define S5P64X0_MEM0DRVCON (S5P_VA_GPIO + 0x1D0)
45#define S5P64X0_MEM1DRVCON (S5P_VA_GPIO + 0x1D4)
46
47#define S5P64X0_EINT12CON (S5P_VA_GPIO + 0x200)
48#define S5P64X0_EINT12FLTCON (S5P_VA_GPIO + 0x220)
49#define S5P64X0_EINT12MASK (S5P_VA_GPIO + 0x240)
50
51/* External interrupt control registers for group0 */
52
53#define EINT0CON0_OFFSET (0x900)
54#define EINT0FLTCON0_OFFSET (0x910)
55#define EINT0FLTCON1_OFFSET (0x914)
56#define EINT0MASK_OFFSET (0x920)
57#define EINT0PEND_OFFSET (0x924)
58
59#define S5P64X0_EINT0CON0 (S5P_VA_GPIO + EINT0CON0_OFFSET)
60#define S5P64X0_EINT0FLTCON0 (S5P_VA_GPIO + EINT0FLTCON0_OFFSET)
61#define S5P64X0_EINT0FLTCON1 (S5P_VA_GPIO + EINT0FLTCON1_OFFSET)
62#define S5P64X0_EINT0MASK (S5P_VA_GPIO + EINT0MASK_OFFSET)
63#define S5P64X0_EINT0PEND (S5P_VA_GPIO + EINT0PEND_OFFSET)
64
65#define S5P64X0_SLPEN (S5P_VA_GPIO + 0x930)
66#define S5P64X0_SLPEN_USE_xSLP (1 << 0)
67
68#endif /* __ASM_ARCH_REGS_GPIO_H */
diff --git a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h b/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
deleted file mode 100644
index d60397d1ff40..000000000000
--- a/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/include/mach/regs-irq.h
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5p64x0/irq-pm.c b/arch/arm/mach-s5p64x0/irq-pm.c
deleted file mode 100644
index 2ed921e095dc..000000000000
--- a/arch/arm/mach-s5p64x0/irq-pm.c
+++ /dev/null
@@ -1,98 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/irq-pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 - Interrupt handling Power Management
7 *
8 * Based on arch/arm/mach-s3c64xx/irq-pm.c by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/syscore_ops.h>
16#include <linux/serial_core.h>
17#include <linux/serial_s3c.h>
18#include <linux/io.h>
19
20#include <plat/pm.h>
21
22#include <mach/regs-gpio.h>
23
24static struct sleep_save irq_save[] = {
25 SAVE_ITEM(S5P64X0_EINT0CON0),
26 SAVE_ITEM(S5P64X0_EINT0FLTCON0),
27 SAVE_ITEM(S5P64X0_EINT0FLTCON1),
28 SAVE_ITEM(S5P64X0_EINT0MASK),
29};
30
31static struct irq_grp_save {
32 u32 con;
33 u32 fltcon;
34 u32 mask;
35} eint_grp_save[4];
36
37#ifdef CONFIG_SERIAL_SAMSUNG
38static u32 irq_uart_mask[CONFIG_SERIAL_SAMSUNG_UARTS];
39#endif
40
41static int s5p64x0_irq_pm_suspend(void)
42{
43 struct irq_grp_save *grp = eint_grp_save;
44 int i;
45
46 S3C_PMDBG("%s: suspending IRQs\n", __func__);
47
48 s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save));
49
50#ifdef CONFIG_SERIAL_SAMSUNG
51 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
52 irq_uart_mask[i] = __raw_readl(S3C_VA_UARTx(i) + S3C64XX_UINTM);
53#endif
54
55 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
56 grp->con = __raw_readl(S5P64X0_EINT12CON + (i * 4));
57 grp->mask = __raw_readl(S5P64X0_EINT12MASK + (i * 4));
58 grp->fltcon = __raw_readl(S5P64X0_EINT12FLTCON + (i * 4));
59 }
60
61 return 0;
62}
63
64static void s5p64x0_irq_pm_resume(void)
65{
66 struct irq_grp_save *grp = eint_grp_save;
67 int i;
68
69 S3C_PMDBG("%s: resuming IRQs\n", __func__);
70
71 s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save));
72
73#ifdef CONFIG_SERIAL_SAMSUNG
74 for (i = 0; i < CONFIG_SERIAL_SAMSUNG_UARTS; i++)
75 __raw_writel(irq_uart_mask[i], S3C_VA_UARTx(i) + S3C64XX_UINTM);
76#endif
77
78 for (i = 0; i < ARRAY_SIZE(eint_grp_save); i++, grp++) {
79 __raw_writel(grp->con, S5P64X0_EINT12CON + (i * 4));
80 __raw_writel(grp->mask, S5P64X0_EINT12MASK + (i * 4));
81 __raw_writel(grp->fltcon, S5P64X0_EINT12FLTCON + (i * 4));
82 }
83
84 S3C_PMDBG("%s: IRQ configuration restored\n", __func__);
85}
86
87static struct syscore_ops s5p64x0_irq_syscore_ops = {
88 .suspend = s5p64x0_irq_pm_suspend,
89 .resume = s5p64x0_irq_pm_resume,
90};
91
92static int __init s5p64x0_syscore_init(void)
93{
94 register_syscore_ops(&s5p64x0_irq_syscore_ops);
95
96 return 0;
97}
98core_initcall(s5p64x0_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6440.c b/arch/arm/mach-s5p64x0/mach-smdk6440.c
deleted file mode 100644
index 6840e197cb2d..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6440.c
+++ /dev/null
@@ -1,280 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6440.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/serial_s3c.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/gpio.h>
26#include <linux/pwm_backlight.h>
27#include <linux/fb.h>
28#include <linux/mmc/host.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/hardware.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/gpio-cfg.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <plat/pll.h>
49#include <plat/adc.h>
50#include <linux/platform_data/touchscreen-s3c2410.h>
51#include <plat/samsung-time.h>
52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/sdhci.h>
55
56#include "common.h"
57#include "i2c.h"
58
59#define SMDK6440_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDK6440_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDK6440_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_TXTRIG16 | \
70 S3C2410_UFCON_RXTRIG8)
71
72static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDK6440_UCON_DEFAULT,
77 .ulcon = SMDK6440_ULCON_DEFAULT,
78 .ufcon = SMDK6440_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDK6440_UCON_DEFAULT,
84 .ulcon = SMDK6440_ULCON_DEFAULT,
85 .ufcon = SMDK6440_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDK6440_UCON_DEFAULT,
91 .ulcon = SMDK6440_ULCON_DEFAULT,
92 .ufcon = SMDK6440_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDK6440_UCON_DEFAULT,
98 .ulcon = SMDK6440_ULCON_DEFAULT,
99 .ufcon = SMDK6440_UFCON_DEFAULT,
100 },
101};
102
103/* Frame Buffer */
104static struct s3c_fb_pd_win smdk6440_fb_win0 = {
105 .max_bpp = 32,
106 .default_bpp = 24,
107 .xres = 800,
108 .yres = 480,
109};
110
111static struct fb_videomode smdk6440_lcd_timing = {
112 .left_margin = 8,
113 .right_margin = 13,
114 .upper_margin = 7,
115 .lower_margin = 5,
116 .hsync_len = 3,
117 .vsync_len = 1,
118 .xres = 800,
119 .yres = 480,
120};
121
122static struct s3c_fb_platdata smdk6440_lcd_pdata __initdata = {
123 .win[0] = &smdk6440_fb_win0,
124 .vtiming = &smdk6440_lcd_timing,
125 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
126 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
127 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
128};
129
130/* LCD power controller */
131static void smdk6440_lte480_reset_power(struct plat_lcd_data *pd,
132 unsigned int power)
133{
134 int err;
135
136 if (power) {
137 err = gpio_request(S5P6440_GPN(5), "GPN");
138 if (err) {
139 printk(KERN_ERR "failed to request GPN for lcd reset\n");
140 return;
141 }
142
143 gpio_direction_output(S5P6440_GPN(5), 1);
144 gpio_set_value(S5P6440_GPN(5), 0);
145 gpio_set_value(S5P6440_GPN(5), 1);
146 gpio_free(S5P6440_GPN(5));
147 }
148}
149
150static struct plat_lcd_data smdk6440_lcd_power_data = {
151 .set_power = smdk6440_lte480_reset_power,
152};
153
154static struct platform_device smdk6440_lcd_lte480wv = {
155 .name = "platform-lcd",
156 .dev.parent = &s3c_device_fb.dev,
157 .dev.platform_data = &smdk6440_lcd_power_data,
158};
159
160static struct platform_device *smdk6440_devices[] __initdata = {
161 &s3c_device_adc,
162 &s3c_device_rtc,
163 &s3c_device_i2c0,
164 &s3c_device_i2c1,
165 &samsung_device_pwm,
166 &s3c_device_ts,
167 &s3c_device_wdt,
168 &s5p6440_device_iis,
169 &s3c_device_fb,
170 &smdk6440_lcd_lte480wv,
171 &s3c_device_hsmmc0,
172 &s3c_device_hsmmc1,
173 &s3c_device_hsmmc2,
174};
175
176static struct s3c_sdhci_platdata smdk6440_hsmmc0_pdata __initdata = {
177 .cd_type = S3C_SDHCI_CD_NONE,
178};
179
180static struct s3c_sdhci_platdata smdk6440_hsmmc1_pdata __initdata = {
181 .cd_type = S3C_SDHCI_CD_INTERNAL,
182#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
183 .max_width = 8,
184 .host_caps = MMC_CAP_8_BIT_DATA,
185#endif
186};
187
188static struct s3c_sdhci_platdata smdk6440_hsmmc2_pdata __initdata = {
189 .cd_type = S3C_SDHCI_CD_NONE,
190};
191
192static struct s3c2410_platform_i2c s5p6440_i2c0_data __initdata = {
193 .flags = 0,
194 .slave_addr = 0x10,
195 .frequency = 100*1000,
196 .sda_delay = 100,
197 .cfg_gpio = s5p6440_i2c0_cfg_gpio,
198};
199
200static struct s3c2410_platform_i2c s5p6440_i2c1_data __initdata = {
201 .flags = 0,
202 .bus_num = 1,
203 .slave_addr = 0x10,
204 .frequency = 100*1000,
205 .sda_delay = 100,
206 .cfg_gpio = s5p6440_i2c1_cfg_gpio,
207};
208
209static struct i2c_board_info smdk6440_i2c_devs0[] __initdata = {
210 { I2C_BOARD_INFO("24c08", 0x50), },
211 { I2C_BOARD_INFO("wm8580", 0x1b), },
212};
213
214static struct i2c_board_info smdk6440_i2c_devs1[] __initdata = {
215 /* To be populated */
216};
217
218/* LCD Backlight data */
219static struct samsung_bl_gpio_info smdk6440_bl_gpio_info = {
220 .no = S5P6440_GPF(15),
221 .func = S3C_GPIO_SFN(2),
222};
223
224static struct platform_pwm_backlight_data smdk6440_bl_data = {
225 .pwm_id = 1,
226 .enable_gpio = -1,
227};
228
229static void __init smdk6440_map_io(void)
230{
231 s5p64x0_init_io(NULL, 0);
232 s3c24xx_init_clocks(12000000);
233 s3c24xx_init_uarts(smdk6440_uartcfgs, ARRAY_SIZE(smdk6440_uartcfgs));
234 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
235}
236
237static void s5p6440_set_lcd_interface(void)
238{
239 unsigned int cfg;
240
241 /* select TFT LCD type (RGB I/F) */
242 cfg = __raw_readl(S5P64X0_SPCON0);
243 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
244 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
245 __raw_writel(cfg, S5P64X0_SPCON0);
246}
247
248static void __init smdk6440_machine_init(void)
249{
250 s3c24xx_ts_set_platdata(NULL);
251
252 s3c_i2c0_set_platdata(&s5p6440_i2c0_data);
253 s3c_i2c1_set_platdata(&s5p6440_i2c1_data);
254 i2c_register_board_info(0, smdk6440_i2c_devs0,
255 ARRAY_SIZE(smdk6440_i2c_devs0));
256 i2c_register_board_info(1, smdk6440_i2c_devs1,
257 ARRAY_SIZE(smdk6440_i2c_devs1));
258
259 s5p6440_set_lcd_interface();
260 s3c_fb_set_platdata(&smdk6440_lcd_pdata);
261
262 s3c_sdhci0_set_platdata(&smdk6440_hsmmc0_pdata);
263 s3c_sdhci1_set_platdata(&smdk6440_hsmmc1_pdata);
264 s3c_sdhci2_set_platdata(&smdk6440_hsmmc2_pdata);
265
266 platform_add_devices(smdk6440_devices, ARRAY_SIZE(smdk6440_devices));
267
268 samsung_bl_set(&smdk6440_bl_gpio_info, &smdk6440_bl_data);
269}
270
271MACHINE_START(SMDK6440, "SMDK6440")
272 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
273 .atag_offset = 0x100,
274
275 .init_irq = s5p6440_init_irq,
276 .map_io = smdk6440_map_io,
277 .init_machine = smdk6440_machine_init,
278 .init_time = samsung_timer_init,
279 .restart = s5p64x0_restart,
280MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/mach-smdk6450.c b/arch/arm/mach-s5p64x0/mach-smdk6450.c
deleted file mode 100644
index fa1341c074ca..000000000000
--- a/arch/arm/mach-s5p64x0/mach-smdk6450.c
+++ /dev/null
@@ -1,299 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/mach-smdk6450.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9*/
10
11#include <linux/kernel.h>
12#include <linux/types.h>
13#include <linux/interrupt.h>
14#include <linux/list.h>
15#include <linux/timer.h>
16#include <linux/delay.h>
17#include <linux/init.h>
18#include <linux/i2c.h>
19#include <linux/serial_core.h>
20#include <linux/serial_s3c.h>
21#include <linux/platform_device.h>
22#include <linux/io.h>
23#include <linux/module.h>
24#include <linux/clk.h>
25#include <linux/gpio.h>
26#include <linux/pwm_backlight.h>
27#include <linux/fb.h>
28#include <linux/mmc/host.h>
29
30#include <video/platform_lcd.h>
31#include <video/samsung_fimd.h>
32
33#include <asm/mach/arch.h>
34#include <asm/mach/map.h>
35#include <asm/irq.h>
36#include <asm/mach-types.h>
37
38#include <mach/hardware.h>
39#include <mach/map.h>
40#include <mach/regs-clock.h>
41#include <mach/regs-gpio.h>
42
43#include <plat/gpio-cfg.h>
44#include <plat/clock.h>
45#include <plat/devs.h>
46#include <plat/cpu.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <plat/pll.h>
49#include <plat/adc.h>
50#include <linux/platform_data/touchscreen-s3c2410.h>
51#include <plat/samsung-time.h>
52#include <plat/backlight.h>
53#include <plat/fb.h>
54#include <plat/sdhci.h>
55
56#include "common.h"
57#include "i2c.h"
58
59#define SMDK6450_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDK6450_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDK6450_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_TXTRIG16 | \
70 S3C2410_UFCON_RXTRIG8)
71
72static struct s3c2410_uartcfg smdk6450_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDK6450_UCON_DEFAULT,
77 .ulcon = SMDK6450_ULCON_DEFAULT,
78 .ufcon = SMDK6450_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDK6450_UCON_DEFAULT,
84 .ulcon = SMDK6450_ULCON_DEFAULT,
85 .ufcon = SMDK6450_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDK6450_UCON_DEFAULT,
91 .ulcon = SMDK6450_ULCON_DEFAULT,
92 .ufcon = SMDK6450_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDK6450_UCON_DEFAULT,
98 .ulcon = SMDK6450_ULCON_DEFAULT,
99 .ufcon = SMDK6450_UFCON_DEFAULT,
100 },
101#if CONFIG_SERIAL_SAMSUNG_UARTS > 4
102 [4] = {
103 .hwport = 4,
104 .flags = 0,
105 .ucon = SMDK6450_UCON_DEFAULT,
106 .ulcon = SMDK6450_ULCON_DEFAULT,
107 .ufcon = SMDK6450_UFCON_DEFAULT,
108 },
109#endif
110#if CONFIG_SERIAL_SAMSUNG_UARTS > 5
111 [5] = {
112 .hwport = 5,
113 .flags = 0,
114 .ucon = SMDK6450_UCON_DEFAULT,
115 .ulcon = SMDK6450_ULCON_DEFAULT,
116 .ufcon = SMDK6450_UFCON_DEFAULT,
117 },
118#endif
119};
120
121/* Frame Buffer */
122static struct s3c_fb_pd_win smdk6450_fb_win0 = {
123 .max_bpp = 32,
124 .default_bpp = 24,
125 .xres = 800,
126 .yres = 480,
127};
128
129static struct fb_videomode smdk6450_lcd_timing = {
130 .left_margin = 8,
131 .right_margin = 13,
132 .upper_margin = 7,
133 .lower_margin = 5,
134 .hsync_len = 3,
135 .vsync_len = 1,
136 .xres = 800,
137 .yres = 480,
138};
139
140static struct s3c_fb_platdata smdk6450_lcd_pdata __initdata = {
141 .win[0] = &smdk6450_fb_win0,
142 .vtiming = &smdk6450_lcd_timing,
143 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
144 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
145 .setup_gpio = s5p64x0_fb_gpio_setup_24bpp,
146};
147
148/* LCD power controller */
149static void smdk6450_lte480_reset_power(struct plat_lcd_data *pd,
150 unsigned int power)
151{
152 int err;
153
154 if (power) {
155 err = gpio_request(S5P6450_GPN(5), "GPN");
156 if (err) {
157 printk(KERN_ERR "failed to request GPN for lcd reset\n");
158 return;
159 }
160
161 gpio_direction_output(S5P6450_GPN(5), 1);
162 gpio_set_value(S5P6450_GPN(5), 0);
163 gpio_set_value(S5P6450_GPN(5), 1);
164 gpio_free(S5P6450_GPN(5));
165 }
166}
167
168static struct plat_lcd_data smdk6450_lcd_power_data = {
169 .set_power = smdk6450_lte480_reset_power,
170};
171
172static struct platform_device smdk6450_lcd_lte480wv = {
173 .name = "platform-lcd",
174 .dev.parent = &s3c_device_fb.dev,
175 .dev.platform_data = &smdk6450_lcd_power_data,
176};
177
178static struct platform_device *smdk6450_devices[] __initdata = {
179 &s3c_device_adc,
180 &s3c_device_rtc,
181 &s3c_device_i2c0,
182 &s3c_device_i2c1,
183 &samsung_device_pwm,
184 &s3c_device_ts,
185 &s3c_device_wdt,
186 &s5p6450_device_iis0,
187 &s3c_device_fb,
188 &smdk6450_lcd_lte480wv,
189 &s3c_device_hsmmc0,
190 &s3c_device_hsmmc1,
191 &s3c_device_hsmmc2,
192 /* s5p6450_device_spi0 will be added */
193};
194
195static struct s3c_sdhci_platdata smdk6450_hsmmc0_pdata __initdata = {
196 .cd_type = S3C_SDHCI_CD_NONE,
197};
198
199static struct s3c_sdhci_platdata smdk6450_hsmmc1_pdata __initdata = {
200 .cd_type = S3C_SDHCI_CD_NONE,
201#if defined(CONFIG_S5P64X0_SD_CH1_8BIT)
202 .max_width = 8,
203 .host_caps = MMC_CAP_8_BIT_DATA,
204#endif
205};
206
207static struct s3c_sdhci_platdata smdk6450_hsmmc2_pdata __initdata = {
208 .cd_type = S3C_SDHCI_CD_NONE,
209};
210
211static struct s3c2410_platform_i2c s5p6450_i2c0_data __initdata = {
212 .flags = 0,
213 .slave_addr = 0x10,
214 .frequency = 100*1000,
215 .sda_delay = 100,
216 .cfg_gpio = s5p6450_i2c0_cfg_gpio,
217};
218
219static struct s3c2410_platform_i2c s5p6450_i2c1_data __initdata = {
220 .flags = 0,
221 .bus_num = 1,
222 .slave_addr = 0x10,
223 .frequency = 100*1000,
224 .sda_delay = 100,
225 .cfg_gpio = s5p6450_i2c1_cfg_gpio,
226};
227
228static struct i2c_board_info smdk6450_i2c_devs0[] __initdata = {
229 { I2C_BOARD_INFO("wm8580", 0x1b), },
230 { I2C_BOARD_INFO("24c08", 0x50), }, /* Samsung KS24C080C EEPROM */
231};
232
233static struct i2c_board_info smdk6450_i2c_devs1[] __initdata = {
234 { I2C_BOARD_INFO("24c128", 0x57), },/* Samsung S524AD0XD1 EEPROM */
235};
236
237/* LCD Backlight data */
238static struct samsung_bl_gpio_info smdk6450_bl_gpio_info = {
239 .no = S5P6450_GPF(15),
240 .func = S3C_GPIO_SFN(2),
241};
242
243static struct platform_pwm_backlight_data smdk6450_bl_data = {
244 .pwm_id = 1,
245 .enable_gpio = -1,
246};
247
248static void __init smdk6450_map_io(void)
249{
250 s5p64x0_init_io(NULL, 0);
251 s3c24xx_init_clocks(19200000);
252 s3c24xx_init_uarts(smdk6450_uartcfgs, ARRAY_SIZE(smdk6450_uartcfgs));
253 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
254}
255
256static void s5p6450_set_lcd_interface(void)
257{
258 unsigned int cfg;
259
260 /* select TFT LCD type (RGB I/F) */
261 cfg = __raw_readl(S5P64X0_SPCON0);
262 cfg &= ~S5P64X0_SPCON0_LCD_SEL_MASK;
263 cfg |= S5P64X0_SPCON0_LCD_SEL_RGB;
264 __raw_writel(cfg, S5P64X0_SPCON0);
265}
266
267static void __init smdk6450_machine_init(void)
268{
269 s3c24xx_ts_set_platdata(NULL);
270
271 s3c_i2c0_set_platdata(&s5p6450_i2c0_data);
272 s3c_i2c1_set_platdata(&s5p6450_i2c1_data);
273 i2c_register_board_info(0, smdk6450_i2c_devs0,
274 ARRAY_SIZE(smdk6450_i2c_devs0));
275 i2c_register_board_info(1, smdk6450_i2c_devs1,
276 ARRAY_SIZE(smdk6450_i2c_devs1));
277
278 s5p6450_set_lcd_interface();
279 s3c_fb_set_platdata(&smdk6450_lcd_pdata);
280
281 s3c_sdhci0_set_platdata(&smdk6450_hsmmc0_pdata);
282 s3c_sdhci1_set_platdata(&smdk6450_hsmmc1_pdata);
283 s3c_sdhci2_set_platdata(&smdk6450_hsmmc2_pdata);
284
285 platform_add_devices(smdk6450_devices, ARRAY_SIZE(smdk6450_devices));
286
287 samsung_bl_set(&smdk6450_bl_gpio_info, &smdk6450_bl_data);
288}
289
290MACHINE_START(SMDK6450, "SMDK6450")
291 /* Maintainer: Kukjin Kim <kgene.kim@samsung.com> */
292 .atag_offset = 0x100,
293
294 .init_irq = s5p6450_init_irq,
295 .map_io = smdk6450_map_io,
296 .init_machine = smdk6450_machine_init,
297 .init_time = samsung_timer_init,
298 .restart = s5p64x0_restart,
299MACHINE_END
diff --git a/arch/arm/mach-s5p64x0/pm.c b/arch/arm/mach-s5p64x0/pm.c
deleted file mode 100644
index ec8229cee716..000000000000
--- a/arch/arm/mach-s5p64x0/pm.c
+++ /dev/null
@@ -1,202 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/pm.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5P64X0 Power Management Support
7 *
8 * Based on arch/arm/mach-s3c64xx/pm.c by Ben Dooks
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/suspend.h>
16#include <linux/syscore_ops.h>
17#include <linux/io.h>
18
19#include <plat/cpu.h>
20#include <plat/pm.h>
21#include <plat/wakeup-mask.h>
22
23#include <mach/regs-clock.h>
24#include <mach/regs-gpio.h>
25
26static struct sleep_save s5p64x0_core_save[] = {
27 SAVE_ITEM(S5P64X0_APLL_CON),
28 SAVE_ITEM(S5P64X0_MPLL_CON),
29 SAVE_ITEM(S5P64X0_EPLL_CON),
30 SAVE_ITEM(S5P64X0_EPLL_CON_K),
31 SAVE_ITEM(S5P64X0_CLK_SRC0),
32 SAVE_ITEM(S5P64X0_CLK_SRC1),
33 SAVE_ITEM(S5P64X0_CLK_DIV0),
34 SAVE_ITEM(S5P64X0_CLK_DIV1),
35 SAVE_ITEM(S5P64X0_CLK_DIV2),
36 SAVE_ITEM(S5P64X0_CLK_DIV3),
37 SAVE_ITEM(S5P64X0_CLK_GATE_MEM0),
38 SAVE_ITEM(S5P64X0_CLK_GATE_HCLK1),
39 SAVE_ITEM(S5P64X0_CLK_GATE_SCLK1),
40};
41
42static struct sleep_save s5p64x0_misc_save[] = {
43 SAVE_ITEM(S5P64X0_AHB_CON0),
44 SAVE_ITEM(S5P64X0_SPCON0),
45 SAVE_ITEM(S5P64X0_SPCON1),
46 SAVE_ITEM(S5P64X0_MEM0CONSLP0),
47 SAVE_ITEM(S5P64X0_MEM0CONSLP1),
48 SAVE_ITEM(S5P64X0_MEM0DRVCON),
49 SAVE_ITEM(S5P64X0_MEM1DRVCON),
50};
51
52/* DPLL is present only in S5P6450 */
53static struct sleep_save s5p6450_core_save[] = {
54 SAVE_ITEM(S5P6450_DPLL_CON),
55 SAVE_ITEM(S5P6450_DPLL_CON_K),
56};
57
58void s3c_pm_configure_extint(void)
59{
60 __raw_writel(s3c_irqwake_eintmask, S5P64X0_EINT_WAKEUP_MASK);
61}
62
63void s3c_pm_restore_core(void)
64{
65 __raw_writel(0, S5P64X0_EINT_WAKEUP_MASK);
66
67 s3c_pm_do_restore_core(s5p64x0_core_save,
68 ARRAY_SIZE(s5p64x0_core_save));
69
70 if (soc_is_s5p6450())
71 s3c_pm_do_restore_core(s5p6450_core_save,
72 ARRAY_SIZE(s5p6450_core_save));
73
74 s3c_pm_do_restore(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
75}
76
77void s3c_pm_save_core(void)
78{
79 s3c_pm_do_save(s5p64x0_misc_save, ARRAY_SIZE(s5p64x0_misc_save));
80
81 if (soc_is_s5p6450())
82 s3c_pm_do_save(s5p6450_core_save,
83 ARRAY_SIZE(s5p6450_core_save));
84
85 s3c_pm_do_save(s5p64x0_core_save, ARRAY_SIZE(s5p64x0_core_save));
86}
87
88static int s5p64x0_cpu_suspend(unsigned long arg)
89{
90 unsigned long tmp = 0;
91
92 /*
93 * Issue the standby signal into the pm unit. Note, we
94 * issue a write-buffer drain just in case.
95 */
96 asm("b 1f\n\t"
97 ".align 5\n\t"
98 "1:\n\t"
99 "mcr p15, 0, %0, c7, c10, 5\n\t"
100 "mcr p15, 0, %0, c7, c10, 4\n\t"
101 "mcr p15, 0, %0, c7, c0, 4" : : "r" (tmp));
102
103 pr_info("Failed to suspend the system\n");
104 return 1; /* Aborting suspend */
105}
106
107/* mapping of interrupts to parts of the wakeup mask */
108static struct samsung_wakeup_mask s5p64x0_wake_irqs[] = {
109 { .irq = IRQ_RTC_ALARM, .bit = S5P64X0_PWR_CFG_RTC_ALRM_DISABLE, },
110 { .irq = IRQ_RTC_TIC, .bit = S5P64X0_PWR_CFG_RTC_TICK_DISABLE, },
111 { .irq = IRQ_HSMMC0, .bit = S5P64X0_PWR_CFG_MMC0_DISABLE, },
112 { .irq = IRQ_HSMMC1, .bit = S5P64X0_PWR_CFG_MMC1_DISABLE, },
113};
114
115static void s5p64x0_pm_prepare(void)
116{
117 u32 tmp;
118
119 samsung_sync_wakemask(S5P64X0_PWR_CFG,
120 s5p64x0_wake_irqs, ARRAY_SIZE(s5p64x0_wake_irqs));
121
122 /* store the resume address in INFORM0 register */
123 __raw_writel(virt_to_phys(s3c_cpu_resume), S5P64X0_INFORM0);
124
125 /* setup clock gating for FIMGVG block */
126 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_HCLK1) | \
127 (S5P64X0_CLK_GATE_HCLK1_FIMGVG)), S5P64X0_CLK_GATE_HCLK1);
128 __raw_writel((__raw_readl(S5P64X0_CLK_GATE_SCLK1) | \
129 (S5P64X0_CLK_GATE_SCLK1_FIMGVG)), S5P64X0_CLK_GATE_SCLK1);
130
131 /* Configure the stabilization counter with wait time required */
132 __raw_writel(S5P64X0_PWR_STABLE_PWR_CNT_VAL4, S5P64X0_PWR_STABLE);
133
134 /* set WFI to SLEEP mode configuration */
135 tmp = __raw_readl(S5P64X0_SLEEP_CFG);
136 tmp &= ~(S5P64X0_SLEEP_CFG_OSC_EN);
137 __raw_writel(tmp, S5P64X0_SLEEP_CFG);
138
139 tmp = __raw_readl(S5P64X0_PWR_CFG);
140 tmp &= ~(S5P64X0_PWR_CFG_WFI_MASK);
141 tmp |= S5P64X0_PWR_CFG_WFI_SLEEP;
142 __raw_writel(tmp, S5P64X0_PWR_CFG);
143
144 /*
145 * set OTHERS register to disable interrupt before going to
146 * sleep. This bit is present only in S5P6450, it is reserved
147 * in S5P6440.
148 */
149 if (soc_is_s5p6450()) {
150 tmp = __raw_readl(S5P64X0_OTHERS);
151 tmp |= S5P6450_OTHERS_DISABLE_INT;
152 __raw_writel(tmp, S5P64X0_OTHERS);
153 }
154
155 /* ensure previous wakeup state is cleared before sleeping */
156 __raw_writel(__raw_readl(S5P64X0_WAKEUP_STAT), S5P64X0_WAKEUP_STAT);
157
158}
159
160static int s5p64x0_pm_add(struct device *dev, struct subsys_interface *sif)
161{
162 pm_cpu_prep = s5p64x0_pm_prepare;
163 pm_cpu_sleep = s5p64x0_cpu_suspend;
164
165 return 0;
166}
167
168static struct subsys_interface s5p64x0_pm_interface = {
169 .name = "s5p64x0_pm",
170 .subsys = &s5p64x0_subsys,
171 .add_dev = s5p64x0_pm_add,
172};
173
174static __init int s5p64x0_pm_drvinit(void)
175{
176 s3c_pm_init();
177
178 return subsys_interface_register(&s5p64x0_pm_interface);
179}
180arch_initcall(s5p64x0_pm_drvinit);
181
182static void s5p64x0_pm_resume(void)
183{
184 u32 tmp;
185
186 tmp = __raw_readl(S5P64X0_OTHERS);
187 tmp |= (S5P64X0_OTHERS_RET_MMC0 | S5P64X0_OTHERS_RET_MMC1 | \
188 S5P64X0_OTHERS_RET_UART);
189 __raw_writel(tmp , S5P64X0_OTHERS);
190}
191
192static struct syscore_ops s5p64x0_pm_syscore_ops = {
193 .resume = s5p64x0_pm_resume,
194};
195
196static __init int s5p64x0_pm_syscore_init(void)
197{
198 register_syscore_ops(&s5p64x0_pm_syscore_ops);
199
200 return 0;
201}
202arch_initcall(s5p64x0_pm_syscore_init);
diff --git a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c b/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
deleted file mode 100644
index f346ee4af54d..000000000000
--- a/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
+++ /dev/null
@@ -1,29 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-fb-24bpp.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Base S5P64X0 GPIO setup information for LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/fb.h>
14#include <linux/gpio.h>
15
16#include <plat/cpu.h>
17#include <plat/fb.h>
18#include <plat/gpio-cfg.h>
19
20void s5p64x0_fb_gpio_setup_24bpp(void)
21{
22 if (soc_is_s5p6440()) {
23 s3c_gpio_cfgrange_nopull(S5P6440_GPI(0), 16, S3C_GPIO_SFN(2));
24 s3c_gpio_cfgrange_nopull(S5P6440_GPJ(0), 12, S3C_GPIO_SFN(2));
25 } else if (soc_is_s5p6450()) {
26 s3c_gpio_cfgrange_nopull(S5P6450_GPI(0), 16, S3C_GPIO_SFN(2));
27 s3c_gpio_cfgrange_nopull(S5P6450_GPJ(0), 12, S3C_GPIO_SFN(2));
28 }
29}
diff --git a/arch/arm/mach-s5p64x0/setup-i2c0.c b/arch/arm/mach-s5p64x0/setup-i2c0.c
deleted file mode 100644
index 569b76ac98cb..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c0.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-i2c0.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * I2C0 GPIO configuration.
7 *
8 * Based on plat-s3c64x0/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h>
23
24#include "i2c.h"
25
26void s5p6440_i2c0_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgall_range(S5P6440_GPB(5), 2,
29 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
30}
31
32void s5p6450_i2c0_cfg_gpio(struct platform_device *dev)
33{
34 s3c_gpio_cfgall_range(S5P6450_GPB(5), 2,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36}
37
38void s3c_i2c0_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-i2c1.c b/arch/arm/mach-s5p64x0/setup-i2c1.c
deleted file mode 100644
index 867374e6d0bc..000000000000
--- a/arch/arm/mach-s5p64x0/setup-i2c1.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64xx/setup-i2c1.c
2 *
3 * Copyright (c) 2009-2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * I2C1 GPIO configuration.
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/gpio.h>
18
19struct platform_device; /* don't need the contents */
20
21#include <plat/gpio-cfg.h>
22#include <linux/platform_data/i2c-s3c2410.h>
23
24#include "i2c.h"
25
26void s5p6440_i2c1_cfg_gpio(struct platform_device *dev)
27{
28 s3c_gpio_cfgall_range(S5P6440_GPR(9), 2,
29 S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
30}
31
32void s5p6450_i2c1_cfg_gpio(struct platform_device *dev)
33{
34 s3c_gpio_cfgall_range(S5P6450_GPR(9), 2,
35 S3C_GPIO_SFN(6), S3C_GPIO_PULL_UP);
36}
37
38void s3c_i2c1_cfg_gpio(struct platform_device *dev) { }
diff --git a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c b/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
deleted file mode 100644
index 8410af0d12bf..000000000000
--- a/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,104 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-sdhci-gpio.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5P64X0 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/platform_device.h>
14#include <linux/io.h>
15#include <linux/gpio.h>
16
17#include <mach/regs-gpio.h>
18#include <mach/regs-clock.h>
19
20#include <plat/gpio-cfg.h>
21#include <plat/sdhci.h>
22#include <plat/cpu.h>
23
24void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27
28 /* Set all the necessary GPG pins to special-function 2 */
29 if (soc_is_s5p6450())
30 s3c_gpio_cfgrange_nopull(S5P6450_GPG(0), 2 + width,
31 S3C_GPIO_SFN(2));
32 else
33 s3c_gpio_cfgrange_nopull(S5P6440_GPG(0), 2 + width,
34 S3C_GPIO_SFN(2));
35
36 /* Set GPG[6] pin to special-function 2 - MMC0 CDn */
37 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
38 if (soc_is_s5p6450()) {
39 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
40 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(2));
41 } else {
42 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
43 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(2));
44 }
45 }
46}
47
48void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
49{
50 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
51
52 /* Set GPH[0:1] pins to special-function 2 - CLK and CMD */
53 if (soc_is_s5p6450())
54 s3c_gpio_cfgrange_nopull(S5P6450_GPH(0), 2, S3C_GPIO_SFN(2));
55 else
56 s3c_gpio_cfgrange_nopull(S5P6440_GPH(0), 2 , S3C_GPIO_SFN(2));
57
58 switch (width) {
59 case 8:
60 /* Set data pins GPH[6:9] special-function 2 */
61 if (soc_is_s5p6450())
62 s3c_gpio_cfgrange_nopull(S5P6450_GPH(6), 4,
63 S3C_GPIO_SFN(2));
64 else
65 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4,
66 S3C_GPIO_SFN(2));
67 case 4:
68 /* set data pins GPH[2:5] special-function 2 */
69 if (soc_is_s5p6450())
70 s3c_gpio_cfgrange_nopull(S5P6450_GPH(2), 4,
71 S3C_GPIO_SFN(2));
72 else
73 s3c_gpio_cfgrange_nopull(S5P6440_GPH(2), 4,
74 S3C_GPIO_SFN(2));
75 default:
76 break;
77 }
78
79 /* Set GPG[6] pin to special-funtion 3 : MMC1 CDn */
80 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
81 if (soc_is_s5p6450()) {
82 s3c_gpio_setpull(S5P6450_GPG(6), S3C_GPIO_PULL_UP);
83 s3c_gpio_cfgpin(S5P6450_GPG(6), S3C_GPIO_SFN(3));
84 } else {
85 s3c_gpio_setpull(S5P6440_GPG(6), S3C_GPIO_PULL_UP);
86 s3c_gpio_cfgpin(S5P6440_GPG(6), S3C_GPIO_SFN(3));
87 }
88 }
89}
90
91void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
92{
93 /* Set GPC[4:5] pins to special-function 3 - CLK and CMD */
94 s3c_gpio_cfgrange_nopull(S5P6440_GPC(4), 2, S3C_GPIO_SFN(3));
95
96 /* Set data pins GPH[6:9] pins to special-function 3 */
97 s3c_gpio_cfgrange_nopull(S5P6440_GPH(6), 4, S3C_GPIO_SFN(3));
98}
99
100void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
101{
102 /* Set all the necessary GPG pins to special-function 3 */
103 s3c_gpio_cfgrange_nopull(S5P6450_GPG(7), 2 + width, S3C_GPIO_SFN(3));
104}
diff --git a/arch/arm/mach-s5p64x0/setup-spi.c b/arch/arm/mach-s5p64x0/setup-spi.c
deleted file mode 100644
index 7664356720ca..000000000000
--- a/arch/arm/mach-s5p64x0/setup-spi.c
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/mach-s5p64x0/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 if (soc_is_s5p6450())
18 s3c_gpio_cfgall_range(S5P6450_GPC(0), 3,
19 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
20 else
21 s3c_gpio_cfgall_range(S5P6440_GPC(0), 3,
22 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
23 return 0;
24}
25#endif
26
27#ifdef CONFIG_S3C64XX_DEV_SPI1
28int s3c64xx_spi1_cfg_gpio(void)
29{
30 if (soc_is_s5p6450())
31 s3c_gpio_cfgall_range(S5P6450_GPC(4), 3,
32 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
33 else
34 s3c_gpio_cfgall_range(S5P6440_GPC(4), 3,
35 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
36 return 0;
37}
38#endif
diff --git a/arch/arm/mach-s5pc100/Kconfig b/arch/arm/mach-s5pc100/Kconfig
deleted file mode 100644
index c5e3a969b063..000000000000
--- a/arch/arm/mach-s5pc100/Kconfig
+++ /dev/null
@@ -1,81 +0,0 @@
1# Copyright 2009 Samsung Electronics Co.
2# Byungho Min <bhmin@samsung.com>
3#
4# Licensed under GPLv2
5
6# Configuration options for the S5PC100 CPU
7
8if ARCH_S5PC100
9
10config CPU_S5PC100
11 bool
12 select ARM_AMBA
13 select PL330_DMA if DMADEVICES
14 select S5P_EXT_INT
15 help
16 Enable S5PC100 CPU support
17
18config S5PC100_SETUP_FB_24BPP
19 bool
20 help
21 Common setup code for S5PC1XX with an 24bpp RGB display helper.
22
23config S5PC100_SETUP_I2C1
24 bool
25 help
26 Common setup code for i2c bus 1.
27
28config S5PC100_SETUP_IDE
29 bool
30 help
31 Common setup code for S5PC100 IDE GPIO configurations
32
33config S5PC100_SETUP_KEYPAD
34 bool
35 help
36 Common setup code for KEYPAD GPIO configurations.
37
38config S5PC100_SETUP_SDHCI
39 bool
40 select S5PC100_SETUP_SDHCI_GPIO
41 help
42 Internal helper functions for S5PC100 based SDHCI systems
43
44config S5PC100_SETUP_SDHCI_GPIO
45 bool
46 help
47 Common setup code for SDHCI gpio.
48
49config S5PC100_SETUP_SPI
50 bool
51 help
52 Common setup code for SPI GPIO configurations.
53
54config MACH_SMDKC100
55 bool "SMDKC100"
56 select CPU_S5PC100
57 select S3C_DEV_FB
58 select S3C_DEV_HSMMC
59 select S3C_DEV_HSMMC1
60 select S3C_DEV_HSMMC2
61 select S3C_DEV_I2C1
62 select S3C_DEV_RTC
63 select S3C_DEV_WDT
64 select S5PC100_SETUP_FB_24BPP
65 select S5PC100_SETUP_I2C1
66 select S5PC100_SETUP_IDE
67 select S5PC100_SETUP_KEYPAD
68 select S5PC100_SETUP_SDHCI
69 select S5P_DEV_FIMC0
70 select S5P_DEV_FIMC1
71 select S5P_DEV_FIMC2
72 select SAMSUNG_DEV_ADC
73 select SAMSUNG_DEV_BACKLIGHT
74 select SAMSUNG_DEV_IDE
75 select SAMSUNG_DEV_KEYPAD
76 select SAMSUNG_DEV_PWM
77 select SAMSUNG_DEV_TS
78 help
79 Machine support for the Samsung SMDKC100
80
81endif
diff --git a/arch/arm/mach-s5pc100/Makefile b/arch/arm/mach-s5pc100/Makefile
deleted file mode 100644
index 118c711f74e8..000000000000
--- a/arch/arm/mach-s5pc100/Makefile
+++ /dev/null
@@ -1,32 +0,0 @@
1# arch/arm/mach-s5pc100/Makefile
2#
3# Copyright 2009 Samsung Electronics Co.
4#
5# Licensed under GPLv2
6
7obj-y :=
8obj-m :=
9obj-n :=
10obj- :=
11
12# Core
13
14obj-y += common.o clock.o
15
16obj-y += dma.o
17
18# machine support
19
20obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
21
22# device support
23
24obj-y += dev-audio.o
25
26obj-y += setup-i2c0.o
27obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
28obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
29obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
30obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
31obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
32obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
diff --git a/arch/arm/mach-s5pc100/Makefile.boot b/arch/arm/mach-s5pc100/Makefile.boot
deleted file mode 100644
index 79ece4055b02..000000000000
--- a/arch/arm/mach-s5pc100/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
1 zreladdr-y += 0x20008000
2params_phys-y := 0x20000100
diff --git a/arch/arm/mach-s5pc100/clock.c b/arch/arm/mach-s5pc100/clock.c
deleted file mode 100644
index d0dc10ee7729..000000000000
--- a/arch/arm/mach-s5pc100/clock.c
+++ /dev/null
@@ -1,1361 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/clock.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock support
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/init.h>
14#include <linux/module.h>
15#include <linux/kernel.h>
16#include <linux/list.h>
17#include <linux/err.h>
18#include <linux/clk.h>
19#include <linux/io.h>
20
21#include <mach/map.h>
22
23#include <plat/cpu-freq.h>
24#include <mach/regs-clock.h>
25#include <plat/clock.h>
26#include <plat/cpu.h>
27#include <plat/pll.h>
28#include <plat/s5p-clock.h>
29#include <plat/clock-clksrc.h>
30
31#include "common.h"
32
33static struct clk s5p_clk_otgphy = {
34 .name = "otg_phy",
35};
36
37static struct clk dummy_apb_pclk = {
38 .name = "apb_pclk",
39 .id = -1,
40};
41
42static struct clk *clk_src_mout_href_list[] = {
43 [0] = &s5p_clk_27m,
44 [1] = &clk_fin_hpll,
45};
46
47static struct clksrc_sources clk_src_mout_href = {
48 .sources = clk_src_mout_href_list,
49 .nr_sources = ARRAY_SIZE(clk_src_mout_href_list),
50};
51
52static struct clksrc_clk clk_mout_href = {
53 .clk = {
54 .name = "mout_href",
55 },
56 .sources = &clk_src_mout_href,
57 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 20, .size = 1 },
58};
59
60static struct clk *clk_src_mout_48m_list[] = {
61 [0] = &clk_xusbxti,
62 [1] = &s5p_clk_otgphy,
63};
64
65static struct clksrc_sources clk_src_mout_48m = {
66 .sources = clk_src_mout_48m_list,
67 .nr_sources = ARRAY_SIZE(clk_src_mout_48m_list),
68};
69
70static struct clksrc_clk clk_mout_48m = {
71 .clk = {
72 .name = "mout_48m",
73 },
74 .sources = &clk_src_mout_48m,
75 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 1 },
76};
77
78static struct clksrc_clk clk_mout_mpll = {
79 .clk = {
80 .name = "mout_mpll",
81 },
82 .sources = &clk_src_mpll,
83 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 4, .size = 1 },
84};
85
86
87static struct clksrc_clk clk_mout_apll = {
88 .clk = {
89 .name = "mout_apll",
90 },
91 .sources = &clk_src_apll,
92 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 0, .size = 1 },
93};
94
95static struct clksrc_clk clk_mout_epll = {
96 .clk = {
97 .name = "mout_epll",
98 },
99 .sources = &clk_src_epll,
100 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 8, .size = 1 },
101};
102
103static struct clk *clk_src_mout_hpll_list[] = {
104 [0] = &s5p_clk_27m,
105};
106
107static struct clksrc_sources clk_src_mout_hpll = {
108 .sources = clk_src_mout_hpll_list,
109 .nr_sources = ARRAY_SIZE(clk_src_mout_hpll_list),
110};
111
112static struct clksrc_clk clk_mout_hpll = {
113 .clk = {
114 .name = "mout_hpll",
115 },
116 .sources = &clk_src_mout_hpll,
117 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 12, .size = 1 },
118};
119
120static struct clksrc_clk clk_div_apll = {
121 .clk = {
122 .name = "div_apll",
123 .parent = &clk_mout_apll.clk,
124 },
125 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 0, .size = 1 },
126};
127
128static struct clksrc_clk clk_div_arm = {
129 .clk = {
130 .name = "div_arm",
131 .parent = &clk_div_apll.clk,
132 },
133 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 4, .size = 3 },
134};
135
136static struct clksrc_clk clk_div_d0_bus = {
137 .clk = {
138 .name = "div_d0_bus",
139 .parent = &clk_div_arm.clk,
140 },
141 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 8, .size = 3 },
142};
143
144static struct clksrc_clk clk_div_pclkd0 = {
145 .clk = {
146 .name = "div_pclkd0",
147 .parent = &clk_div_d0_bus.clk,
148 },
149 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 12, .size = 3 },
150};
151
152static struct clksrc_clk clk_div_secss = {
153 .clk = {
154 .name = "div_secss",
155 .parent = &clk_div_d0_bus.clk,
156 },
157 .reg_div = { .reg = S5P_CLK_DIV0, .shift = 16, .size = 3 },
158};
159
160static struct clksrc_clk clk_div_apll2 = {
161 .clk = {
162 .name = "div_apll2",
163 .parent = &clk_mout_apll.clk,
164 },
165 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 0, .size = 3 },
166};
167
168static struct clk *clk_src_mout_am_list[] = {
169 [0] = &clk_mout_mpll.clk,
170 [1] = &clk_div_apll2.clk,
171};
172
173static struct clksrc_sources clk_src_mout_am = {
174 .sources = clk_src_mout_am_list,
175 .nr_sources = ARRAY_SIZE(clk_src_mout_am_list),
176};
177
178static struct clksrc_clk clk_mout_am = {
179 .clk = {
180 .name = "mout_am",
181 },
182 .sources = &clk_src_mout_am,
183 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 16, .size = 1 },
184};
185
186static struct clksrc_clk clk_div_d1_bus = {
187 .clk = {
188 .name = "div_d1_bus",
189 .parent = &clk_mout_am.clk,
190 },
191 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 3 },
192};
193
194static struct clksrc_clk clk_div_mpll2 = {
195 .clk = {
196 .name = "div_mpll2",
197 .parent = &clk_mout_am.clk,
198 },
199 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 8, .size = 1 },
200};
201
202static struct clksrc_clk clk_div_mpll = {
203 .clk = {
204 .name = "div_mpll",
205 .parent = &clk_mout_am.clk,
206 },
207 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 4, .size = 2 },
208};
209
210static struct clk *clk_src_mout_onenand_list[] = {
211 [0] = &clk_div_d0_bus.clk,
212 [1] = &clk_div_d1_bus.clk,
213};
214
215static struct clksrc_sources clk_src_mout_onenand = {
216 .sources = clk_src_mout_onenand_list,
217 .nr_sources = ARRAY_SIZE(clk_src_mout_onenand_list),
218};
219
220static struct clksrc_clk clk_mout_onenand = {
221 .clk = {
222 .name = "mout_onenand",
223 },
224 .sources = &clk_src_mout_onenand,
225 .reg_src = { .reg = S5P_CLK_SRC0, .shift = 24, .size = 1 },
226};
227
228static struct clksrc_clk clk_div_onenand = {
229 .clk = {
230 .name = "div_onenand",
231 .parent = &clk_mout_onenand.clk,
232 },
233 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 2 },
234};
235
236static struct clksrc_clk clk_div_pclkd1 = {
237 .clk = {
238 .name = "div_pclkd1",
239 .parent = &clk_div_d1_bus.clk,
240 },
241 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 3 },
242};
243
244static struct clksrc_clk clk_div_cam = {
245 .clk = {
246 .name = "div_cam",
247 .parent = &clk_div_mpll2.clk,
248 },
249 .reg_div = { .reg = S5P_CLK_DIV1, .shift = 24, .size = 5 },
250};
251
252static struct clksrc_clk clk_div_hdmi = {
253 .clk = {
254 .name = "div_hdmi",
255 .parent = &clk_mout_hpll.clk,
256 },
257 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 28, .size = 4 },
258};
259
260static u32 epll_div[][4] = {
261 { 32750000, 131, 3, 4 },
262 { 32768000, 131, 3, 4 },
263 { 36000000, 72, 3, 3 },
264 { 45000000, 90, 3, 3 },
265 { 45158000, 90, 3, 3 },
266 { 45158400, 90, 3, 3 },
267 { 48000000, 96, 3, 3 },
268 { 49125000, 131, 4, 3 },
269 { 49152000, 131, 4, 3 },
270 { 60000000, 120, 3, 3 },
271 { 67737600, 226, 5, 3 },
272 { 67738000, 226, 5, 3 },
273 { 73800000, 246, 5, 3 },
274 { 73728000, 246, 5, 3 },
275 { 72000000, 144, 3, 3 },
276 { 84000000, 168, 3, 3 },
277 { 96000000, 96, 3, 2 },
278 { 144000000, 144, 3, 2 },
279 { 192000000, 96, 3, 1 }
280};
281
282static int s5pc100_epll_set_rate(struct clk *clk, unsigned long rate)
283{
284 unsigned int epll_con;
285 unsigned int i;
286
287 if (clk->rate == rate) /* Return if nothing changed */
288 return 0;
289
290 epll_con = __raw_readl(S5P_EPLL_CON);
291
292 epll_con &= ~(PLL65XX_MDIV_MASK | PLL65XX_PDIV_MASK | PLL65XX_SDIV_MASK);
293
294 for (i = 0; i < ARRAY_SIZE(epll_div); i++) {
295 if (epll_div[i][0] == rate) {
296 epll_con |= (epll_div[i][1] << PLL65XX_MDIV_SHIFT) |
297 (epll_div[i][2] << PLL65XX_PDIV_SHIFT) |
298 (epll_div[i][3] << PLL65XX_SDIV_SHIFT);
299 break;
300 }
301 }
302
303 if (i == ARRAY_SIZE(epll_div)) {
304 printk(KERN_ERR "%s: Invalid Clock EPLL Frequency\n", __func__);
305 return -EINVAL;
306 }
307
308 __raw_writel(epll_con, S5P_EPLL_CON);
309
310 printk(KERN_WARNING "EPLL Rate changes from %lu to %lu\n",
311 clk->rate, rate);
312
313 clk->rate = rate;
314
315 return 0;
316}
317
318static struct clk_ops s5pc100_epll_ops = {
319 .get_rate = s5p_epll_get_rate,
320 .set_rate = s5pc100_epll_set_rate,
321};
322
323static int s5pc100_d0_0_ctrl(struct clk *clk, int enable)
324{
325 return s5p_gatectrl(S5P_CLKGATE_D00, clk, enable);
326}
327
328static int s5pc100_d0_1_ctrl(struct clk *clk, int enable)
329{
330 return s5p_gatectrl(S5P_CLKGATE_D01, clk, enable);
331}
332
333static int s5pc100_d0_2_ctrl(struct clk *clk, int enable)
334{
335 return s5p_gatectrl(S5P_CLKGATE_D02, clk, enable);
336}
337
338static int s5pc100_d1_0_ctrl(struct clk *clk, int enable)
339{
340 return s5p_gatectrl(S5P_CLKGATE_D10, clk, enable);
341}
342
343static int s5pc100_d1_1_ctrl(struct clk *clk, int enable)
344{
345 return s5p_gatectrl(S5P_CLKGATE_D11, clk, enable);
346}
347
348static int s5pc100_d1_2_ctrl(struct clk *clk, int enable)
349{
350 return s5p_gatectrl(S5P_CLKGATE_D12, clk, enable);
351}
352
353static int s5pc100_d1_3_ctrl(struct clk *clk, int enable)
354{
355 return s5p_gatectrl(S5P_CLKGATE_D13, clk, enable);
356}
357
358static int s5pc100_d1_4_ctrl(struct clk *clk, int enable)
359{
360 return s5p_gatectrl(S5P_CLKGATE_D14, clk, enable);
361}
362
363static int s5pc100_d1_5_ctrl(struct clk *clk, int enable)
364{
365 return s5p_gatectrl(S5P_CLKGATE_D15, clk, enable);
366}
367
368static int s5pc100_sclk0_ctrl(struct clk *clk, int enable)
369{
370 return s5p_gatectrl(S5P_CLKGATE_SCLK0, clk, enable);
371}
372
373static int s5pc100_sclk1_ctrl(struct clk *clk, int enable)
374{
375 return s5p_gatectrl(S5P_CLKGATE_SCLK1, clk, enable);
376}
377
378/*
379 * The following clocks will be disabled during clock initialization. It is
380 * recommended to keep the following clocks disabled until the driver requests
381 * for enabling the clock.
382 */
383static struct clk init_clocks_off[] = {
384 {
385 .name = "cssys",
386 .parent = &clk_div_d0_bus.clk,
387 .enable = s5pc100_d0_0_ctrl,
388 .ctrlbit = (1 << 6),
389 }, {
390 .name = "secss",
391 .parent = &clk_div_d0_bus.clk,
392 .enable = s5pc100_d0_0_ctrl,
393 .ctrlbit = (1 << 5),
394 }, {
395 .name = "g2d",
396 .parent = &clk_div_d0_bus.clk,
397 .enable = s5pc100_d0_0_ctrl,
398 .ctrlbit = (1 << 4),
399 }, {
400 .name = "mdma",
401 .parent = &clk_div_d0_bus.clk,
402 .enable = s5pc100_d0_0_ctrl,
403 .ctrlbit = (1 << 3),
404 }, {
405 .name = "cfcon",
406 .parent = &clk_div_d0_bus.clk,
407 .enable = s5pc100_d0_0_ctrl,
408 .ctrlbit = (1 << 2),
409 }, {
410 .name = "nfcon",
411 .parent = &clk_div_d0_bus.clk,
412 .enable = s5pc100_d0_1_ctrl,
413 .ctrlbit = (1 << 3),
414 }, {
415 .name = "onenandc",
416 .parent = &clk_div_d0_bus.clk,
417 .enable = s5pc100_d0_1_ctrl,
418 .ctrlbit = (1 << 2),
419 }, {
420 .name = "sdm",
421 .parent = &clk_div_d0_bus.clk,
422 .enable = s5pc100_d0_2_ctrl,
423 .ctrlbit = (1 << 2),
424 }, {
425 .name = "seckey",
426 .parent = &clk_div_d0_bus.clk,
427 .enable = s5pc100_d0_2_ctrl,
428 .ctrlbit = (1 << 1),
429 }, {
430 .name = "modemif",
431 .parent = &clk_div_d1_bus.clk,
432 .enable = s5pc100_d1_0_ctrl,
433 .ctrlbit = (1 << 4),
434 }, {
435 .name = "otg",
436 .parent = &clk_div_d1_bus.clk,
437 .enable = s5pc100_d1_0_ctrl,
438 .ctrlbit = (1 << 3),
439 }, {
440 .name = "usbhost",
441 .parent = &clk_div_d1_bus.clk,
442 .enable = s5pc100_d1_0_ctrl,
443 .ctrlbit = (1 << 2),
444 }, {
445 .name = "dma",
446 .devname = "dma-pl330.1",
447 .parent = &clk_div_d1_bus.clk,
448 .enable = s5pc100_d1_0_ctrl,
449 .ctrlbit = (1 << 1),
450 }, {
451 .name = "dma",
452 .devname = "dma-pl330.0",
453 .parent = &clk_div_d1_bus.clk,
454 .enable = s5pc100_d1_0_ctrl,
455 .ctrlbit = (1 << 0),
456 }, {
457 .name = "lcd",
458 .parent = &clk_div_d1_bus.clk,
459 .enable = s5pc100_d1_1_ctrl,
460 .ctrlbit = (1 << 0),
461 }, {
462 .name = "rotator",
463 .parent = &clk_div_d1_bus.clk,
464 .enable = s5pc100_d1_1_ctrl,
465 .ctrlbit = (1 << 1),
466 }, {
467 .name = "fimc",
468 .devname = "s5p-fimc.0",
469 .parent = &clk_div_d1_bus.clk,
470 .enable = s5pc100_d1_1_ctrl,
471 .ctrlbit = (1 << 2),
472 }, {
473 .name = "fimc",
474 .devname = "s5p-fimc.1",
475 .parent = &clk_div_d1_bus.clk,
476 .enable = s5pc100_d1_1_ctrl,
477 .ctrlbit = (1 << 3),
478 }, {
479 .name = "fimc",
480 .devname = "s5p-fimc.2",
481 .enable = s5pc100_d1_1_ctrl,
482 .ctrlbit = (1 << 4),
483 }, {
484 .name = "jpeg",
485 .parent = &clk_div_d1_bus.clk,
486 .enable = s5pc100_d1_1_ctrl,
487 .ctrlbit = (1 << 5),
488 }, {
489 .name = "mipi-dsim",
490 .parent = &clk_div_d1_bus.clk,
491 .enable = s5pc100_d1_1_ctrl,
492 .ctrlbit = (1 << 6),
493 }, {
494 .name = "mipi-csis",
495 .parent = &clk_div_d1_bus.clk,
496 .enable = s5pc100_d1_1_ctrl,
497 .ctrlbit = (1 << 7),
498 }, {
499 .name = "g3d",
500 .parent = &clk_div_d1_bus.clk,
501 .enable = s5pc100_d1_0_ctrl,
502 .ctrlbit = (1 << 8),
503 }, {
504 .name = "tv",
505 .parent = &clk_div_d1_bus.clk,
506 .enable = s5pc100_d1_2_ctrl,
507 .ctrlbit = (1 << 0),
508 }, {
509 .name = "vp",
510 .parent = &clk_div_d1_bus.clk,
511 .enable = s5pc100_d1_2_ctrl,
512 .ctrlbit = (1 << 1),
513 }, {
514 .name = "mixer",
515 .parent = &clk_div_d1_bus.clk,
516 .enable = s5pc100_d1_2_ctrl,
517 .ctrlbit = (1 << 2),
518 }, {
519 .name = "hdmi",
520 .parent = &clk_div_d1_bus.clk,
521 .enable = s5pc100_d1_2_ctrl,
522 .ctrlbit = (1 << 3),
523 }, {
524 .name = "mfc",
525 .parent = &clk_div_d1_bus.clk,
526 .enable = s5pc100_d1_2_ctrl,
527 .ctrlbit = (1 << 4),
528 }, {
529 .name = "apc",
530 .parent = &clk_div_d1_bus.clk,
531 .enable = s5pc100_d1_3_ctrl,
532 .ctrlbit = (1 << 2),
533 }, {
534 .name = "iec",
535 .parent = &clk_div_d1_bus.clk,
536 .enable = s5pc100_d1_3_ctrl,
537 .ctrlbit = (1 << 3),
538 }, {
539 .name = "systimer",
540 .parent = &clk_div_d1_bus.clk,
541 .enable = s5pc100_d1_3_ctrl,
542 .ctrlbit = (1 << 7),
543 }, {
544 .name = "watchdog",
545 .parent = &clk_div_d1_bus.clk,
546 .enable = s5pc100_d1_3_ctrl,
547 .ctrlbit = (1 << 8),
548 }, {
549 .name = "rtc",
550 .parent = &clk_div_d1_bus.clk,
551 .enable = s5pc100_d1_3_ctrl,
552 .ctrlbit = (1 << 9),
553 }, {
554 .name = "i2c",
555 .devname = "s3c2440-i2c.0",
556 .parent = &clk_div_d1_bus.clk,
557 .enable = s5pc100_d1_4_ctrl,
558 .ctrlbit = (1 << 4),
559 }, {
560 .name = "i2c",
561 .devname = "s3c2440-i2c.1",
562 .parent = &clk_div_d1_bus.clk,
563 .enable = s5pc100_d1_4_ctrl,
564 .ctrlbit = (1 << 5),
565 }, {
566 .name = "spi",
567 .devname = "s5pc100-spi.0",
568 .parent = &clk_div_d1_bus.clk,
569 .enable = s5pc100_d1_4_ctrl,
570 .ctrlbit = (1 << 6),
571 }, {
572 .name = "spi",
573 .devname = "s5pc100-spi.1",
574 .parent = &clk_div_d1_bus.clk,
575 .enable = s5pc100_d1_4_ctrl,
576 .ctrlbit = (1 << 7),
577 }, {
578 .name = "spi",
579 .devname = "s5pc100-spi.2",
580 .parent = &clk_div_d1_bus.clk,
581 .enable = s5pc100_d1_4_ctrl,
582 .ctrlbit = (1 << 8),
583 }, {
584 .name = "irda",
585 .parent = &clk_div_d1_bus.clk,
586 .enable = s5pc100_d1_4_ctrl,
587 .ctrlbit = (1 << 9),
588 }, {
589 .name = "ccan",
590 .parent = &clk_div_d1_bus.clk,
591 .enable = s5pc100_d1_4_ctrl,
592 .ctrlbit = (1 << 10),
593 }, {
594 .name = "ccan",
595 .parent = &clk_div_d1_bus.clk,
596 .enable = s5pc100_d1_4_ctrl,
597 .ctrlbit = (1 << 11),
598 }, {
599 .name = "hsitx",
600 .parent = &clk_div_d1_bus.clk,
601 .enable = s5pc100_d1_4_ctrl,
602 .ctrlbit = (1 << 12),
603 }, {
604 .name = "hsirx",
605 .parent = &clk_div_d1_bus.clk,
606 .enable = s5pc100_d1_4_ctrl,
607 .ctrlbit = (1 << 13),
608 }, {
609 .name = "ac97",
610 .parent = &clk_div_pclkd1.clk,
611 .enable = s5pc100_d1_5_ctrl,
612 .ctrlbit = (1 << 3),
613 }, {
614 .name = "pcm",
615 .devname = "samsung-pcm.0",
616 .parent = &clk_div_pclkd1.clk,
617 .enable = s5pc100_d1_5_ctrl,
618 .ctrlbit = (1 << 4),
619 }, {
620 .name = "pcm",
621 .devname = "samsung-pcm.1",
622 .parent = &clk_div_pclkd1.clk,
623 .enable = s5pc100_d1_5_ctrl,
624 .ctrlbit = (1 << 5),
625 }, {
626 .name = "spdif",
627 .parent = &clk_div_pclkd1.clk,
628 .enable = s5pc100_d1_5_ctrl,
629 .ctrlbit = (1 << 6),
630 }, {
631 .name = "adc",
632 .parent = &clk_div_pclkd1.clk,
633 .enable = s5pc100_d1_5_ctrl,
634 .ctrlbit = (1 << 7),
635 }, {
636 .name = "keypad",
637 .parent = &clk_div_pclkd1.clk,
638 .enable = s5pc100_d1_5_ctrl,
639 .ctrlbit = (1 << 8),
640 }, {
641 .name = "mmc_48m",
642 .devname = "s3c-sdhci.0",
643 .parent = &clk_mout_48m.clk,
644 .enable = s5pc100_sclk0_ctrl,
645 .ctrlbit = (1 << 15),
646 }, {
647 .name = "mmc_48m",
648 .devname = "s3c-sdhci.1",
649 .parent = &clk_mout_48m.clk,
650 .enable = s5pc100_sclk0_ctrl,
651 .ctrlbit = (1 << 16),
652 }, {
653 .name = "mmc_48m",
654 .devname = "s3c-sdhci.2",
655 .parent = &clk_mout_48m.clk,
656 .enable = s5pc100_sclk0_ctrl,
657 .ctrlbit = (1 << 17),
658 },
659};
660
661static struct clk clk_hsmmc2 = {
662 .name = "hsmmc",
663 .devname = "s3c-sdhci.2",
664 .parent = &clk_div_d1_bus.clk,
665 .enable = s5pc100_d1_0_ctrl,
666 .ctrlbit = (1 << 7),
667};
668
669static struct clk clk_hsmmc1 = {
670 .name = "hsmmc",
671 .devname = "s3c-sdhci.1",
672 .parent = &clk_div_d1_bus.clk,
673 .enable = s5pc100_d1_0_ctrl,
674 .ctrlbit = (1 << 6),
675};
676
677static struct clk clk_hsmmc0 = {
678 .name = "hsmmc",
679 .devname = "s3c-sdhci.0",
680 .parent = &clk_div_d1_bus.clk,
681 .enable = s5pc100_d1_0_ctrl,
682 .ctrlbit = (1 << 5),
683};
684
685static struct clk clk_48m_spi0 = {
686 .name = "spi_48m",
687 .devname = "s5pc100-spi.0",
688 .parent = &clk_mout_48m.clk,
689 .enable = s5pc100_sclk0_ctrl,
690 .ctrlbit = (1 << 7),
691};
692
693static struct clk clk_48m_spi1 = {
694 .name = "spi_48m",
695 .devname = "s5pc100-spi.1",
696 .parent = &clk_mout_48m.clk,
697 .enable = s5pc100_sclk0_ctrl,
698 .ctrlbit = (1 << 8),
699};
700
701static struct clk clk_48m_spi2 = {
702 .name = "spi_48m",
703 .devname = "s5pc100-spi.2",
704 .parent = &clk_mout_48m.clk,
705 .enable = s5pc100_sclk0_ctrl,
706 .ctrlbit = (1 << 9),
707};
708
709static struct clk clk_i2s0 = {
710 .name = "iis",
711 .devname = "samsung-i2s.0",
712 .parent = &clk_div_pclkd1.clk,
713 .enable = s5pc100_d1_5_ctrl,
714 .ctrlbit = (1 << 0),
715};
716
717static struct clk clk_i2s1 = {
718 .name = "iis",
719 .devname = "samsung-i2s.1",
720 .parent = &clk_div_pclkd1.clk,
721 .enable = s5pc100_d1_5_ctrl,
722 .ctrlbit = (1 << 1),
723};
724
725static struct clk clk_i2s2 = {
726 .name = "iis",
727 .devname = "samsung-i2s.2",
728 .parent = &clk_div_pclkd1.clk,
729 .enable = s5pc100_d1_5_ctrl,
730 .ctrlbit = (1 << 2),
731};
732
733static struct clk clk_vclk54m = {
734 .name = "vclk_54m",
735 .rate = 54000000,
736};
737
738static struct clk clk_i2scdclk0 = {
739 .name = "i2s_cdclk0",
740};
741
742static struct clk clk_i2scdclk1 = {
743 .name = "i2s_cdclk1",
744};
745
746static struct clk clk_i2scdclk2 = {
747 .name = "i2s_cdclk2",
748};
749
750static struct clk clk_pcmcdclk0 = {
751 .name = "pcm_cdclk0",
752};
753
754static struct clk clk_pcmcdclk1 = {
755 .name = "pcm_cdclk1",
756};
757
758static struct clk *clk_src_group1_list[] = {
759 [0] = &clk_mout_epll.clk,
760 [1] = &clk_div_mpll2.clk,
761 [2] = &clk_fin_epll,
762 [3] = &clk_mout_hpll.clk,
763};
764
765static struct clksrc_sources clk_src_group1 = {
766 .sources = clk_src_group1_list,
767 .nr_sources = ARRAY_SIZE(clk_src_group1_list),
768};
769
770static struct clk *clk_src_group2_list[] = {
771 [0] = &clk_mout_epll.clk,
772 [1] = &clk_div_mpll.clk,
773};
774
775static struct clksrc_sources clk_src_group2 = {
776 .sources = clk_src_group2_list,
777 .nr_sources = ARRAY_SIZE(clk_src_group2_list),
778};
779
780static struct clk *clk_src_group3_list[] = {
781 [0] = &clk_mout_epll.clk,
782 [1] = &clk_div_mpll.clk,
783 [2] = &clk_fin_epll,
784 [3] = &clk_i2scdclk0,
785 [4] = &clk_pcmcdclk0,
786 [5] = &clk_mout_hpll.clk,
787};
788
789static struct clksrc_sources clk_src_group3 = {
790 .sources = clk_src_group3_list,
791 .nr_sources = ARRAY_SIZE(clk_src_group3_list),
792};
793
794static struct clksrc_clk clk_sclk_audio0 = {
795 .clk = {
796 .name = "sclk_audio",
797 .devname = "samsung-pcm.0",
798 .ctrlbit = (1 << 8),
799 .enable = s5pc100_sclk1_ctrl,
800 },
801 .sources = &clk_src_group3,
802 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 3 },
803 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
804};
805
806static struct clk *clk_src_group4_list[] = {
807 [0] = &clk_mout_epll.clk,
808 [1] = &clk_div_mpll.clk,
809 [2] = &clk_fin_epll,
810 [3] = &clk_i2scdclk1,
811 [4] = &clk_pcmcdclk1,
812 [5] = &clk_mout_hpll.clk,
813};
814
815static struct clksrc_sources clk_src_group4 = {
816 .sources = clk_src_group4_list,
817 .nr_sources = ARRAY_SIZE(clk_src_group4_list),
818};
819
820static struct clksrc_clk clk_sclk_audio1 = {
821 .clk = {
822 .name = "sclk_audio",
823 .devname = "samsung-pcm.1",
824 .ctrlbit = (1 << 9),
825 .enable = s5pc100_sclk1_ctrl,
826 },
827 .sources = &clk_src_group4,
828 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 3 },
829 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
830};
831
832static struct clk *clk_src_group5_list[] = {
833 [0] = &clk_mout_epll.clk,
834 [1] = &clk_div_mpll.clk,
835 [2] = &clk_fin_epll,
836 [3] = &clk_i2scdclk2,
837 [4] = &clk_mout_hpll.clk,
838};
839
840static struct clksrc_sources clk_src_group5 = {
841 .sources = clk_src_group5_list,
842 .nr_sources = ARRAY_SIZE(clk_src_group5_list),
843};
844
845static struct clksrc_clk clk_sclk_audio2 = {
846 .clk = {
847 .name = "sclk_audio",
848 .devname = "samsung-pcm.2",
849 .ctrlbit = (1 << 10),
850 .enable = s5pc100_sclk1_ctrl,
851 },
852 .sources = &clk_src_group5,
853 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 3 },
854 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
855};
856
857static struct clk *clk_src_group6_list[] = {
858 [0] = &s5p_clk_27m,
859 [1] = &clk_vclk54m,
860 [2] = &clk_div_hdmi.clk,
861};
862
863static struct clksrc_sources clk_src_group6 = {
864 .sources = clk_src_group6_list,
865 .nr_sources = ARRAY_SIZE(clk_src_group6_list),
866};
867
868static struct clk *clk_src_group7_list[] = {
869 [0] = &clk_mout_epll.clk,
870 [1] = &clk_div_mpll.clk,
871 [2] = &clk_mout_hpll.clk,
872 [3] = &clk_vclk54m,
873};
874
875static struct clksrc_sources clk_src_group7 = {
876 .sources = clk_src_group7_list,
877 .nr_sources = ARRAY_SIZE(clk_src_group7_list),
878};
879
880static struct clk *clk_src_mmc0_list[] = {
881 [0] = &clk_mout_epll.clk,
882 [1] = &clk_div_mpll.clk,
883 [2] = &clk_fin_epll,
884};
885
886static struct clksrc_sources clk_src_mmc0 = {
887 .sources = clk_src_mmc0_list,
888 .nr_sources = ARRAY_SIZE(clk_src_mmc0_list),
889};
890
891static struct clk *clk_src_mmc12_list[] = {
892 [0] = &clk_mout_epll.clk,
893 [1] = &clk_div_mpll.clk,
894 [2] = &clk_fin_epll,
895 [3] = &clk_mout_hpll.clk,
896};
897
898static struct clksrc_sources clk_src_mmc12 = {
899 .sources = clk_src_mmc12_list,
900 .nr_sources = ARRAY_SIZE(clk_src_mmc12_list),
901};
902
903static struct clk *clk_src_irda_usb_list[] = {
904 [0] = &clk_mout_epll.clk,
905 [1] = &clk_div_mpll.clk,
906 [2] = &clk_fin_epll,
907 [3] = &clk_mout_hpll.clk,
908};
909
910static struct clksrc_sources clk_src_irda_usb = {
911 .sources = clk_src_irda_usb_list,
912 .nr_sources = ARRAY_SIZE(clk_src_irda_usb_list),
913};
914
915static struct clk *clk_src_pwi_list[] = {
916 [0] = &clk_fin_epll,
917 [1] = &clk_mout_epll.clk,
918 [2] = &clk_div_mpll.clk,
919};
920
921static struct clksrc_sources clk_src_pwi = {
922 .sources = clk_src_pwi_list,
923 .nr_sources = ARRAY_SIZE(clk_src_pwi_list),
924};
925
926static struct clk *clk_sclk_spdif_list[] = {
927 [0] = &clk_sclk_audio0.clk,
928 [1] = &clk_sclk_audio1.clk,
929 [2] = &clk_sclk_audio2.clk,
930};
931
932static struct clksrc_sources clk_src_sclk_spdif = {
933 .sources = clk_sclk_spdif_list,
934 .nr_sources = ARRAY_SIZE(clk_sclk_spdif_list),
935};
936
937static struct clksrc_clk clk_sclk_spdif = {
938 .clk = {
939 .name = "sclk_spdif",
940 .ctrlbit = (1 << 11),
941 .enable = s5pc100_sclk1_ctrl,
942 .ops = &s5p_sclk_spdif_ops,
943 },
944 .sources = &clk_src_sclk_spdif,
945 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 24, .size = 2 },
946};
947
948static struct clksrc_clk clksrcs[] = {
949 {
950 .clk = {
951 .name = "sclk_mixer",
952 .ctrlbit = (1 << 6),
953 .enable = s5pc100_sclk0_ctrl,
954
955 },
956 .sources = &clk_src_group6,
957 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 28, .size = 2 },
958 }, {
959 .clk = {
960 .name = "sclk_lcd",
961 .ctrlbit = (1 << 0),
962 .enable = s5pc100_sclk1_ctrl,
963
964 },
965 .sources = &clk_src_group7,
966 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 12, .size = 2 },
967 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
968 }, {
969 .clk = {
970 .name = "sclk_fimc",
971 .devname = "s5p-fimc.0",
972 .ctrlbit = (1 << 1),
973 .enable = s5pc100_sclk1_ctrl,
974
975 },
976 .sources = &clk_src_group7,
977 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 16, .size = 2 },
978 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
979 }, {
980 .clk = {
981 .name = "sclk_fimc",
982 .devname = "s5p-fimc.1",
983 .ctrlbit = (1 << 2),
984 .enable = s5pc100_sclk1_ctrl,
985
986 },
987 .sources = &clk_src_group7,
988 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 20, .size = 2 },
989 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
990 }, {
991 .clk = {
992 .name = "sclk_fimc",
993 .devname = "s5p-fimc.2",
994 .ctrlbit = (1 << 3),
995 .enable = s5pc100_sclk1_ctrl,
996
997 },
998 .sources = &clk_src_group7,
999 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 24, .size = 2 },
1000 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 24, .size = 4 },
1001 }, {
1002 .clk = {
1003 .name = "sclk_irda",
1004 .ctrlbit = (1 << 10),
1005 .enable = s5pc100_sclk0_ctrl,
1006
1007 },
1008 .sources = &clk_src_irda_usb,
1009 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1010 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1011 }, {
1012 .clk = {
1013 .name = "sclk_irda",
1014 .ctrlbit = (1 << 10),
1015 .enable = s5pc100_sclk0_ctrl,
1016
1017 },
1018 .sources = &clk_src_mmc12,
1019 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 2 },
1020 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 16, .size = 4 },
1021 }, {
1022 .clk = {
1023 .name = "sclk_pwi",
1024 .ctrlbit = (1 << 1),
1025 .enable = s5pc100_sclk0_ctrl,
1026
1027 },
1028 .sources = &clk_src_pwi,
1029 .reg_src = { .reg = S5P_CLK_SRC3, .shift = 0, .size = 2 },
1030 .reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 3 },
1031 }, {
1032 .clk = {
1033 .name = "sclk_uhost",
1034 .ctrlbit = (1 << 11),
1035 .enable = s5pc100_sclk0_ctrl,
1036
1037 },
1038 .sources = &clk_src_irda_usb,
1039 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 2 },
1040 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 20, .size = 4 },
1041 },
1042};
1043
1044static struct clksrc_clk clk_sclk_uart = {
1045 .clk = {
1046 .name = "uclk1",
1047 .ctrlbit = (1 << 3),
1048 .enable = s5pc100_sclk0_ctrl,
1049 },
1050 .sources = &clk_src_group2,
1051 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 0, .size = 1 },
1052 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
1053};
1054
1055static struct clksrc_clk clk_sclk_mmc0 = {
1056 .clk = {
1057 .name = "sclk_mmc",
1058 .devname = "s3c-sdhci.0",
1059 .ctrlbit = (1 << 12),
1060 .enable = s5pc100_sclk1_ctrl,
1061 },
1062 .sources = &clk_src_mmc0,
1063 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
1064 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 0, .size = 4 },
1065};
1066
1067static struct clksrc_clk clk_sclk_mmc1 = {
1068 .clk = {
1069 .name = "sclk_mmc",
1070 .devname = "s3c-sdhci.1",
1071 .ctrlbit = (1 << 13),
1072 .enable = s5pc100_sclk1_ctrl,
1073 },
1074 .sources = &clk_src_mmc12,
1075 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
1076 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 4, .size = 4 },
1077};
1078
1079static struct clksrc_clk clk_sclk_mmc2 = {
1080 .clk = {
1081 .name = "sclk_mmc",
1082 .devname = "s3c-sdhci.2",
1083 .ctrlbit = (1 << 14),
1084 .enable = s5pc100_sclk1_ctrl,
1085 },
1086 .sources = &clk_src_mmc12,
1087 .reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
1088 .reg_div = { .reg = S5P_CLK_DIV3, .shift = 8, .size = 4 },
1089};
1090
1091static struct clksrc_clk clk_sclk_spi0 = {
1092 .clk = {
1093 .name = "sclk_spi",
1094 .devname = "s5pc100-spi.0",
1095 .ctrlbit = (1 << 4),
1096 .enable = s5pc100_sclk0_ctrl,
1097 },
1098 .sources = &clk_src_group1,
1099 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 4, .size = 2 },
1100 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
1101};
1102
1103static struct clksrc_clk clk_sclk_spi1 = {
1104 .clk = {
1105 .name = "sclk_spi",
1106 .devname = "s5pc100-spi.1",
1107 .ctrlbit = (1 << 5),
1108 .enable = s5pc100_sclk0_ctrl,
1109 },
1110 .sources = &clk_src_group1,
1111 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 8, .size = 2 },
1112 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
1113};
1114
1115static struct clksrc_clk clk_sclk_spi2 = {
1116 .clk = {
1117 .name = "sclk_spi",
1118 .devname = "s5pc100-spi.2",
1119 .ctrlbit = (1 << 6),
1120 .enable = s5pc100_sclk0_ctrl,
1121 },
1122 .sources = &clk_src_group1,
1123 .reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 2 },
1124 .reg_div = { .reg = S5P_CLK_DIV2, .shift = 12, .size = 4 },
1125};
1126
1127/* Clock initialisation code */
1128static struct clksrc_clk *sysclks[] = {
1129 &clk_mout_apll,
1130 &clk_mout_epll,
1131 &clk_mout_mpll,
1132 &clk_mout_hpll,
1133 &clk_mout_href,
1134 &clk_mout_48m,
1135 &clk_div_apll,
1136 &clk_div_arm,
1137 &clk_div_d0_bus,
1138 &clk_div_pclkd0,
1139 &clk_div_secss,
1140 &clk_div_apll2,
1141 &clk_mout_am,
1142 &clk_div_d1_bus,
1143 &clk_div_mpll2,
1144 &clk_div_mpll,
1145 &clk_mout_onenand,
1146 &clk_div_onenand,
1147 &clk_div_pclkd1,
1148 &clk_div_cam,
1149 &clk_div_hdmi,
1150 &clk_sclk_audio0,
1151 &clk_sclk_audio1,
1152 &clk_sclk_audio2,
1153 &clk_sclk_spdif,
1154};
1155
1156static struct clk *clk_cdev[] = {
1157 &clk_hsmmc0,
1158 &clk_hsmmc1,
1159 &clk_hsmmc2,
1160 &clk_48m_spi0,
1161 &clk_48m_spi1,
1162 &clk_48m_spi2,
1163 &clk_i2s0,
1164 &clk_i2s1,
1165 &clk_i2s2,
1166};
1167
1168static struct clksrc_clk *clksrc_cdev[] = {
1169 &clk_sclk_uart,
1170 &clk_sclk_mmc0,
1171 &clk_sclk_mmc1,
1172 &clk_sclk_mmc2,
1173 &clk_sclk_spi0,
1174 &clk_sclk_spi1,
1175 &clk_sclk_spi2,
1176};
1177
1178void __init_or_cpufreq s5pc100_setup_clocks(void)
1179{
1180 unsigned long xtal;
1181 unsigned long arm;
1182 unsigned long hclkd0;
1183 unsigned long hclkd1;
1184 unsigned long pclkd0;
1185 unsigned long pclkd1;
1186 unsigned long apll;
1187 unsigned long mpll;
1188 unsigned long epll;
1189 unsigned long hpll;
1190 unsigned int ptr;
1191
1192 /* Set S5PC100 functions for clk_fout_epll */
1193 clk_fout_epll.enable = s5p_epll_enable;
1194 clk_fout_epll.ops = &s5pc100_epll_ops;
1195
1196 printk(KERN_DEBUG "%s: registering clocks\n", __func__);
1197
1198 xtal = clk_get_rate(&clk_xtal);
1199
1200 printk(KERN_DEBUG "%s: xtal is %ld\n", __func__, xtal);
1201
1202 apll = s5p_get_pll65xx(xtal, __raw_readl(S5P_APLL_CON));
1203 mpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_MPLL_CON));
1204 epll = s5p_get_pll65xx(xtal, __raw_readl(S5P_EPLL_CON));
1205 hpll = s5p_get_pll65xx(xtal, __raw_readl(S5P_HPLL_CON));
1206
1207 printk(KERN_INFO "S5PC100: PLL settings, A=%ld.%ldMHz, M=%ld.%ldMHz, E=%ld.%ldMHz, H=%ld.%ldMHz\n",
1208 print_mhz(apll), print_mhz(mpll), print_mhz(epll), print_mhz(hpll));
1209
1210 clk_fout_apll.rate = apll;
1211 clk_fout_mpll.rate = mpll;
1212 clk_fout_epll.rate = epll;
1213 clk_mout_hpll.clk.rate = hpll;
1214
1215 for (ptr = 0; ptr < ARRAY_SIZE(clksrcs); ptr++)
1216 s3c_set_clksrc(&clksrcs[ptr], true);
1217
1218 arm = clk_get_rate(&clk_div_arm.clk);
1219 hclkd0 = clk_get_rate(&clk_div_d0_bus.clk);
1220 pclkd0 = clk_get_rate(&clk_div_pclkd0.clk);
1221 hclkd1 = clk_get_rate(&clk_div_d1_bus.clk);
1222 pclkd1 = clk_get_rate(&clk_div_pclkd1.clk);
1223
1224 printk(KERN_INFO "S5PC100: HCLKD0=%ld.%ldMHz, HCLKD1=%ld.%ldMHz, PCLKD0=%ld.%ldMHz, PCLKD1=%ld.%ldMHz\n",
1225 print_mhz(hclkd0), print_mhz(hclkd1), print_mhz(pclkd0), print_mhz(pclkd1));
1226
1227 clk_f.rate = arm;
1228 clk_h.rate = hclkd1;
1229 clk_p.rate = pclkd1;
1230}
1231
1232/*
1233 * The following clocks will be enabled during clock initialization.
1234 */
1235static struct clk init_clocks[] = {
1236 {
1237 .name = "tzic",
1238 .parent = &clk_div_d0_bus.clk,
1239 .enable = s5pc100_d0_0_ctrl,
1240 .ctrlbit = (1 << 1),
1241 }, {
1242 .name = "intc",
1243 .parent = &clk_div_d0_bus.clk,
1244 .enable = s5pc100_d0_0_ctrl,
1245 .ctrlbit = (1 << 0),
1246 }, {
1247 .name = "ebi",
1248 .parent = &clk_div_d0_bus.clk,
1249 .enable = s5pc100_d0_1_ctrl,
1250 .ctrlbit = (1 << 5),
1251 }, {
1252 .name = "intmem",
1253 .parent = &clk_div_d0_bus.clk,
1254 .enable = s5pc100_d0_1_ctrl,
1255 .ctrlbit = (1 << 4),
1256 }, {
1257 .name = "sromc",
1258 .parent = &clk_div_d0_bus.clk,
1259 .enable = s5pc100_d0_1_ctrl,
1260 .ctrlbit = (1 << 1),
1261 }, {
1262 .name = "dmc",
1263 .parent = &clk_div_d0_bus.clk,
1264 .enable = s5pc100_d0_1_ctrl,
1265 .ctrlbit = (1 << 0),
1266 }, {
1267 .name = "chipid",
1268 .parent = &clk_div_d0_bus.clk,
1269 .enable = s5pc100_d0_1_ctrl,
1270 .ctrlbit = (1 << 0),
1271 }, {
1272 .name = "gpio",
1273 .parent = &clk_div_d1_bus.clk,
1274 .enable = s5pc100_d1_3_ctrl,
1275 .ctrlbit = (1 << 1),
1276 }, {
1277 .name = "uart",
1278 .devname = "s3c6400-uart.0",
1279 .parent = &clk_div_d1_bus.clk,
1280 .enable = s5pc100_d1_4_ctrl,
1281 .ctrlbit = (1 << 0),
1282 }, {
1283 .name = "uart",
1284 .devname = "s3c6400-uart.1",
1285 .parent = &clk_div_d1_bus.clk,
1286 .enable = s5pc100_d1_4_ctrl,
1287 .ctrlbit = (1 << 1),
1288 }, {
1289 .name = "uart",
1290 .devname = "s3c6400-uart.2",
1291 .parent = &clk_div_d1_bus.clk,
1292 .enable = s5pc100_d1_4_ctrl,
1293 .ctrlbit = (1 << 2),
1294 }, {
1295 .name = "uart",
1296 .devname = "s3c6400-uart.3",
1297 .parent = &clk_div_d1_bus.clk,
1298 .enable = s5pc100_d1_4_ctrl,
1299 .ctrlbit = (1 << 3),
1300 }, {
1301 .name = "timers",
1302 .parent = &clk_div_d1_bus.clk,
1303 .enable = s5pc100_d1_3_ctrl,
1304 .ctrlbit = (1 << 6),
1305 },
1306};
1307
1308static struct clk *clks[] __initdata = {
1309 &clk_ext,
1310 &clk_i2scdclk0,
1311 &clk_i2scdclk1,
1312 &clk_i2scdclk2,
1313 &clk_pcmcdclk0,
1314 &clk_pcmcdclk1,
1315};
1316
1317static struct clk_lookup s5pc100_clk_lookup[] = {
1318 CLKDEV_INIT(NULL, "clk_uart_baud2", &clk_p),
1319 CLKDEV_INIT(NULL, "clk_uart_baud3", &clk_sclk_uart.clk),
1320 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.0", &clk_hsmmc0),
1321 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.0", &clk_hsmmc1),
1322 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.0", &clk_hsmmc2),
1323 CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &clk_sclk_mmc0.clk),
1324 CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &clk_sclk_mmc1.clk),
1325 CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &clk_sclk_mmc2.clk),
1326 CLKDEV_INIT(NULL, "spi_busclk0", &clk_p),
1327 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk1", &clk_48m_spi0),
1328 CLKDEV_INIT("s5pc100-spi.0", "spi_busclk2", &clk_sclk_spi0.clk),
1329 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk1", &clk_48m_spi1),
1330 CLKDEV_INIT("s5pc100-spi.1", "spi_busclk2", &clk_sclk_spi1.clk),
1331 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk1", &clk_48m_spi2),
1332 CLKDEV_INIT("s5pc100-spi.2", "spi_busclk2", &clk_sclk_spi2.clk),
1333 CLKDEV_INIT("samsung-i2s.0", "i2s_opclk0", &clk_i2s0),
1334 CLKDEV_INIT("samsung-i2s.1", "i2s_opclk0", &clk_i2s1),
1335 CLKDEV_INIT("samsung-i2s.2", "i2s_opclk0", &clk_i2s2),
1336};
1337
1338void __init s5pc100_register_clocks(void)
1339{
1340 int ptr;
1341
1342 s3c24xx_register_clocks(clks, ARRAY_SIZE(clks));
1343
1344 for (ptr = 0; ptr < ARRAY_SIZE(sysclks); ptr++)
1345 s3c_register_clksrc(sysclks[ptr], 1);
1346
1347 s3c_register_clksrc(clksrcs, ARRAY_SIZE(clksrcs));
1348 s3c_register_clocks(init_clocks, ARRAY_SIZE(init_clocks));
1349 for (ptr = 0; ptr < ARRAY_SIZE(clksrc_cdev); ptr++)
1350 s3c_register_clksrc(clksrc_cdev[ptr], 1);
1351
1352 s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1353 s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
1354 clkdev_add_table(s5pc100_clk_lookup, ARRAY_SIZE(s5pc100_clk_lookup));
1355
1356 s3c24xx_register_clocks(clk_cdev, ARRAY_SIZE(clk_cdev));
1357 for (ptr = 0; ptr < ARRAY_SIZE(clk_cdev); ptr++)
1358 s3c_disable_clocks(clk_cdev[ptr], 1);
1359
1360 s3c24xx_register_clock(&dummy_apb_pclk);
1361}
diff --git a/arch/arm/mach-s5pc100/common.c b/arch/arm/mach-s5pc100/common.c
deleted file mode 100644
index 6a41bf7dacf6..000000000000
--- a/arch/arm/mach-s5pc100/common.c
+++ /dev/null
@@ -1,255 +0,0 @@
1/*
2 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Copyright 2009 Samsung Electronics Co.
6 * Byungho Min <bhmin@samsung.com>
7 *
8 * Common Codes for S5PC100
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17#include <linux/interrupt.h>
18#include <linux/list.h>
19#include <linux/timer.h>
20#include <linux/init.h>
21#include <linux/clk.h>
22#include <linux/io.h>
23#include <linux/device.h>
24#include <linux/serial_core.h>
25#include <linux/serial_s3c.h>
26#include <clocksource/samsung_pwm.h>
27#include <linux/platform_device.h>
28#include <linux/sched.h>
29#include <linux/reboot.h>
30
31#include <asm/irq.h>
32#include <asm/proc-fns.h>
33#include <asm/system_misc.h>
34#include <asm/mach/arch.h>
35#include <asm/mach/map.h>
36#include <asm/mach/irq.h>
37
38#include <mach/map.h>
39#include <mach/hardware.h>
40#include <mach/regs-clock.h>
41
42#include <plat/cpu.h>
43#include <plat/devs.h>
44#include <plat/clock.h>
45#include <plat/sdhci.h>
46#include <plat/adc-core.h>
47#include <plat/ata-core.h>
48#include <plat/fb-core.h>
49#include <plat/iic-core.h>
50#include <plat/onenand-core.h>
51#include <plat/pwm-core.h>
52#include <plat/spi-core.h>
53#include <plat/watchdog-reset.h>
54
55#include "common.h"
56
57static const char name_s5pc100[] = "S5PC100";
58
59static struct cpu_table cpu_ids[] __initdata = {
60 {
61 .idcode = S5PC100_CPU_ID,
62 .idmask = S5PC100_CPU_MASK,
63 .map_io = s5pc100_map_io,
64 .init_clocks = s5pc100_init_clocks,
65 .init_uarts = s5pc100_init_uarts,
66 .init = s5pc100_init,
67 .name = name_s5pc100,
68 },
69};
70
71/* Initial IO mappings */
72
73static struct map_desc s5pc100_iodesc[] __initdata = {
74 {
75 .virtual = (unsigned long)S5P_VA_CHIPID,
76 .pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
77 .length = SZ_4K,
78 .type = MT_DEVICE,
79 }, {
80 .virtual = (unsigned long)S3C_VA_SYS,
81 .pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
82 .length = SZ_64K,
83 .type = MT_DEVICE,
84 }, {
85 .virtual = (unsigned long)S3C_VA_TIMER,
86 .pfn = __phys_to_pfn(S5PC100_PA_TIMER),
87 .length = SZ_16K,
88 .type = MT_DEVICE,
89 }, {
90 .virtual = (unsigned long)S3C_VA_WATCHDOG,
91 .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
92 .length = SZ_4K,
93 .type = MT_DEVICE,
94 }, {
95 .virtual = (unsigned long)S5P_VA_SROMC,
96 .pfn = __phys_to_pfn(S5PC100_PA_SROMC),
97 .length = SZ_4K,
98 .type = MT_DEVICE,
99 }, {
100 .virtual = (unsigned long)S5P_VA_SYSTIMER,
101 .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
102 .length = SZ_16K,
103 .type = MT_DEVICE,
104 }, {
105 .virtual = (unsigned long)S5P_VA_GPIO,
106 .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
107 .length = SZ_4K,
108 .type = MT_DEVICE,
109 }, {
110 .virtual = (unsigned long)VA_VIC0,
111 .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
112 .length = SZ_16K,
113 .type = MT_DEVICE,
114 }, {
115 .virtual = (unsigned long)VA_VIC1,
116 .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
117 .length = SZ_16K,
118 .type = MT_DEVICE,
119 }, {
120 .virtual = (unsigned long)VA_VIC2,
121 .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
122 .length = SZ_16K,
123 .type = MT_DEVICE,
124 }, {
125 .virtual = (unsigned long)S3C_VA_UART,
126 .pfn = __phys_to_pfn(S3C_PA_UART),
127 .length = SZ_512K,
128 .type = MT_DEVICE,
129 }, {
130 .virtual = (unsigned long)S5PC100_VA_OTHERS,
131 .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
132 .length = SZ_4K,
133 .type = MT_DEVICE,
134 }
135};
136
137static struct samsung_pwm_variant s5pc100_pwm_variant = {
138 .bits = 32,
139 .div_base = 0,
140 .has_tint_cstat = true,
141 .tclk_mask = (1 << 5),
142};
143
144void __init samsung_set_timer_source(unsigned int event, unsigned int source)
145{
146 s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1;
147 s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source));
148}
149
150void __init samsung_timer_init(void)
151{
152 unsigned int timer_irqs[SAMSUNG_PWM_NUM] = {
153 IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
154 IRQ_TIMER3_VIC, IRQ_TIMER4_VIC,
155 };
156
157 samsung_pwm_clocksource_init(S3C_VA_TIMER,
158 timer_irqs, &s5pc100_pwm_variant);
159}
160
161/*
162 * s5pc100_map_io
163 *
164 * register the standard CPU IO areas
165 */
166
167void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
168{
169 /* initialize the io descriptors we need for initialization */
170 iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
171 if (mach_desc)
172 iotable_init(mach_desc, size);
173
174 /* detect cpu id and rev. */
175 s5p_init_cpu(S5P_VA_CHIPID);
176
177 s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
178
179 samsung_pwm_set_platdata(&s5pc100_pwm_variant);
180}
181
182void __init s5pc100_map_io(void)
183{
184 /* initialise device information early */
185 s5pc100_default_sdhci0();
186 s5pc100_default_sdhci1();
187 s5pc100_default_sdhci2();
188
189 s3c_adc_setname("s3c64xx-adc");
190
191 /* the i2c devices are directly compatible with s3c2440 */
192 s3c_i2c0_setname("s3c2440-i2c");
193 s3c_i2c1_setname("s3c2440-i2c");
194
195 s3c_onenand_setname("s5pc100-onenand");
196 s3c_fb_setname("s5pc100-fb");
197 s3c_cfcon_setname("s5pc100-pata");
198
199 s3c64xx_spi_setname("s5pc100-spi");
200}
201
202void __init s5pc100_init_clocks(int xtal)
203{
204 printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
205
206 s3c24xx_register_baseclocks(xtal);
207 s5p_register_clocks(xtal);
208 s5pc100_register_clocks();
209 s5pc100_setup_clocks();
210 samsung_wdt_reset_init(S3C_VA_WATCHDOG);
211}
212
213void __init s5pc100_init_irq(void)
214{
215 u32 vic[] = {~0, ~0, ~0};
216
217 /* VIC0, VIC1, and VIC2 are fully populated. */
218 s5p_init_irq(vic, ARRAY_SIZE(vic));
219}
220
221static struct bus_type s5pc100_subsys = {
222 .name = "s5pc100-core",
223 .dev_name = "s5pc100-core",
224};
225
226static struct device s5pc100_dev = {
227 .bus = &s5pc100_subsys,
228};
229
230static int __init s5pc100_core_init(void)
231{
232 return subsys_system_register(&s5pc100_subsys, NULL);
233}
234core_initcall(s5pc100_core_init);
235
236int __init s5pc100_init(void)
237{
238 printk(KERN_INFO "S5PC100: Initializing architecture\n");
239 return device_register(&s5pc100_dev);
240}
241
242/* uart registration process */
243
244void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
245{
246 s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
247}
248
249void s5pc100_restart(enum reboot_mode mode, const char *cmd)
250{
251 if (mode != REBOOT_SOFT)
252 samsung_wdt_reset();
253
254 soft_restart(0);
255}
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
deleted file mode 100644
index 08d782d65d7b..000000000000
--- a/arch/arm/mach-s5pc100/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
1/*
2 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Common Header for S5PC100 machines
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H
13#define __ARCH_ARM_MACH_S5PC100_COMMON_H
14
15#include <linux/reboot.h>
16
17void s5pc100_init_io(struct map_desc *mach_desc, int size);
18void s5pc100_init_irq(void);
19
20void s5pc100_register_clocks(void);
21void s5pc100_setup_clocks(void);
22
23void s5pc100_restart(enum reboot_mode mode, const char *cmd);
24
25extern int s5pc100_init(void);
26extern void s5pc100_map_io(void);
27extern void s5pc100_init_clocks(int xtal);
28extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
29
30#endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pc100/dev-audio.c b/arch/arm/mach-s5pc100/dev-audio.c
deleted file mode 100644
index 46f488b09391..000000000000
--- a/arch/arm/mach-s5pc100/dev-audio.c
+++ /dev/null
@@ -1,239 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dev-audio.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co. Ltd
4 * Jaswinder Singh <jassi.brar@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/platform_device.h>
12#include <linux/dma-mapping.h>
13#include <linux/gpio.h>
14
15#include <plat/gpio-cfg.h>
16#include <linux/platform_data/asoc-s3c.h>
17
18#include <mach/map.h>
19#include <mach/dma.h>
20#include <mach/irqs.h>
21
22static int s5pc100_cfg_i2s(struct platform_device *pdev)
23{
24 /* configure GPIO for i2s port */
25 switch (pdev->id) {
26 case 0: /* Dedicated pins */
27 break;
28 case 1:
29 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2));
30 break;
31 case 2:
32 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4));
33 break;
34 default:
35 printk(KERN_ERR "Invalid Device %d\n", pdev->id);
36 return -EINVAL;
37 }
38
39 return 0;
40}
41
42static struct s3c_audio_pdata i2sv5_pdata = {
43 .cfg_gpio = s5pc100_cfg_i2s,
44 .type = {
45 .i2s = {
46 .quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI
47 | QUIRK_NEED_RSTCLR,
48 },
49 },
50};
51
52static struct resource s5pc100_iis0_resource[] = {
53 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256),
54 [1] = DEFINE_RES_DMA(DMACH_I2S0_TX),
55 [2] = DEFINE_RES_DMA(DMACH_I2S0_RX),
56 [3] = DEFINE_RES_DMA(DMACH_I2S0S_TX),
57};
58
59struct platform_device s5pc100_device_iis0 = {
60 .name = "samsung-i2s",
61 .id = 0,
62 .num_resources = ARRAY_SIZE(s5pc100_iis0_resource),
63 .resource = s5pc100_iis0_resource,
64 .dev = {
65 .platform_data = &i2sv5_pdata,
66 },
67};
68
69static struct s3c_audio_pdata i2sv3_pdata = {
70 .cfg_gpio = s5pc100_cfg_i2s,
71};
72
73static struct resource s5pc100_iis1_resource[] = {
74 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256),
75 [1] = DEFINE_RES_DMA(DMACH_I2S1_TX),
76 [2] = DEFINE_RES_DMA(DMACH_I2S1_RX),
77};
78
79struct platform_device s5pc100_device_iis1 = {
80 .name = "samsung-i2s",
81 .id = 1,
82 .num_resources = ARRAY_SIZE(s5pc100_iis1_resource),
83 .resource = s5pc100_iis1_resource,
84 .dev = {
85 .platform_data = &i2sv3_pdata,
86 },
87};
88
89static struct resource s5pc100_iis2_resource[] = {
90 [0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256),
91 [1] = DEFINE_RES_DMA(DMACH_I2S2_TX),
92 [2] = DEFINE_RES_DMA(DMACH_I2S2_RX),
93};
94
95struct platform_device s5pc100_device_iis2 = {
96 .name = "samsung-i2s",
97 .id = 2,
98 .num_resources = ARRAY_SIZE(s5pc100_iis2_resource),
99 .resource = s5pc100_iis2_resource,
100 .dev = {
101 .platform_data = &i2sv3_pdata,
102 },
103};
104
105/* PCM Controller platform_devices */
106
107static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev)
108{
109 switch (pdev->id) {
110 case 0:
111 s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5));
112 break;
113
114 case 1:
115 s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3));
116 break;
117
118 default:
119 printk(KERN_DEBUG "Invalid PCM Controller number!");
120 return -EINVAL;
121 }
122
123 return 0;
124}
125
126static struct s3c_audio_pdata s3c_pcm_pdata = {
127 .cfg_gpio = s5pc100_pcm_cfg_gpio,
128};
129
130static struct resource s5pc100_pcm0_resource[] = {
131 [0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256),
132 [1] = DEFINE_RES_DMA(DMACH_PCM0_TX),
133 [2] = DEFINE_RES_DMA(DMACH_PCM0_RX),
134};
135
136struct platform_device s5pc100_device_pcm0 = {
137 .name = "samsung-pcm",
138 .id = 0,
139 .num_resources = ARRAY_SIZE(s5pc100_pcm0_resource),
140 .resource = s5pc100_pcm0_resource,
141 .dev = {
142 .platform_data = &s3c_pcm_pdata,
143 },
144};
145
146static struct resource s5pc100_pcm1_resource[] = {
147 [0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256),
148 [1] = DEFINE_RES_DMA(DMACH_PCM1_TX),
149 [2] = DEFINE_RES_DMA(DMACH_PCM1_RX),
150};
151
152struct platform_device s5pc100_device_pcm1 = {
153 .name = "samsung-pcm",
154 .id = 1,
155 .num_resources = ARRAY_SIZE(s5pc100_pcm1_resource),
156 .resource = s5pc100_pcm1_resource,
157 .dev = {
158 .platform_data = &s3c_pcm_pdata,
159 },
160};
161
162/* AC97 Controller platform devices */
163
164static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev)
165{
166 return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4));
167}
168
169static struct resource s5pc100_ac97_resource[] = {
170 [0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256),
171 [1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT),
172 [2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN),
173 [3] = DEFINE_RES_DMA(DMACH_AC97_MICIN),
174 [4] = DEFINE_RES_IRQ(IRQ_AC97),
175};
176
177static struct s3c_audio_pdata s3c_ac97_pdata = {
178 .cfg_gpio = s5pc100_ac97_cfg_gpio,
179};
180
181static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32);
182
183struct platform_device s5pc100_device_ac97 = {
184 .name = "samsung-ac97",
185 .id = -1,
186 .num_resources = ARRAY_SIZE(s5pc100_ac97_resource),
187 .resource = s5pc100_ac97_resource,
188 .dev = {
189 .platform_data = &s3c_ac97_pdata,
190 .dma_mask = &s5pc100_ac97_dmamask,
191 .coherent_dma_mask = DMA_BIT_MASK(32),
192 },
193};
194
195/* S/PDIF Controller platform_device */
196static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev)
197{
198 s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3));
199
200 return 0;
201}
202
203static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev)
204{
205 s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3));
206
207 return 0;
208}
209
210static struct resource s5pc100_spdif_resource[] = {
211 [0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256),
212 [1] = DEFINE_RES_DMA(DMACH_SPDIF),
213};
214
215static struct s3c_audio_pdata s5p_spdif_pdata = {
216 .cfg_gpio = s5pc100_spdif_cfg_gpd,
217};
218
219static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32);
220
221struct platform_device s5pc100_device_spdif = {
222 .name = "samsung-spdif",
223 .id = -1,
224 .num_resources = ARRAY_SIZE(s5pc100_spdif_resource),
225 .resource = s5pc100_spdif_resource,
226 .dev = {
227 .platform_data = &s5p_spdif_pdata,
228 .dma_mask = &s5pc100_spdif_dmamask,
229 .coherent_dma_mask = DMA_BIT_MASK(32),
230 },
231};
232
233void __init s5pc100_spdif_setup_gpio(int gpio)
234{
235 if (gpio == S5PC100_SPDIF_GPD)
236 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd;
237 else
238 s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3;
239}
diff --git a/arch/arm/mach-s5pc100/dma.c b/arch/arm/mach-s5pc100/dma.c
deleted file mode 100644
index b1418409709e..000000000000
--- a/arch/arm/mach-s5pc100/dma.c
+++ /dev/null
@@ -1,130 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/dma.c
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
7 * Jaswinder Singh <jassi.brar@samsung.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
22 */
23
24#include <linux/dma-mapping.h>
25#include <linux/amba/bus.h>
26#include <linux/amba/pl330.h>
27
28#include <asm/irq.h>
29#include <plat/devs.h>
30#include <plat/irqs.h>
31
32#include <mach/map.h>
33#include <mach/irqs.h>
34#include <mach/dma.h>
35
36static u8 pdma0_peri[] = {
37 DMACH_UART0_RX,
38 DMACH_UART0_TX,
39 DMACH_UART1_RX,
40 DMACH_UART1_TX,
41 DMACH_UART2_RX,
42 DMACH_UART2_TX,
43 DMACH_UART3_RX,
44 DMACH_UART3_TX,
45 DMACH_IRDA,
46 DMACH_I2S0_RX,
47 DMACH_I2S0_TX,
48 DMACH_I2S0S_TX,
49 DMACH_I2S1_RX,
50 DMACH_I2S1_TX,
51 DMACH_I2S2_RX,
52 DMACH_I2S2_TX,
53 DMACH_SPI0_RX,
54 DMACH_SPI0_TX,
55 DMACH_SPI1_RX,
56 DMACH_SPI1_TX,
57 DMACH_SPI2_RX,
58 DMACH_SPI2_TX,
59 DMACH_AC97_MICIN,
60 DMACH_AC97_PCMIN,
61 DMACH_AC97_PCMOUT,
62 DMACH_EXTERNAL,
63 DMACH_PWM,
64 DMACH_SPDIF,
65 DMACH_HSI_RX,
66 DMACH_HSI_TX,
67};
68
69static struct dma_pl330_platdata s5pc100_pdma0_pdata = {
70 .nr_valid_peri = ARRAY_SIZE(pdma0_peri),
71 .peri_id = pdma0_peri,
72};
73
74static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330,
75 S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata);
76
77static u8 pdma1_peri[] = {
78 DMACH_UART0_RX,
79 DMACH_UART0_TX,
80 DMACH_UART1_RX,
81 DMACH_UART1_TX,
82 DMACH_UART2_RX,
83 DMACH_UART2_TX,
84 DMACH_UART3_RX,
85 DMACH_UART3_TX,
86 DMACH_IRDA,
87 DMACH_I2S0_RX,
88 DMACH_I2S0_TX,
89 DMACH_I2S0S_TX,
90 DMACH_I2S1_RX,
91 DMACH_I2S1_TX,
92 DMACH_I2S2_RX,
93 DMACH_I2S2_TX,
94 DMACH_SPI0_RX,
95 DMACH_SPI0_TX,
96 DMACH_SPI1_RX,
97 DMACH_SPI1_TX,
98 DMACH_SPI2_RX,
99 DMACH_SPI2_TX,
100 DMACH_PCM0_RX,
101 DMACH_PCM0_TX,
102 DMACH_PCM1_RX,
103 DMACH_PCM1_TX,
104 DMACH_MSM_REQ0,
105 DMACH_MSM_REQ1,
106 DMACH_MSM_REQ2,
107 DMACH_MSM_REQ3,
108};
109
110static struct dma_pl330_platdata s5pc100_pdma1_pdata = {
111 .nr_valid_peri = ARRAY_SIZE(pdma1_peri),
112 .peri_id = pdma1_peri,
113};
114
115static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330,
116 S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata);
117
118static int __init s5pc100_dma_init(void)
119{
120 dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask);
121 dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask);
122 amba_device_register(&s5pc100_pdma0_device, &iomem_resource);
123
124 dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask);
125 dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask);
126 amba_device_register(&s5pc100_pdma1_device, &iomem_resource);
127
128 return 0;
129}
130arch_initcall(s5pc100_dma_init);
diff --git a/arch/arm/mach-s5pc100/include/mach/debug-macro.S b/arch/arm/mach-s5pc100/include/mach/debug-macro.S
deleted file mode 100644
index 22c23859e45e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/debug-macro.S
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 *
7 * Based on mach-s3c6400/include/mach/debug-macro.S
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12*/
13
14/* pull in the relevant register and map files. */
15
16#include <linux/serial_s3c.h>
17#include <mach/map.h>
18
19 /* note, for the boot process to work we have to keep the UART
20 * virtual address aligned to an 1MiB boundary for the L1
21 * mapping the head code makes. We keep the UART virtual address
22 * aligned and add in the offset when we load the value here.
23 */
24
25 .macro addruart, rp, rv, tmp
26 ldr \rp, = S3C_PA_UART
27 ldr \rv, = S3C_VA_UART
28#if CONFIG_DEBUG_S3C_UART != 0
29 add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART)
30 add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART)
31#endif
32 .endm
33
34/* include the reset of the code which will do the work, we're only
35 * compiling for a single cpu processor type so the default of s3c2440
36 * will be fine with us.
37 */
38
39#include <debug/samsung.S>
diff --git a/arch/arm/mach-s5pc100/include/mach/dma.h b/arch/arm/mach-s5pc100/include/mach/dma.h
deleted file mode 100644
index 201842a3769e..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/dma.h
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Copyright (C) 2010 Samsung Electronics Co. Ltd.
3 * Jaswinder Singh <jassi.brar@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
18 */
19
20#ifndef __MACH_DMA_H
21#define __MACH_DMA_H
22
23/* This platform uses the common DMA API driver for PL330 */
24#include <plat/dma-pl330.h>
25
26#endif /* __MACH_DMA_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/entry-macro.S b/arch/arm/mach-s5pc100/include/mach/entry-macro.S
deleted file mode 100644
index bad0700457db..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/entry-macro.S
+++ /dev/null
@@ -1,19 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/entry-macro.S
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Based on mach-s3c6400/include/mach/entry-macro.S
7 *
8 * Low-level IRQ helper macros for the Samsung S5PC1XX series
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13*/
14
15 .macro get_irqnr_preamble, base, tmp
16 .endm
17
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 .endm
diff --git a/arch/arm/mach-s5pc100/include/mach/gpio.h b/arch/arm/mach-s5pc100/include/mach/gpio.h
deleted file mode 100644
index 5e1a924b595f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/gpio.h
+++ /dev/null
@@ -1,144 +0,0 @@
1/* arch/arm/mach-s5pc100/include/mach/gpio.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - GPIO lib support
7 *
8 * Base on mach-s3c6400/include/mach/gpio.h
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#ifndef __ASM_ARCH_GPIO_H
16#define __ASM_ARCH_GPIO_H __FILE__
17
18/* GPIO bank sizes */
19#define S5PC100_GPIO_A0_NR (8)
20#define S5PC100_GPIO_A1_NR (5)
21#define S5PC100_GPIO_B_NR (8)
22#define S5PC100_GPIO_C_NR (5)
23#define S5PC100_GPIO_D_NR (7)
24#define S5PC100_GPIO_E0_NR (8)
25#define S5PC100_GPIO_E1_NR (6)
26#define S5PC100_GPIO_F0_NR (8)
27#define S5PC100_GPIO_F1_NR (8)
28#define S5PC100_GPIO_F2_NR (8)
29#define S5PC100_GPIO_F3_NR (4)
30#define S5PC100_GPIO_G0_NR (8)
31#define S5PC100_GPIO_G1_NR (3)
32#define S5PC100_GPIO_G2_NR (7)
33#define S5PC100_GPIO_G3_NR (7)
34#define S5PC100_GPIO_H0_NR (8)
35#define S5PC100_GPIO_H1_NR (8)
36#define S5PC100_GPIO_H2_NR (8)
37#define S5PC100_GPIO_H3_NR (8)
38#define S5PC100_GPIO_I_NR (8)
39#define S5PC100_GPIO_J0_NR (8)
40#define S5PC100_GPIO_J1_NR (5)
41#define S5PC100_GPIO_J2_NR (8)
42#define S5PC100_GPIO_J3_NR (8)
43#define S5PC100_GPIO_J4_NR (4)
44#define S5PC100_GPIO_K0_NR (8)
45#define S5PC100_GPIO_K1_NR (6)
46#define S5PC100_GPIO_K2_NR (8)
47#define S5PC100_GPIO_K3_NR (8)
48#define S5PC100_GPIO_L0_NR (8)
49#define S5PC100_GPIO_L1_NR (8)
50#define S5PC100_GPIO_L2_NR (8)
51#define S5PC100_GPIO_L3_NR (8)
52#define S5PC100_GPIO_L4_NR (8)
53
54/* GPIO bank numbes */
55
56/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
57 * space for debugging purposes so that any accidental
58 * change from one gpio bank to another can be caught.
59*/
60
61#define S5PC100_GPIO_NEXT(__gpio) \
62 ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
63
64enum s5p_gpio_number {
65 S5PC100_GPIO_A0_START = 0,
66 S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
67 S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
68 S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
69 S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
70 S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
71 S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
72 S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
73 S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
74 S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
75 S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
76 S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
77 S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
78 S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
79 S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
80 S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
81 S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
82 S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
83 S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
84 S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
85 S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
86 S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
87 S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
88 S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
89 S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
90 S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
91 S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
92 S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
93 S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
94 S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
95 S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
96 S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
97 S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
98 S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
99 S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
100};
101
102/* S5PC100 GPIO number definitions. */
103#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr))
104#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr))
105#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr))
106#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr))
107#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr))
108#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr))
109#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr))
110#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr))
111#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr))
112#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr))
113#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr))
114#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr))
115#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr))
116#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr))
117#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr))
118#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr))
119#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr))
120#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr))
121#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr))
122#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr))
123#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr))
124#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr))
125#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr))
126#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr))
127#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr))
128#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr))
129#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr))
130#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr))
131#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr))
132#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr))
133#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr))
134#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
135#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
136#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
137
138/* It used the end of the S5PC100 gpios */
139#define S3C_GPIO_END S5PC100_GPIO_END
140
141/* define the number of gpios we need to the one after the MP04() range */
142#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
143
144#endif /* __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/hardware.h b/arch/arm/mach-s5pc100/include/mach/hardware.h
deleted file mode 100644
index 6b38618c2fd9..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/hardware.h
+++ /dev/null
@@ -1,14 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - Hardware support
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H __FILE__
11
12/* currently nothing here, placeholder */
13
14#endif /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/irqs.h b/arch/arm/mach-s5pc100/include/mach/irqs.h
deleted file mode 100644
index d2eb4757381f..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/irqs.h
+++ /dev/null
@@ -1,115 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - IRQ definitions
7 */
8
9#ifndef __ASM_ARCH_IRQS_H
10#define __ASM_ARCH_IRQS_H __FILE__
11
12#include <plat/irqs.h>
13
14/* VIC0: system, DMA, timer */
15#define IRQ_EINT16_31 S5P_IRQ_VIC0(16)
16#define IRQ_BATF S5P_IRQ_VIC0(17)
17#define IRQ_MDMA S5P_IRQ_VIC0(18)
18#define IRQ_PDMA0 S5P_IRQ_VIC0(19)
19#define IRQ_PDMA1 S5P_IRQ_VIC0(20)
20#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21)
21#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22)
22#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23)
23#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24)
24#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25)
25#define IRQ_SYSTIMER S5P_IRQ_VIC0(26)
26#define IRQ_WDT S5P_IRQ_VIC0(27)
27#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28)
28#define IRQ_RTC_TIC S5P_IRQ_VIC0(29)
29#define IRQ_GPIOINT S5P_IRQ_VIC0(30)
30
31/* VIC1: ARM, power, memory, connectivity */
32#define IRQ_PMU S5P_IRQ_VIC1(0)
33#define IRQ_CORTEX1 S5P_IRQ_VIC1(1)
34#define IRQ_CORTEX2 S5P_IRQ_VIC1(2)
35#define IRQ_CORTEX3 S5P_IRQ_VIC1(3)
36#define IRQ_CORTEX4 S5P_IRQ_VIC1(4)
37#define IRQ_IEMAPC S5P_IRQ_VIC1(5)
38#define IRQ_IEMIEC S5P_IRQ_VIC1(6)
39#define IRQ_ONENAND S5P_IRQ_VIC1(7)
40#define IRQ_NFC S5P_IRQ_VIC1(8)
41#define IRQ_CFCON S5P_IRQ_VIC1(9)
42#define IRQ_UART0 S5P_IRQ_VIC1(10)
43#define IRQ_UART1 S5P_IRQ_VIC1(11)
44#define IRQ_UART2 S5P_IRQ_VIC1(12)
45#define IRQ_UART3 S5P_IRQ_VIC1(13)
46#define IRQ_IIC S5P_IRQ_VIC1(14)
47#define IRQ_SPI0 S5P_IRQ_VIC1(15)
48#define IRQ_SPI1 S5P_IRQ_VIC1(16)
49#define IRQ_SPI2 S5P_IRQ_VIC1(17)
50#define IRQ_IRDA S5P_IRQ_VIC1(18)
51#define IRQ_IIC2 S5P_IRQ_VIC1(19)
52#define IRQ_IIC3 S5P_IRQ_VIC1(20)
53#define IRQ_HSIRX S5P_IRQ_VIC1(21)
54#define IRQ_HSITX S5P_IRQ_VIC1(22)
55#define IRQ_UHOST S5P_IRQ_VIC1(23)
56#define IRQ_OTG S5P_IRQ_VIC1(24)
57#define IRQ_MSM S5P_IRQ_VIC1(25)
58#define IRQ_HSMMC0 S5P_IRQ_VIC1(26)
59#define IRQ_HSMMC1 S5P_IRQ_VIC1(27)
60#define IRQ_HSMMC2 S5P_IRQ_VIC1(28)
61#define IRQ_MIPICSI S5P_IRQ_VIC1(29)
62#define IRQ_MIPIDSI S5P_IRQ_VIC1(30)
63
64/* VIC2: multimedia, audio, security */
65#define IRQ_LCD0 S5P_IRQ_VIC2(0)
66#define IRQ_LCD1 S5P_IRQ_VIC2(1)
67#define IRQ_LCD2 S5P_IRQ_VIC2(2)
68#define IRQ_LCD3 S5P_IRQ_VIC2(3)
69#define IRQ_ROTATOR S5P_IRQ_VIC2(4)
70#define IRQ_FIMC0 S5P_IRQ_VIC2(5)
71#define IRQ_FIMC1 S5P_IRQ_VIC2(6)
72#define IRQ_FIMC2 S5P_IRQ_VIC2(7)
73#define IRQ_JPEG S5P_IRQ_VIC2(8)
74#define IRQ_2D S5P_IRQ_VIC2(9)
75#define IRQ_3D S5P_IRQ_VIC2(10)
76#define IRQ_MIXER S5P_IRQ_VIC2(11)
77#define IRQ_HDMI S5P_IRQ_VIC2(12)
78#define IRQ_IIC1 S5P_IRQ_VIC2(13)
79#define IRQ_MFC S5P_IRQ_VIC2(14)
80#define IRQ_TVENC S5P_IRQ_VIC2(15)
81#define IRQ_I2S0 S5P_IRQ_VIC2(16)
82#define IRQ_I2S1 S5P_IRQ_VIC2(17)
83#define IRQ_I2S2 S5P_IRQ_VIC2(18)
84#define IRQ_AC97 S5P_IRQ_VIC2(19)
85#define IRQ_PCM0 S5P_IRQ_VIC2(20)
86#define IRQ_PCM1 S5P_IRQ_VIC2(21)
87#define IRQ_SPDIF S5P_IRQ_VIC2(22)
88#define IRQ_ADC S5P_IRQ_VIC2(23)
89#define IRQ_PENDN S5P_IRQ_VIC2(24)
90#define IRQ_TC IRQ_PENDN
91#define IRQ_KEYPAD S5P_IRQ_VIC2(25)
92#define IRQ_CG S5P_IRQ_VIC2(26)
93#define IRQ_SEC S5P_IRQ_VIC2(27)
94#define IRQ_SECRX S5P_IRQ_VIC2(28)
95#define IRQ_SECTX S5P_IRQ_VIC2(29)
96#define IRQ_SDMIRQ S5P_IRQ_VIC2(30)
97#define IRQ_SDMFIQ S5P_IRQ_VIC2(31)
98#define IRQ_VIC_END S5P_IRQ_VIC2(31)
99
100#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0))
101#define S5P_EINT_BASE2 (IRQ_VIC_END + 1)
102
103/* GPIO interrupt */
104#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1)
105#define S5P_GPIOINT_GROUP_MAXNR 21
106
107/* Set the default NR_IRQS */
108#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1)
109
110/* Compatibility */
111#define IRQ_LCD_FIFO IRQ_LCD0
112#define IRQ_LCD_VSYNC IRQ_LCD1
113#define IRQ_LCD_SYSTEM IRQ_LCD2
114
115#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/map.h b/arch/arm/mach-s5pc100/include/mach/map.h
deleted file mode 100644
index 2550b6112b82..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/map.h
+++ /dev/null
@@ -1,137 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/map.h
2 *
3 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * Copyright 2009 Samsung Electronics Co.
7 * Byungho Min <bhmin@samsung.com>
8 *
9 * S5PC100 - Memory map definitions
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14*/
15
16#ifndef __ASM_ARCH_MAP_H
17#define __ASM_ARCH_MAP_H __FILE__
18
19#include <plat/map-base.h>
20#include <plat/map-s5p.h>
21
22#define S5PC100_PA_SDRAM 0x20000000
23
24#define S5PC100_PA_ONENAND 0xE7100000
25#define S5PC100_PA_ONENAND_BUF 0xB0000000
26
27#define S5PC100_PA_CHIPID 0xE0000000
28
29#define S5PC100_PA_SYSCON 0xE0100000
30
31#define S5PC100_PA_OTHERS 0xE0200000
32
33#define S5PC100_PA_GPIO 0xE0300000
34
35#define S5PC100_PA_VIC0 0xE4000000
36#define S5PC100_PA_VIC1 0xE4100000
37#define S5PC100_PA_VIC2 0xE4200000
38
39#define S5PC100_PA_SROMC 0xE7000000
40
41#define S5PC100_PA_CFCON 0xE7800000
42
43#define S5PC100_PA_MDMA 0xE8100000
44#define S5PC100_PA_PDMA0 0xE9000000
45#define S5PC100_PA_PDMA1 0xE9200000
46
47#define S5PC100_PA_TIMER 0xEA000000
48#define S5PC100_PA_SYSTIMER 0xEA100000
49#define S5PC100_PA_WATCHDOG 0xEA200000
50#define S5PC100_PA_RTC 0xEA300000
51
52#define S5PC100_PA_UART 0xEC000000
53
54#define S5PC100_PA_IIC0 0xEC100000
55#define S5PC100_PA_IIC1 0xEC200000
56
57#define S5PC100_PA_SPI0 0xEC300000
58#define S5PC100_PA_SPI1 0xEC400000
59#define S5PC100_PA_SPI2 0xEC500000
60
61#define S5PC100_PA_USB_HSOTG 0xED200000
62#define S5PC100_PA_USB_HSPHY 0xED300000
63
64#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000))
65
66#define S5PC100_PA_FB 0xEE000000
67
68#define S5PC100_PA_FIMC0 0xEE200000
69#define S5PC100_PA_FIMC1 0xEE300000
70#define S5PC100_PA_FIMC2 0xEE400000
71
72#define S5PC100_PA_I2S0 0xF2000000
73#define S5PC100_PA_I2S1 0xF2100000
74#define S5PC100_PA_I2S2 0xF2200000
75
76#define S5PC100_PA_AC97 0xF2300000
77
78#define S5PC100_PA_PCM0 0xF2400000
79#define S5PC100_PA_PCM1 0xF2500000
80
81#define S5PC100_PA_SPDIF 0xF2600000
82
83#define S5PC100_PA_TSADC 0xF3000000
84
85#define S5PC100_PA_KEYPAD 0xF3100000
86
87/* Compatibiltiy Defines */
88
89#define S3C_PA_FB S5PC100_PA_FB
90#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0)
91#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1)
92#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2)
93#define S3C_PA_IIC S5PC100_PA_IIC0
94#define S3C_PA_IIC1 S5PC100_PA_IIC1
95#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD
96#define S3C_PA_ONENAND S5PC100_PA_ONENAND
97#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF
98#define S3C_PA_RTC S5PC100_PA_RTC
99#define S3C_PA_TSADC S5PC100_PA_TSADC
100#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG
101#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY
102#define S3C_PA_WDT S5PC100_PA_WATCHDOG
103#define S3C_PA_SPI0 S5PC100_PA_SPI0
104#define S3C_PA_SPI1 S5PC100_PA_SPI1
105#define S3C_PA_SPI2 S5PC100_PA_SPI2
106
107#define S5P_PA_CHIPID S5PC100_PA_CHIPID
108#define S5P_PA_FIMC0 S5PC100_PA_FIMC0
109#define S5P_PA_FIMC1 S5PC100_PA_FIMC1
110#define S5P_PA_FIMC2 S5PC100_PA_FIMC2
111#define S5P_PA_SDRAM S5PC100_PA_SDRAM
112#define S5P_PA_SROMC S5PC100_PA_SROMC
113#define S5P_PA_SYSCON S5PC100_PA_SYSCON
114#define S5P_PA_TIMER S5PC100_PA_TIMER
115
116#define SAMSUNG_PA_ADC S5PC100_PA_TSADC
117#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON
118#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD
119#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER
120
121#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000)
122
123#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M)
124
125/* UART */
126
127#define S3C_PA_UART S5PC100_PA_UART
128
129#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET))
130#define S5P_PA_UART0 S5P_PA_UART(0)
131#define S5P_PA_UART1 S5P_PA_UART(1)
132#define S5P_PA_UART2 S5P_PA_UART(2)
133#define S5P_PA_UART3 S5P_PA_UART(3)
134
135#define S5P_SZ_UART SZ_256
136
137#endif /* __ASM_ARCH_MAP_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-clock.h b/arch/arm/mach-s5pc100/include/mach/regs-clock.h
deleted file mode 100644
index bc92da2e0ba2..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-clock.h
+++ /dev/null
@@ -1,80 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * S5PC100 - Clock register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_CLOCK_H
14#define __ASM_ARCH_REGS_CLOCK_H __FILE__
15
16#include <mach/map.h>
17
18#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
19
20#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x))
21
22#define S5P_APLL_LOCK S5P_CLKREG(0x00)
23#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
24#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
25#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
26
27#define S5P_APLL_CON S5P_CLKREG(0x100)
28#define S5P_MPLL_CON S5P_CLKREG(0x104)
29#define S5P_EPLL_CON S5P_CLKREG(0x108)
30#define S5P_HPLL_CON S5P_CLKREG(0x10C)
31
32#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
33#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
34#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
35#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
36
37#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
38#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
39#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
40#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
41#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
42
43#define S5P_CLK_OUT S5P_CLKREG(0x400)
44
45#define S5P_CLKGATE_D00 S5P_CLKREG(0x500)
46#define S5P_CLKGATE_D01 S5P_CLKREG(0x504)
47#define S5P_CLKGATE_D02 S5P_CLKREG(0x508)
48
49#define S5P_CLKGATE_D10 S5P_CLKREG(0x520)
50#define S5P_CLKGATE_D11 S5P_CLKREG(0x524)
51#define S5P_CLKGATE_D12 S5P_CLKREG(0x528)
52#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C)
53#define S5P_CLKGATE_D14 S5P_CLKREG(0x530)
54#define S5P_CLKGATE_D15 S5P_CLKREG(0x534)
55
56#define S5P_CLKGATE_D20 S5P_CLKREG(0x540)
57
58#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560)
59#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564)
60
61/* CLKDIV0 */
62#define S5P_CLKDIV0_D0_MASK (0x7<<8)
63#define S5P_CLKDIV0_D0_SHIFT (8)
64#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
65#define S5P_CLKDIV0_PCLKD0_SHIFT (12)
66
67/* CLKDIV1 */
68#define S5P_CLKDIV1_D1_MASK (0x7<<12)
69#define S5P_CLKDIV1_D1_SHIFT (12)
70#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
71#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
72
73#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000)
74#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200)
75
76#define S5PC100_SWRESET_RESETVAL 0xc100
77
78#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30
79
80#endif /* __ASM_ARCH_REGS_CLOCK_H */
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h b/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
deleted file mode 100644
index 0bf73209ec7b..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-gpio.h
+++ /dev/null
@@ -1,38 +0,0 @@
1/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - GPIO register definitions
7 */
8
9#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
10#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
11
12#include <mach/map.h>
13
14#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00)
15#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4))
16
17#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80)
18#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4))
19
20#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00)
21#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4))
22
23#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40)
24#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4))
25
26#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3)
27
28#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7))
29
30#define EINT_MODE S3C_GPIO_SFN(0x2)
31
32#define EINT_GPIO_0(x) S5PC100_GPH0(x)
33#define EINT_GPIO_1(x) S5PC100_GPH1(x)
34#define EINT_GPIO_2(x) S5PC100_GPH2(x)
35#define EINT_GPIO_3(x) S5PC100_GPH3(x)
36
37#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
38
diff --git a/arch/arm/mach-s5pc100/include/mach/regs-irq.h b/arch/arm/mach-s5pc100/include/mach/regs-irq.h
deleted file mode 100644
index 761627897f30..000000000000
--- a/arch/arm/mach-s5pc100/include/mach/regs-irq.h
+++ /dev/null
@@ -1,18 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * S5PC100 - IRQ register definitions
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#ifndef __ASM_ARCH_REGS_IRQ_H
14#define __ASM_ARCH_REGS_IRQ_H __FILE__
15
16#include <mach/map.h>
17
18#endif /* __ASM_ARCH_REGS_IRQ_H */
diff --git a/arch/arm/mach-s5pc100/mach-smdkc100.c b/arch/arm/mach-s5pc100/mach-smdkc100.c
deleted file mode 100644
index 668af3ac31f3..000000000000
--- a/arch/arm/mach-s5pc100/mach-smdkc100.c
+++ /dev/null
@@ -1,264 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Author: Byungho Min <bhmin@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/list.h>
16#include <linux/timer.h>
17#include <linux/init.h>
18#include <linux/serial_core.h>
19#include <linux/serial_s3c.h>
20#include <linux/platform_device.h>
21#include <linux/io.h>
22#include <linux/gpio.h>
23#include <linux/i2c.h>
24#include <linux/fb.h>
25#include <linux/delay.h>
26#include <linux/input.h>
27#include <linux/pwm_backlight.h>
28
29#include <asm/mach/arch.h>
30#include <asm/mach/map.h>
31
32#include <mach/map.h>
33#include <mach/regs-gpio.h>
34
35#include <video/platform_lcd.h>
36#include <video/samsung_fimd.h>
37
38#include <asm/irq.h>
39#include <asm/mach-types.h>
40
41#include <plat/gpio-cfg.h>
42
43#include <plat/clock.h>
44#include <plat/devs.h>
45#include <plat/cpu.h>
46#include <plat/fb.h>
47#include <linux/platform_data/i2c-s3c2410.h>
48#include <linux/platform_data/ata-samsung_cf.h>
49#include <plat/adc.h>
50#include <plat/keypad.h>
51#include <linux/platform_data/touchscreen-s3c2410.h>
52#include <linux/platform_data/asoc-s3c.h>
53#include <plat/backlight.h>
54#include <plat/samsung-time.h>
55
56#include "common.h"
57
58/* Following are default values for UCON, ULCON and UFCON UART registers */
59#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \
60 S3C2410_UCON_RXILEVEL | \
61 S3C2410_UCON_TXIRQMODE | \
62 S3C2410_UCON_RXIRQMODE | \
63 S3C2410_UCON_RXFIFO_TOI | \
64 S3C2443_UCON_RXERR_IRQEN)
65
66#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8
67
68#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \
69 S3C2440_UFCON_RXTRIG8 | \
70 S3C2440_UFCON_TXTRIG16)
71
72static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = {
73 [0] = {
74 .hwport = 0,
75 .flags = 0,
76 .ucon = SMDKC100_UCON_DEFAULT,
77 .ulcon = SMDKC100_ULCON_DEFAULT,
78 .ufcon = SMDKC100_UFCON_DEFAULT,
79 },
80 [1] = {
81 .hwport = 1,
82 .flags = 0,
83 .ucon = SMDKC100_UCON_DEFAULT,
84 .ulcon = SMDKC100_ULCON_DEFAULT,
85 .ufcon = SMDKC100_UFCON_DEFAULT,
86 },
87 [2] = {
88 .hwport = 2,
89 .flags = 0,
90 .ucon = SMDKC100_UCON_DEFAULT,
91 .ulcon = SMDKC100_ULCON_DEFAULT,
92 .ufcon = SMDKC100_UFCON_DEFAULT,
93 },
94 [3] = {
95 .hwport = 3,
96 .flags = 0,
97 .ucon = SMDKC100_UCON_DEFAULT,
98 .ulcon = SMDKC100_ULCON_DEFAULT,
99 .ufcon = SMDKC100_UFCON_DEFAULT,
100 },
101};
102
103/* I2C0 */
104static struct i2c_board_info i2c_devs0[] __initdata = {
105 {I2C_BOARD_INFO("wm8580", 0x1b),},
106};
107
108/* I2C1 */
109static struct i2c_board_info i2c_devs1[] __initdata = {
110};
111
112/* LCD power controller */
113static void smdkc100_lcd_power_set(struct plat_lcd_data *pd,
114 unsigned int power)
115{
116 if (power) {
117 /* module reset */
118 gpio_direction_output(S5PC100_GPH0(6), 1);
119 mdelay(100);
120 gpio_direction_output(S5PC100_GPH0(6), 0);
121 mdelay(10);
122 gpio_direction_output(S5PC100_GPH0(6), 1);
123 mdelay(10);
124 }
125}
126
127static struct plat_lcd_data smdkc100_lcd_power_data = {
128 .set_power = smdkc100_lcd_power_set,
129};
130
131static struct platform_device smdkc100_lcd_powerdev = {
132 .name = "platform-lcd",
133 .dev.parent = &s3c_device_fb.dev,
134 .dev.platform_data = &smdkc100_lcd_power_data,
135};
136
137/* Frame Buffer */
138static struct s3c_fb_pd_win smdkc100_fb_win0 = {
139 .max_bpp = 32,
140 .default_bpp = 16,
141 .xres = 800,
142 .yres = 480,
143};
144
145static struct fb_videomode smdkc100_lcd_timing = {
146 .left_margin = 8,
147 .right_margin = 13,
148 .upper_margin = 7,
149 .lower_margin = 5,
150 .hsync_len = 3,
151 .vsync_len = 1,
152 .xres = 800,
153 .yres = 480,
154 .refresh = 80,
155};
156
157static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = {
158 .win[0] = &smdkc100_fb_win0,
159 .vtiming = &smdkc100_lcd_timing,
160 .vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
161 .vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
162 .setup_gpio = s5pc100_fb_gpio_setup_24bpp,
163};
164
165static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = {
166 .setup_gpio = s5pc100_ide_setup_gpio,
167};
168
169static uint32_t smdkc100_keymap[] __initdata = {
170 /* KEY(row, col, keycode) */
171 KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3),
172 KEY(0, 6, KEY_4), KEY(0, 7, KEY_5),
173 KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C),
174 KEY(1, 6, KEY_D), KEY(1, 7, KEY_E)
175};
176
177static struct matrix_keymap_data smdkc100_keymap_data __initdata = {
178 .keymap = smdkc100_keymap,
179 .keymap_size = ARRAY_SIZE(smdkc100_keymap),
180};
181
182static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = {
183 .keymap_data = &smdkc100_keymap_data,
184 .rows = 2,
185 .cols = 8,
186};
187
188static struct platform_device *smdkc100_devices[] __initdata = {
189 &s3c_device_adc,
190 &s3c_device_cfcon,
191 &s3c_device_i2c0,
192 &s3c_device_i2c1,
193 &s3c_device_fb,
194 &s3c_device_hsmmc0,
195 &s3c_device_hsmmc1,
196 &s3c_device_hsmmc2,
197 &samsung_device_pwm,
198 &s3c_device_ts,
199 &s3c_device_wdt,
200 &smdkc100_lcd_powerdev,
201 &s5pc100_device_iis0,
202 &samsung_device_keypad,
203 &s5pc100_device_ac97,
204 &s3c_device_rtc,
205 &s5p_device_fimc0,
206 &s5p_device_fimc1,
207 &s5p_device_fimc2,
208 &s5pc100_device_spdif,
209};
210
211/* LCD Backlight data */
212static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = {
213 .no = S5PC100_GPD(0),
214 .func = S3C_GPIO_SFN(2),
215};
216
217static struct platform_pwm_backlight_data smdkc100_bl_data = {
218 .pwm_id = 0,
219 .enable_gpio = -1,
220};
221
222static void __init smdkc100_map_io(void)
223{
224 s5pc100_init_io(NULL, 0);
225 s3c24xx_init_clocks(12000000);
226 s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs));
227 samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4);
228}
229
230static void __init smdkc100_machine_init(void)
231{
232 s3c24xx_ts_set_platdata(NULL);
233
234 /* I2C */
235 s3c_i2c0_set_platdata(NULL);
236 s3c_i2c1_set_platdata(NULL);
237 i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0));
238 i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1));
239
240 s3c_fb_set_platdata(&smdkc100_lcd_pdata);
241 s3c_ide_set_platdata(&smdkc100_ide_pdata);
242
243 samsung_keypad_set_platdata(&smdkc100_keypad_data);
244
245 s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD);
246
247 /* LCD init */
248 gpio_request(S5PC100_GPH0(6), "GPH0");
249 smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0);
250
251 platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices));
252
253 samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data);
254}
255
256MACHINE_START(SMDKC100, "SMDKC100")
257 /* Maintainer: Byungho Min <bhmin@samsung.com> */
258 .atag_offset = 0x100,
259 .init_irq = s5pc100_init_irq,
260 .map_io = smdkc100_map_io,
261 .init_machine = smdkc100_machine_init,
262 .init_time = samsung_timer_init,
263 .restart = s5pc100_restart,
264MACHINE_END
diff --git a/arch/arm/mach-s5pc100/setup-fb-24bpp.c b/arch/arm/mach-s5pc100/setup-fb-24bpp.c
deleted file mode 100644
index 8978e4cf9ed5..000000000000
--- a/arch/arm/mach-s5pc100/setup-fb-24bpp.c
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
3 *
4 * Copyright 2009 Samsung Electronics
5 *
6 * Base S5PC100 setup information for 24bpp LCD framebuffer
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/types.h>
15#include <linux/fb.h>
16#include <linux/gpio.h>
17
18#include <mach/map.h>
19#include <plat/fb.h>
20#include <plat/gpio-cfg.h>
21
22#define DISR_OFFSET 0x7008
23
24static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr)
25{
26 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2));
27}
28
29void s5pc100_fb_gpio_setup_24bpp(void)
30{
31 s5pc100_fb_setgpios(S5PC100_GPF0(0), 8);
32 s5pc100_fb_setgpios(S5PC100_GPF1(0), 8);
33 s5pc100_fb_setgpios(S5PC100_GPF2(0), 8);
34 s5pc100_fb_setgpios(S5PC100_GPF3(0), 4);
35}
diff --git a/arch/arm/mach-s5pc100/setup-i2c0.c b/arch/arm/mach-s5pc100/setup-i2c0.c
deleted file mode 100644
index 89a6a769d622..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c0.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Base S5PC100 I2C bus 0 gpio configuration
7 *
8 * Based on plat-s3c64xx/setup-i2c0.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <linux/gpio.h>
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c0_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPD(3), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pc100/setup-i2c1.c b/arch/arm/mach-s5pc100/setup-i2c1.c
deleted file mode 100644
index faa667ef02cb..000000000000
--- a/arch/arm/mach-s5pc100/setup-i2c1.c
+++ /dev/null
@@ -1,28 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
2 *
3 * Copyright 2009 Samsung Electronics Co.
4 * Byungho Min <bhmin@samsung.com>
5 *
6 * Base S5PC100 I2C bus 1 gpio configuration
7 *
8 * Based on plat-s3c64xx/setup-i2c1.c
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13*/
14
15#include <linux/kernel.h>
16#include <linux/types.h>
17
18struct platform_device; /* don't need the contents */
19
20#include <linux/gpio.h>
21#include <linux/platform_data/i2c-s3c2410.h>
22#include <plat/gpio-cfg.h>
23
24void s3c_i2c1_cfg_gpio(struct platform_device *dev)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPD(5), 2,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28}
diff --git a/arch/arm/mach-s5pc100/setup-ide.c b/arch/arm/mach-s5pc100/setup-ide.c
deleted file mode 100644
index 223aae044466..000000000000
--- a/arch/arm/mach-s5pc100/setup-ide.c
+++ /dev/null
@@ -1,57 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-ide.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
5 *
6 * S5PC100 setup information for IDE
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/kernel.h>
14#include <linux/gpio.h>
15#include <linux/io.h>
16
17#include <mach/regs-clock.h>
18#include <plat/gpio-cfg.h>
19
20static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr)
21{
22 s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4));
23
24 for (; nr > 0; nr--, base++)
25 s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4);
26}
27
28void s5pc100_ide_setup_gpio(void)
29{
30 u32 reg;
31
32 /* Independent CF interface, CF chip select configuration */
33 reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f);
34 writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG);
35
36 /* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */
37 s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8);
38
39 /*CF_Data[0 - 7] */
40 s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8);
41
42 /* CF_Data[8 - 15] */
43 s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8);
44
45 /* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */
46 s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4);
47
48 /* EBI_OE, EBI_WE */
49 s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0));
50
51 /* CF_OE, CF_WE */
52 s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2));
53
54 /* CF_CD */
55 s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2));
56 s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE);
57}
diff --git a/arch/arm/mach-s5pc100/setup-keypad.c b/arch/arm/mach-s5pc100/setup-keypad.c
deleted file mode 100644
index ada377f0c206..000000000000
--- a/arch/arm/mach-s5pc100/setup-keypad.c
+++ /dev/null
@@ -1,23 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-keypad.c
2 *
3 * Copyright (c) 2010 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com/
5 *
6 * GPIO configuration for S5PC100 KeyPad device
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#include <linux/gpio.h>
14#include <plat/gpio-cfg.h>
15
16void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols)
17{
18 /* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */
19 s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3));
20
21 /* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */
22 s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3));
23}
diff --git a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c b/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
deleted file mode 100644
index 6010c0310cb5..000000000000
--- a/arch/arm/mach-s5pc100/setup-sdhci-gpio.c
+++ /dev/null
@@ -1,70 +0,0 @@
1/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
2 *
3 * Copyright 2009 Samsung Eletronics
4 *
5 * S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC)
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10*/
11
12#include <linux/kernel.h>
13#include <linux/types.h>
14#include <linux/interrupt.h>
15#include <linux/platform_device.h>
16#include <linux/io.h>
17#include <linux/gpio.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/card.h>
20
21#include <plat/gpio-cfg.h>
22#include <plat/sdhci.h>
23
24void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
25{
26 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
27 unsigned int num;
28
29 num = width;
30 /* In case of 8 width, we should decrease the 2 */
31 if (width == 8)
32 num = width - 2;
33
34 /* Set all the necessary GPG0/GPG1 pins to special-function 0 */
35 s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2));
36
37 if (width == 8)
38 s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2));
39
40 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
41 s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP);
42 s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2));
43 }
44}
45
46void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
47{
48 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
49
50 /* Set all the necessary GPG2 pins to special-function 2 */
51 s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2));
52
53 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
54 s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP);
55 s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2));
56 }
57}
58
59void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
60{
61 struct s3c_sdhci_platdata *pdata = dev->dev.platform_data;
62
63 /* Set all the necessary GPG3 pins to special-function 2 */
64 s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2));
65
66 if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) {
67 s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP);
68 s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2));
69 }
70}
diff --git a/arch/arm/mach-s5pc100/setup-spi.c b/arch/arm/mach-s5pc100/setup-spi.c
deleted file mode 100644
index 183567961de1..000000000000
--- a/arch/arm/mach-s5pc100/setup-spi.c
+++ /dev/null
@@ -1,41 +0,0 @@
1/* linux/arch/arm/mach-s5pc100/setup-spi.c
2 *
3 * Copyright (C) 2011 Samsung Electronics Ltd.
4 * http://www.samsung.com/
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include <linux/gpio.h>
12#include <plat/gpio-cfg.h>
13
14#ifdef CONFIG_S3C64XX_DEV_SPI0
15int s3c64xx_spi0_cfg_gpio(void)
16{
17 s3c_gpio_cfgall_range(S5PC100_GPB(0), 3,
18 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
19 return 0;
20}
21#endif
22
23#ifdef CONFIG_S3C64XX_DEV_SPI1
24int s3c64xx_spi1_cfg_gpio(void)
25{
26 s3c_gpio_cfgall_range(S5PC100_GPB(4), 3,
27 S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP);
28 return 0;
29}
30#endif
31
32#ifdef CONFIG_S3C64XX_DEV_SPI2
33int s3c64xx_spi2_cfg_gpio(void)
34{
35 s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3));
36 s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP);
37 s3c_gpio_cfgall_range(S5PC100_GPB(2), 2,
38 S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP);
39 return 0;
40}
41#endif
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index 301b892d97d9..1c629c2c270f 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -15,7 +15,7 @@ config PLAT_SAMSUNG
15 15
16config PLAT_S5P 16config PLAT_S5P
17 bool 17 bool
18 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 18 depends on ARCH_S5PV210
19 default y 19 default y
20 select ARCH_REQUIRE_GPIOLIB 20 select ARCH_REQUIRE_GPIOLIB
21 select ARM_VIC 21 select ARM_VIC
@@ -29,7 +29,7 @@ config PLAT_S5P
29 29
30config SAMSUNG_PM 30config SAMSUNG_PM
31 bool 31 bool
32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || ARCH_S5P64X0 || S5P_PM) 32 depends on PM && (PLAT_S3C24XX || ARCH_S3C64XX || S5P_PM)
33 default y 33 default y
34 help 34 help
35 Base platform power management code for samsung code 35 Base platform power management code for samsung code
@@ -78,14 +78,14 @@ config SAMSUNG_CLKSRC
78 used by newer systems such as the S3C64XX. 78 used by newer systems such as the S3C64XX.
79 79
80config S5P_CLOCK 80config S5P_CLOCK
81 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 81 def_bool ARCH_S5PV210
82 help 82 help
83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs 83 Support common clock part for ARCH_S5P and ARCH_EXYNOS SoCs
84 84
85# options for IRQ support 85# options for IRQ support
86 86
87config S5P_IRQ 87config S5P_IRQ
88 def_bool (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 88 def_bool ARCH_S5PV210
89 help 89 help
90 Support common interrupt part for ARCH_S5P SoCs 90 Support common interrupt part for ARCH_S5P SoCs
91 91
@@ -93,7 +93,6 @@ config S5P_EXT_INT
93 bool 93 bool
94 help 94 help
95 Use the external interrupts (other than GPIO interrupts.) 95 Use the external interrupts (other than GPIO interrupts.)
96 Note: Do not choose this for S5P6440 and S5P6450.
97 96
98config S5P_GPIO_INT 97config S5P_GPIO_INT
99 bool 98 bool
@@ -143,7 +142,7 @@ config S3C_GPIO_TRACK
143 142
144config S5P_DEV_UART 143config S5P_DEV_UART
145 def_bool y 144 def_bool y
146 depends on (ARCH_S5P64X0 || ARCH_S5PC100 || ARCH_S5PV210) 145 depends on ARCH_S5PV210
147 146
148# ADC driver 147# ADC driver
149 148
@@ -397,7 +396,7 @@ config SAMSUNG_PM_GPIO
397 396
398config SAMSUNG_DMADEV 397config SAMSUNG_DMADEV
399 bool "Use legacy Samsung DMA abstraction" 398 bool "Use legacy Samsung DMA abstraction"
400 depends on CPU_S5PV210 || CPU_S5PC100 || ARCH_S5P64X0 || ARCH_S3C64XX 399 depends on CPU_S5PV210 || ARCH_S3C64XX
401 select DMADEVICES 400 select DMADEVICES
402 default y 401 default y
403 help 402 help
@@ -474,7 +473,6 @@ config S5P_PM
474 bool 473 bool
475 help 474 help
476 Common code for power management support on S5P and newer SoCs 475 Common code for power management support on S5P and newer SoCs
477 Note: Do not select this for S5P6440 and S5P6450.
478 476
479config S5P_SLEEP 477config S5P_SLEEP
480 bool 478 bool
diff --git a/arch/arm/plat-samsung/adc.c b/arch/arm/plat-samsung/adc.c
index 79690f2f6d3f..468352633101 100644
--- a/arch/arm/plat-samsung/adc.c
+++ b/arch/arm/plat-samsung/adc.c
@@ -43,7 +43,7 @@ enum s3c_cpu_type {
43 TYPE_ADCV1, /* S3C24XX */ 43 TYPE_ADCV1, /* S3C24XX */
44 TYPE_ADCV11, /* S3C2443 */ 44 TYPE_ADCV11, /* S3C2443 */
45 TYPE_ADCV12, /* S3C2416, S3C2450 */ 45 TYPE_ADCV12, /* S3C2416, S3C2450 */
46 TYPE_ADCV2, /* S3C64XX, S5P64X0, S5PC100 */ 46 TYPE_ADCV2, /* S3C64XX */
47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */ 47 TYPE_ADCV3, /* S5PV210, S5PC110, EXYNOS4210 */
48}; 48};
49 49
diff --git a/arch/arm/plat-samsung/include/plat/cpu.h b/arch/arm/plat-samsung/include/plat/cpu.h
index 5a237db9f9eb..d1d4659025bb 100644
--- a/arch/arm/plat-samsung/include/plat/cpu.h
+++ b/arch/arm/plat-samsung/include/plat/cpu.h
@@ -33,13 +33,6 @@ extern unsigned long samsung_cpu_id;
33#define S3C6410_CPU_ID 0x36410000 33#define S3C6410_CPU_ID 0x36410000
34#define S3C64XX_CPU_MASK 0xFFFFF000 34#define S3C64XX_CPU_MASK 0xFFFFF000
35 35
36#define S5P6440_CPU_ID 0x56440000
37#define S5P6450_CPU_ID 0x36450000
38#define S5P64XX_CPU_MASK 0xFFFFF000
39
40#define S5PC100_CPU_ID 0x43100000
41#define S5PC100_CPU_MASK 0xFFFFF000
42
43#define S5PV210_CPU_ID 0x43110000 36#define S5PV210_CPU_ID 0x43110000
44#define S5PV210_CPU_MASK 0xFFFFF000 37#define S5PV210_CPU_MASK 0xFFFFF000
45 38
@@ -54,9 +47,6 @@ IS_SAMSUNG_CPU(s3c24xx, S3C24XX_CPU_ID, S3C24XX_CPU_MASK)
54IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK) 47IS_SAMSUNG_CPU(s3c2412, S3C2412_CPU_ID, S3C2412_CPU_MASK)
55IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK) 48IS_SAMSUNG_CPU(s3c6400, S3C6400_CPU_ID, S3C64XX_CPU_MASK)
56IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK) 49IS_SAMSUNG_CPU(s3c6410, S3C6410_CPU_ID, S3C64XX_CPU_MASK)
57IS_SAMSUNG_CPU(s5p6440, S5P6440_CPU_ID, S5P64XX_CPU_MASK)
58IS_SAMSUNG_CPU(s5p6450, S5P6450_CPU_ID, S5P64XX_CPU_MASK)
59IS_SAMSUNG_CPU(s5pc100, S5PC100_CPU_ID, S5PC100_CPU_MASK)
60IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK) 50IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
61 51
62#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \ 52#if defined(CONFIG_CPU_S3C2410) || defined(CONFIG_CPU_S3C2412) || \
@@ -86,24 +76,6 @@ IS_SAMSUNG_CPU(s5pv210, S5PV210_CPU_ID, S5PV210_CPU_MASK)
86# define soc_is_s3c64xx() 0 76# define soc_is_s3c64xx() 0
87#endif 77#endif
88 78
89#if defined(CONFIG_CPU_S5P6440)
90# define soc_is_s5p6440() is_samsung_s5p6440()
91#else
92# define soc_is_s5p6440() 0
93#endif
94
95#if defined(CONFIG_CPU_S5P6450)
96# define soc_is_s5p6450() is_samsung_s5p6450()
97#else
98# define soc_is_s5p6450() 0
99#endif
100
101#if defined(CONFIG_CPU_S5PC100)
102# define soc_is_s5pc100() is_samsung_s5pc100()
103#else
104# define soc_is_s5pc100() 0
105#endif
106
107#if defined(CONFIG_CPU_S5PV210) 79#if defined(CONFIG_CPU_S5PV210)
108# define soc_is_s5pv210() is_samsung_s5pv210() 80# define soc_is_s5pv210() is_samsung_s5pv210()
109#else 81#else
@@ -177,7 +149,6 @@ extern struct bus_type s3c2440_subsys;
177extern struct bus_type s3c2442_subsys; 149extern struct bus_type s3c2442_subsys;
178extern struct bus_type s3c2443_subsys; 150extern struct bus_type s3c2443_subsys;
179extern struct bus_type s3c6410_subsys; 151extern struct bus_type s3c6410_subsys;
180extern struct bus_type s5p64x0_subsys;
181extern struct bus_type s5pv210_subsys; 152extern struct bus_type s5pv210_subsys;
182 153
183extern void (*s5pc1xx_idle)(void); 154extern void (*s5pc1xx_idle)(void);
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index eece188ed188..5f5a28d08c2e 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -94,23 +94,6 @@ extern struct platform_device s5p_device_mixer;
94extern struct platform_device s5p_device_onenand; 94extern struct platform_device s5p_device_onenand;
95extern struct platform_device s5p_device_sdo; 95extern struct platform_device s5p_device_sdo;
96 96
97extern struct platform_device s5p6440_device_iis;
98extern struct platform_device s5p6440_device_pcm;
99
100extern struct platform_device s5p6450_device_iis0;
101extern struct platform_device s5p6450_device_iis1;
102extern struct platform_device s5p6450_device_iis2;
103extern struct platform_device s5p6450_device_pcm0;
104
105
106extern struct platform_device s5pc100_device_ac97;
107extern struct platform_device s5pc100_device_iis0;
108extern struct platform_device s5pc100_device_iis1;
109extern struct platform_device s5pc100_device_iis2;
110extern struct platform_device s5pc100_device_pcm0;
111extern struct platform_device s5pc100_device_pcm1;
112extern struct platform_device s5pc100_device_spdif;
113
114extern struct platform_device s5pv210_device_ac97; 97extern struct platform_device s5pv210_device_ac97;
115extern struct platform_device s5pv210_device_iis0; 98extern struct platform_device s5pv210_device_iis0;
116extern struct platform_device s5pv210_device_iis1; 99extern struct platform_device s5pv210_device_iis1;
diff --git a/arch/arm/plat-samsung/include/plat/fb.h b/arch/arm/plat-samsung/include/plat/fb.h
index 9ae507270785..5a0e26afb961 100644
--- a/arch/arm/plat-samsung/include/plat/fb.h
+++ b/arch/arm/plat-samsung/include/plat/fb.h
@@ -41,13 +41,6 @@ extern void s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd);
41extern void s3c64xx_fb_gpio_setup_24bpp(void); 41extern void s3c64xx_fb_gpio_setup_24bpp(void);
42 42
43/** 43/**
44 * s5pc100_fb_gpio_setup_24bpp() - S5PC100 setup function for 24bpp LCD
45 *
46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
47 */
48extern void s5pc100_fb_gpio_setup_24bpp(void);
49
50/**
51 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD 44 * s5pv210_fb_gpio_setup_24bpp() - S5PV210/S5PC110 setup function for 24bpp LCD
52 * 45 *
53 * Initialise the GPIO for an 24bpp LCD display on the RGB interface. 46 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
@@ -61,11 +54,4 @@ extern void s5pv210_fb_gpio_setup_24bpp(void);
61 */ 54 */
62extern void exynos4_fimd0_gpio_setup_24bpp(void); 55extern void exynos4_fimd0_gpio_setup_24bpp(void);
63 56
64/**
65 * s5p64x0_fb_gpio_setup_24bpp() - S5P6440/S5P6450 setup function for 24bpp LCD
66 *
67 * Initialise the GPIO for an 24bpp LCD display on the RGB interface.
68 */
69extern void s5p64x0_fb_gpio_setup_24bpp(void);
70
71#endif /* __PLAT_S3C_FB_H */ 57#endif /* __PLAT_S3C_FB_H */
diff --git a/arch/arm/plat-samsung/include/plat/s5p-clock.h b/arch/arm/plat-samsung/include/plat/s5p-clock.h
index 8364b4bea8b8..acacc4b88a39 100644
--- a/arch/arm/plat-samsung/include/plat/s5p-clock.h
+++ b/arch/arm/plat-samsung/include/plat/s5p-clock.h
@@ -57,7 +57,7 @@ extern int s5p_gatectrl(void __iomem *reg, struct clk *clk, int enable);
57extern int s5p_epll_enable(struct clk *clk, int enable); 57extern int s5p_epll_enable(struct clk *clk, int enable);
58extern unsigned long s5p_epll_get_rate(struct clk *clk); 58extern unsigned long s5p_epll_get_rate(struct clk *clk);
59 59
60/* SPDIF clk operations common for S5PC100/V210/C110 and Exynos4 */ 60/* SPDIF clk operations common for S5PV210/C110 and Exynos4 */
61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate); 61extern int s5p_spdif_set_rate(struct clk *clk, unsigned long rate);
62extern unsigned long s5p_spdif_get_rate(struct clk *clk); 62extern unsigned long s5p_spdif_get_rate(struct clk *clk);
63 63
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index bf650218b40e..f84b6cbc8745 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -56,9 +56,6 @@ extern void s3c2416_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
56extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 56extern void s3c2416_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 57extern void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 58extern void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
59extern void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
60extern void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
61extern void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
62extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 59extern void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
63extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w); 60extern void s5pv210_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
64extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 61extern void s5pv210_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
@@ -68,10 +65,6 @@ extern void exynos4_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
68extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w); 65extern void exynos4_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
69extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w); 66extern void exynos4_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
70extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w); 67extern void exynos4_setup_sdhci3_cfg_gpio(struct platform_device *, int w);
71extern void s5p64x0_setup_sdhci0_cfg_gpio(struct platform_device *, int w);
72extern void s5p64x0_setup_sdhci1_cfg_gpio(struct platform_device *, int w);
73extern void s5p6440_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
74extern void s5p6450_setup_sdhci2_cfg_gpio(struct platform_device *, int w);
75 68
76/* S3C2416 SDHCI setup */ 69/* S3C2416 SDHCI setup */
77 70
@@ -151,76 +144,6 @@ static inline void s3c6400_default_sdhci2(void) { }
151 144
152#endif /* CONFIG_S3C64XX_SETUP_SDHCI */ 145#endif /* CONFIG_S3C64XX_SETUP_SDHCI */
153 146
154/* S5P64X0 SDHCI setup */
155
156#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
157static inline void s5p64x0_default_sdhci0(void)
158{
159#ifdef CONFIG_S3C_DEV_HSMMC
160 s3c_hsmmc0_def_platdata.cfg_gpio = s5p64x0_setup_sdhci0_cfg_gpio;
161#endif
162}
163
164static inline void s5p64x0_default_sdhci1(void)
165{
166#ifdef CONFIG_S3C_DEV_HSMMC1
167 s3c_hsmmc1_def_platdata.cfg_gpio = s5p64x0_setup_sdhci1_cfg_gpio;
168#endif
169}
170
171static inline void s5p6440_default_sdhci2(void)
172{
173#ifdef CONFIG_S3C_DEV_HSMMC2
174 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6440_setup_sdhci2_cfg_gpio;
175#endif
176}
177
178static inline void s5p6450_default_sdhci2(void)
179{
180#ifdef CONFIG_S3C_DEV_HSMMC2
181 s3c_hsmmc2_def_platdata.cfg_gpio = s5p6450_setup_sdhci2_cfg_gpio;
182#endif
183}
184
185#else
186static inline void s5p64x0_default_sdhci0(void) { }
187static inline void s5p64x0_default_sdhci1(void) { }
188static inline void s5p6440_default_sdhci2(void) { }
189static inline void s5p6450_default_sdhci2(void) { }
190
191#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
192
193/* S5PC100 SDHCI setup */
194
195#ifdef CONFIG_S5PC100_SETUP_SDHCI
196static inline void s5pc100_default_sdhci0(void)
197{
198#ifdef CONFIG_S3C_DEV_HSMMC
199 s3c_hsmmc0_def_platdata.cfg_gpio = s5pc100_setup_sdhci0_cfg_gpio;
200#endif
201}
202
203static inline void s5pc100_default_sdhci1(void)
204{
205#ifdef CONFIG_S3C_DEV_HSMMC1
206 s3c_hsmmc1_def_platdata.cfg_gpio = s5pc100_setup_sdhci1_cfg_gpio;
207#endif
208}
209
210static inline void s5pc100_default_sdhci2(void)
211{
212#ifdef CONFIG_S3C_DEV_HSMMC2
213 s3c_hsmmc2_def_platdata.cfg_gpio = s5pc100_setup_sdhci2_cfg_gpio;
214#endif
215}
216
217#else
218static inline void s5pc100_default_sdhci0(void) { }
219static inline void s5pc100_default_sdhci1(void) { }
220static inline void s5pc100_default_sdhci2(void) { }
221
222#endif /* CONFIG_S5PC100_SETUP_SDHCI */
223
224/* S5PV210 SDHCI setup */ 147/* S5PV210 SDHCI setup */
225 148
226#ifdef CONFIG_S5PV210_SETUP_SDHCI 149#ifdef CONFIG_S5PV210_SETUP_SDHCI
diff --git a/drivers/gpio/gpio-samsung.c b/drivers/gpio/gpio-samsung.c
index 07105ee5c9ae..7d4281e0d901 100644
--- a/drivers/gpio/gpio-samsung.c
+++ b/drivers/gpio/gpio-samsung.c
@@ -358,47 +358,6 @@ static unsigned s3c24xx_gpio_getcfg_abank(struct samsung_gpio_chip *chip,
358} 358}
359#endif 359#endif
360 360
361#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
362static int s5p64x0_gpio_setcfg_rbank(struct samsung_gpio_chip *chip,
363 unsigned int off, unsigned int cfg)
364{
365 void __iomem *reg = chip->base;
366 unsigned int shift;
367 u32 con;
368
369 switch (off) {
370 case 0:
371 case 1:
372 case 2:
373 case 3:
374 case 4:
375 case 5:
376 shift = (off & 7) * 4;
377 reg -= 4;
378 break;
379 case 6:
380 shift = ((off + 1) & 7) * 4;
381 reg -= 4;
382 break;
383 default:
384 shift = ((off + 1) & 7) * 4;
385 break;
386 }
387
388 if (samsung_gpio_is_cfg_special(cfg)) {
389 cfg &= 0xf;
390 cfg <<= shift;
391 }
392
393 con = __raw_readl(reg);
394 con &= ~(0xf << shift);
395 con |= cfg;
396 __raw_writel(con, reg);
397
398 return 0;
399}
400#endif
401
402static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg, 361static void __init samsung_gpiolib_set_cfg(struct samsung_gpio_cfg *chipcfg,
403 int nr_chips) 362 int nr_chips)
404{ 363{
@@ -426,16 +385,6 @@ static struct samsung_gpio_cfg s3c24xx_gpiocfg_banka = {
426}; 385};
427#endif 386#endif
428 387
429#if defined(CONFIG_CPU_S5P6440) || defined(CONFIG_CPU_S5P6450)
430static struct samsung_gpio_cfg s5p64x0_gpio_cfg_rbank = {
431 .cfg_eint = 0x3,
432 .set_config = s5p64x0_gpio_setcfg_rbank,
433 .get_config = samsung_gpio_getcfg_4bit,
434 .set_pull = samsung_gpio_setpull_updown,
435 .get_pull = samsung_gpio_getpull_updown,
436};
437#endif
438
439static struct samsung_gpio_cfg samsung_gpio_cfgs[] = { 388static struct samsung_gpio_cfg samsung_gpio_cfgs[] = {
440 [0] = { 389 [0] = {
441 .cfg_eint = 0x0, 390 .cfg_eint = 0x0,
@@ -708,91 +657,6 @@ static int s3c24xx_gpiolib_banka_output(struct gpio_chip *chip,
708} 657}
709#endif 658#endif
710 659
711/* The next set of routines are for the case of s5p64x0 bank r */
712
713static int s5p64x0_gpiolib_rbank_input(struct gpio_chip *chip,
714 unsigned int offset)
715{
716 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
717 void __iomem *base = ourchip->base;
718 void __iomem *regcon = base;
719 unsigned long con;
720 unsigned long flags;
721
722 switch (offset) {
723 case 6:
724 offset += 1;
725 case 0:
726 case 1:
727 case 2:
728 case 3:
729 case 4:
730 case 5:
731 regcon -= 4;
732 break;
733 default:
734 offset -= 7;
735 break;
736 }
737
738 samsung_gpio_lock(ourchip, flags);
739
740 con = __raw_readl(regcon);
741 con &= ~(0xf << con_4bit_shift(offset));
742 __raw_writel(con, regcon);
743
744 samsung_gpio_unlock(ourchip, flags);
745
746 return 0;
747}
748
749static int s5p64x0_gpiolib_rbank_output(struct gpio_chip *chip,
750 unsigned int offset, int value)
751{
752 struct samsung_gpio_chip *ourchip = to_samsung_gpio(chip);
753 void __iomem *base = ourchip->base;
754 void __iomem *regcon = base;
755 unsigned long con;
756 unsigned long dat;
757 unsigned long flags;
758 unsigned con_offset = offset;
759
760 switch (con_offset) {
761 case 6:
762 con_offset += 1;
763 case 0:
764 case 1:
765 case 2:
766 case 3:
767 case 4:
768 case 5:
769 regcon -= 4;
770 break;
771 default:
772 con_offset -= 7;
773 break;
774 }
775
776 samsung_gpio_lock(ourchip, flags);
777
778 con = __raw_readl(regcon);
779 con &= ~(0xf << con_4bit_shift(con_offset));
780 con |= 0x1 << con_4bit_shift(con_offset);
781
782 dat = __raw_readl(base + GPIODAT_OFF);
783 if (value)
784 dat |= 1 << offset;
785 else
786 dat &= ~(1 << offset);
787
788 __raw_writel(con, regcon);
789 __raw_writel(dat, base + GPIODAT_OFF);
790
791 samsung_gpio_unlock(ourchip, flags);
792
793 return 0;
794}
795
796static void samsung_gpiolib_set(struct gpio_chip *chip, 660static void samsung_gpiolib_set(struct gpio_chip *chip,
797 unsigned offset, int value) 661 unsigned offset, int value)
798{ 662{
@@ -999,20 +863,6 @@ static void __init samsung_gpiolib_add_4bit2_chips(struct samsung_gpio_chip *chi
999 } 863 }
1000} 864}
1001 865
1002static void __init s5p64x0_gpiolib_add_rbank(struct samsung_gpio_chip *chip,
1003 int nr_chips)
1004{
1005 for (; nr_chips > 0; nr_chips--, chip++) {
1006 chip->chip.direction_input = s5p64x0_gpiolib_rbank_input;
1007 chip->chip.direction_output = s5p64x0_gpiolib_rbank_output;
1008
1009 if (!chip->pm)
1010 chip->pm = __gpio_pm(&samsung_gpio_pm_4bit);
1011
1012 samsung_gpiolib_add(chip);
1013 }
1014}
1015
1016int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) 866int samsung_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
1017{ 867{
1018 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip); 868 struct samsung_gpio_chip *samsung_chip = container_of(chip, struct samsung_gpio_chip, chip);
@@ -1320,545 +1170,6 @@ static struct samsung_gpio_chip s3c64xx_gpios_2bit[] = {
1320}; 1170};
1321 1171
1322/* 1172/*
1323 * S5P6440 GPIO bank summary:
1324 *
1325 * Bank GPIOs Style SlpCon ExtInt Group
1326 * A 6 4Bit Yes 1
1327 * B 7 4Bit Yes 1
1328 * C 8 4Bit Yes 2
1329 * F 2 2Bit Yes 4 [1]
1330 * G 7 4Bit Yes 5
1331 * H 10 4Bit[2] Yes 6
1332 * I 16 2Bit Yes None
1333 * J 12 2Bit Yes None
1334 * N 16 2Bit No IRQ_EINT
1335 * P 8 2Bit Yes 8
1336 * R 15 4Bit[2] Yes 8
1337 */
1338
1339static struct samsung_gpio_chip s5p6440_gpios_4bit[] = {
1340#ifdef CONFIG_CPU_S5P6440
1341 {
1342 .chip = {
1343 .base = S5P6440_GPA(0),
1344 .ngpio = S5P6440_GPIO_A_NR,
1345 .label = "GPA",
1346 },
1347 }, {
1348 .chip = {
1349 .base = S5P6440_GPB(0),
1350 .ngpio = S5P6440_GPIO_B_NR,
1351 .label = "GPB",
1352 },
1353 }, {
1354 .chip = {
1355 .base = S5P6440_GPC(0),
1356 .ngpio = S5P6440_GPIO_C_NR,
1357 .label = "GPC",
1358 },
1359 }, {
1360 .base = S5P64X0_GPG_BASE,
1361 .chip = {
1362 .base = S5P6440_GPG(0),
1363 .ngpio = S5P6440_GPIO_G_NR,
1364 .label = "GPG",
1365 },
1366 },
1367#endif
1368};
1369
1370static struct samsung_gpio_chip s5p6440_gpios_4bit2[] = {
1371#ifdef CONFIG_CPU_S5P6440
1372 {
1373 .base = S5P64X0_GPH_BASE + 0x4,
1374 .chip = {
1375 .base = S5P6440_GPH(0),
1376 .ngpio = S5P6440_GPIO_H_NR,
1377 .label = "GPH",
1378 },
1379 },
1380#endif
1381};
1382
1383static struct samsung_gpio_chip s5p6440_gpios_rbank[] = {
1384#ifdef CONFIG_CPU_S5P6440
1385 {
1386 .base = S5P64X0_GPR_BASE + 0x4,
1387 .config = &s5p64x0_gpio_cfg_rbank,
1388 .chip = {
1389 .base = S5P6440_GPR(0),
1390 .ngpio = S5P6440_GPIO_R_NR,
1391 .label = "GPR",
1392 },
1393 },
1394#endif
1395};
1396
1397static struct samsung_gpio_chip s5p6440_gpios_2bit[] = {
1398#ifdef CONFIG_CPU_S5P6440
1399 {
1400 .base = S5P64X0_GPF_BASE,
1401 .config = &samsung_gpio_cfgs[6],
1402 .chip = {
1403 .base = S5P6440_GPF(0),
1404 .ngpio = S5P6440_GPIO_F_NR,
1405 .label = "GPF",
1406 },
1407 }, {
1408 .base = S5P64X0_GPI_BASE,
1409 .config = &samsung_gpio_cfgs[4],
1410 .chip = {
1411 .base = S5P6440_GPI(0),
1412 .ngpio = S5P6440_GPIO_I_NR,
1413 .label = "GPI",
1414 },
1415 }, {
1416 .base = S5P64X0_GPJ_BASE,
1417 .config = &samsung_gpio_cfgs[4],
1418 .chip = {
1419 .base = S5P6440_GPJ(0),
1420 .ngpio = S5P6440_GPIO_J_NR,
1421 .label = "GPJ",
1422 },
1423 }, {
1424 .base = S5P64X0_GPN_BASE,
1425 .config = &samsung_gpio_cfgs[5],
1426 .chip = {
1427 .base = S5P6440_GPN(0),
1428 .ngpio = S5P6440_GPIO_N_NR,
1429 .label = "GPN",
1430 },
1431 }, {
1432 .base = S5P64X0_GPP_BASE,
1433 .config = &samsung_gpio_cfgs[6],
1434 .chip = {
1435 .base = S5P6440_GPP(0),
1436 .ngpio = S5P6440_GPIO_P_NR,
1437 .label = "GPP",
1438 },
1439 },
1440#endif
1441};
1442
1443/*
1444 * S5P6450 GPIO bank summary:
1445 *
1446 * Bank GPIOs Style SlpCon ExtInt Group
1447 * A 6 4Bit Yes 1
1448 * B 7 4Bit Yes 1
1449 * C 8 4Bit Yes 2
1450 * D 8 4Bit Yes None
1451 * F 2 2Bit Yes None
1452 * G 14 4Bit[2] Yes 5
1453 * H 10 4Bit[2] Yes 6
1454 * I 16 2Bit Yes None
1455 * J 12 2Bit Yes None
1456 * K 5 4Bit Yes None
1457 * N 16 2Bit No IRQ_EINT
1458 * P 11 2Bit Yes 8
1459 * Q 14 2Bit Yes None
1460 * R 15 4Bit[2] Yes None
1461 * S 8 2Bit Yes None
1462 *
1463 * [1] BANKF pins 14,15 do not form part of the external interrupt sources
1464 * [2] BANK has two control registers, GPxCON0 and GPxCON1
1465 */
1466
1467static struct samsung_gpio_chip s5p6450_gpios_4bit[] = {
1468#ifdef CONFIG_CPU_S5P6450
1469 {
1470 .chip = {
1471 .base = S5P6450_GPA(0),
1472 .ngpio = S5P6450_GPIO_A_NR,
1473 .label = "GPA",
1474 },
1475 }, {
1476 .chip = {
1477 .base = S5P6450_GPB(0),
1478 .ngpio = S5P6450_GPIO_B_NR,
1479 .label = "GPB",
1480 },
1481 }, {
1482 .chip = {
1483 .base = S5P6450_GPC(0),
1484 .ngpio = S5P6450_GPIO_C_NR,
1485 .label = "GPC",
1486 },
1487 }, {
1488 .chip = {
1489 .base = S5P6450_GPD(0),
1490 .ngpio = S5P6450_GPIO_D_NR,
1491 .label = "GPD",
1492 },
1493 }, {
1494 .base = S5P6450_GPK_BASE,
1495 .chip = {
1496 .base = S5P6450_GPK(0),
1497 .ngpio = S5P6450_GPIO_K_NR,
1498 .label = "GPK",
1499 },
1500 },
1501#endif
1502};
1503
1504static struct samsung_gpio_chip s5p6450_gpios_4bit2[] = {
1505#ifdef CONFIG_CPU_S5P6450
1506 {
1507 .base = S5P64X0_GPG_BASE + 0x4,
1508 .chip = {
1509 .base = S5P6450_GPG(0),
1510 .ngpio = S5P6450_GPIO_G_NR,
1511 .label = "GPG",
1512 },
1513 }, {
1514 .base = S5P64X0_GPH_BASE + 0x4,
1515 .chip = {
1516 .base = S5P6450_GPH(0),
1517 .ngpio = S5P6450_GPIO_H_NR,
1518 .label = "GPH",
1519 },
1520 },
1521#endif
1522};
1523
1524static struct samsung_gpio_chip s5p6450_gpios_rbank[] = {
1525#ifdef CONFIG_CPU_S5P6450
1526 {
1527 .base = S5P64X0_GPR_BASE + 0x4,
1528 .config = &s5p64x0_gpio_cfg_rbank,
1529 .chip = {
1530 .base = S5P6450_GPR(0),
1531 .ngpio = S5P6450_GPIO_R_NR,
1532 .label = "GPR",
1533 },
1534 },
1535#endif
1536};
1537
1538static struct samsung_gpio_chip s5p6450_gpios_2bit[] = {
1539#ifdef CONFIG_CPU_S5P6450
1540 {
1541 .base = S5P64X0_GPF_BASE,
1542 .config = &samsung_gpio_cfgs[6],
1543 .chip = {
1544 .base = S5P6450_GPF(0),
1545 .ngpio = S5P6450_GPIO_F_NR,
1546 .label = "GPF",
1547 },
1548 }, {
1549 .base = S5P64X0_GPI_BASE,
1550 .config = &samsung_gpio_cfgs[4],
1551 .chip = {
1552 .base = S5P6450_GPI(0),
1553 .ngpio = S5P6450_GPIO_I_NR,
1554 .label = "GPI",
1555 },
1556 }, {
1557 .base = S5P64X0_GPJ_BASE,
1558 .config = &samsung_gpio_cfgs[4],
1559 .chip = {
1560 .base = S5P6450_GPJ(0),
1561 .ngpio = S5P6450_GPIO_J_NR,
1562 .label = "GPJ",
1563 },
1564 }, {
1565 .base = S5P64X0_GPN_BASE,
1566 .config = &samsung_gpio_cfgs[5],
1567 .chip = {
1568 .base = S5P6450_GPN(0),
1569 .ngpio = S5P6450_GPIO_N_NR,
1570 .label = "GPN",
1571 },
1572 }, {
1573 .base = S5P64X0_GPP_BASE,
1574 .config = &samsung_gpio_cfgs[6],
1575 .chip = {
1576 .base = S5P6450_GPP(0),
1577 .ngpio = S5P6450_GPIO_P_NR,
1578 .label = "GPP",
1579 },
1580 }, {
1581 .base = S5P6450_GPQ_BASE,
1582 .config = &samsung_gpio_cfgs[5],
1583 .chip = {
1584 .base = S5P6450_GPQ(0),
1585 .ngpio = S5P6450_GPIO_Q_NR,
1586 .label = "GPQ",
1587 },
1588 }, {
1589 .base = S5P6450_GPS_BASE,
1590 .config = &samsung_gpio_cfgs[6],
1591 .chip = {
1592 .base = S5P6450_GPS(0),
1593 .ngpio = S5P6450_GPIO_S_NR,
1594 .label = "GPS",
1595 },
1596 },
1597#endif
1598};
1599
1600/*
1601 * S5PC100 GPIO bank summary:
1602 *
1603 * Bank GPIOs Style INT Type
1604 * A0 8 4Bit GPIO_INT0
1605 * A1 5 4Bit GPIO_INT1
1606 * B 8 4Bit GPIO_INT2
1607 * C 5 4Bit GPIO_INT3
1608 * D 7 4Bit GPIO_INT4
1609 * E0 8 4Bit GPIO_INT5
1610 * E1 6 4Bit GPIO_INT6
1611 * F0 8 4Bit GPIO_INT7
1612 * F1 8 4Bit GPIO_INT8
1613 * F2 8 4Bit GPIO_INT9
1614 * F3 4 4Bit GPIO_INT10
1615 * G0 8 4Bit GPIO_INT11
1616 * G1 3 4Bit GPIO_INT12
1617 * G2 7 4Bit GPIO_INT13
1618 * G3 7 4Bit GPIO_INT14
1619 * H0 8 4Bit WKUP_INT
1620 * H1 8 4Bit WKUP_INT
1621 * H2 8 4Bit WKUP_INT
1622 * H3 8 4Bit WKUP_INT
1623 * I 8 4Bit GPIO_INT15
1624 * J0 8 4Bit GPIO_INT16
1625 * J1 5 4Bit GPIO_INT17
1626 * J2 8 4Bit GPIO_INT18
1627 * J3 8 4Bit GPIO_INT19
1628 * J4 4 4Bit GPIO_INT20
1629 * K0 8 4Bit None
1630 * K1 6 4Bit None
1631 * K2 8 4Bit None
1632 * K3 8 4Bit None
1633 * L0 8 4Bit None
1634 * L1 8 4Bit None
1635 * L2 8 4Bit None
1636 * L3 8 4Bit None
1637 */
1638
1639static struct samsung_gpio_chip s5pc100_gpios_4bit[] = {
1640#ifdef CONFIG_CPU_S5PC100
1641 {
1642 .chip = {
1643 .base = S5PC100_GPA0(0),
1644 .ngpio = S5PC100_GPIO_A0_NR,
1645 .label = "GPA0",
1646 },
1647 }, {
1648 .chip = {
1649 .base = S5PC100_GPA1(0),
1650 .ngpio = S5PC100_GPIO_A1_NR,
1651 .label = "GPA1",
1652 },
1653 }, {
1654 .chip = {
1655 .base = S5PC100_GPB(0),
1656 .ngpio = S5PC100_GPIO_B_NR,
1657 .label = "GPB",
1658 },
1659 }, {
1660 .chip = {
1661 .base = S5PC100_GPC(0),
1662 .ngpio = S5PC100_GPIO_C_NR,
1663 .label = "GPC",
1664 },
1665 }, {
1666 .chip = {
1667 .base = S5PC100_GPD(0),
1668 .ngpio = S5PC100_GPIO_D_NR,
1669 .label = "GPD",
1670 },
1671 }, {
1672 .chip = {
1673 .base = S5PC100_GPE0(0),
1674 .ngpio = S5PC100_GPIO_E0_NR,
1675 .label = "GPE0",
1676 },
1677 }, {
1678 .chip = {
1679 .base = S5PC100_GPE1(0),
1680 .ngpio = S5PC100_GPIO_E1_NR,
1681 .label = "GPE1",
1682 },
1683 }, {
1684 .chip = {
1685 .base = S5PC100_GPF0(0),
1686 .ngpio = S5PC100_GPIO_F0_NR,
1687 .label = "GPF0",
1688 },
1689 }, {
1690 .chip = {
1691 .base = S5PC100_GPF1(0),
1692 .ngpio = S5PC100_GPIO_F1_NR,
1693 .label = "GPF1",
1694 },
1695 }, {
1696 .chip = {
1697 .base = S5PC100_GPF2(0),
1698 .ngpio = S5PC100_GPIO_F2_NR,
1699 .label = "GPF2",
1700 },
1701 }, {
1702 .chip = {
1703 .base = S5PC100_GPF3(0),
1704 .ngpio = S5PC100_GPIO_F3_NR,
1705 .label = "GPF3",
1706 },
1707 }, {
1708 .chip = {
1709 .base = S5PC100_GPG0(0),
1710 .ngpio = S5PC100_GPIO_G0_NR,
1711 .label = "GPG0",
1712 },
1713 }, {
1714 .chip = {
1715 .base = S5PC100_GPG1(0),
1716 .ngpio = S5PC100_GPIO_G1_NR,
1717 .label = "GPG1",
1718 },
1719 }, {
1720 .chip = {
1721 .base = S5PC100_GPG2(0),
1722 .ngpio = S5PC100_GPIO_G2_NR,
1723 .label = "GPG2",
1724 },
1725 }, {
1726 .chip = {
1727 .base = S5PC100_GPG3(0),
1728 .ngpio = S5PC100_GPIO_G3_NR,
1729 .label = "GPG3",
1730 },
1731 }, {
1732 .chip = {
1733 .base = S5PC100_GPI(0),
1734 .ngpio = S5PC100_GPIO_I_NR,
1735 .label = "GPI",
1736 },
1737 }, {
1738 .chip = {
1739 .base = S5PC100_GPJ0(0),
1740 .ngpio = S5PC100_GPIO_J0_NR,
1741 .label = "GPJ0",
1742 },
1743 }, {
1744 .chip = {
1745 .base = S5PC100_GPJ1(0),
1746 .ngpio = S5PC100_GPIO_J1_NR,
1747 .label = "GPJ1",
1748 },
1749 }, {
1750 .chip = {
1751 .base = S5PC100_GPJ2(0),
1752 .ngpio = S5PC100_GPIO_J2_NR,
1753 .label = "GPJ2",
1754 },
1755 }, {
1756 .chip = {
1757 .base = S5PC100_GPJ3(0),
1758 .ngpio = S5PC100_GPIO_J3_NR,
1759 .label = "GPJ3",
1760 },
1761 }, {
1762 .chip = {
1763 .base = S5PC100_GPJ4(0),
1764 .ngpio = S5PC100_GPIO_J4_NR,
1765 .label = "GPJ4",
1766 },
1767 }, {
1768 .chip = {
1769 .base = S5PC100_GPK0(0),
1770 .ngpio = S5PC100_GPIO_K0_NR,
1771 .label = "GPK0",
1772 },
1773 }, {
1774 .chip = {
1775 .base = S5PC100_GPK1(0),
1776 .ngpio = S5PC100_GPIO_K1_NR,
1777 .label = "GPK1",
1778 },
1779 }, {
1780 .chip = {
1781 .base = S5PC100_GPK2(0),
1782 .ngpio = S5PC100_GPIO_K2_NR,
1783 .label = "GPK2",
1784 },
1785 }, {
1786 .chip = {
1787 .base = S5PC100_GPK3(0),
1788 .ngpio = S5PC100_GPIO_K3_NR,
1789 .label = "GPK3",
1790 },
1791 }, {
1792 .chip = {
1793 .base = S5PC100_GPL0(0),
1794 .ngpio = S5PC100_GPIO_L0_NR,
1795 .label = "GPL0",
1796 },
1797 }, {
1798 .chip = {
1799 .base = S5PC100_GPL1(0),
1800 .ngpio = S5PC100_GPIO_L1_NR,
1801 .label = "GPL1",
1802 },
1803 }, {
1804 .chip = {
1805 .base = S5PC100_GPL2(0),
1806 .ngpio = S5PC100_GPIO_L2_NR,
1807 .label = "GPL2",
1808 },
1809 }, {
1810 .chip = {
1811 .base = S5PC100_GPL3(0),
1812 .ngpio = S5PC100_GPIO_L3_NR,
1813 .label = "GPL3",
1814 },
1815 }, {
1816 .chip = {
1817 .base = S5PC100_GPL4(0),
1818 .ngpio = S5PC100_GPIO_L4_NR,
1819 .label = "GPL4",
1820 },
1821 }, {
1822 .base = (S5P_VA_GPIO + 0xC00),
1823 .irq_base = IRQ_EINT(0),
1824 .chip = {
1825 .base = S5PC100_GPH0(0),
1826 .ngpio = S5PC100_GPIO_H0_NR,
1827 .label = "GPH0",
1828 .to_irq = samsung_gpiolib_to_irq,
1829 },
1830 }, {
1831 .base = (S5P_VA_GPIO + 0xC20),
1832 .irq_base = IRQ_EINT(8),
1833 .chip = {
1834 .base = S5PC100_GPH1(0),
1835 .ngpio = S5PC100_GPIO_H1_NR,
1836 .label = "GPH1",
1837 .to_irq = samsung_gpiolib_to_irq,
1838 },
1839 }, {
1840 .base = (S5P_VA_GPIO + 0xC40),
1841 .irq_base = IRQ_EINT(16),
1842 .chip = {
1843 .base = S5PC100_GPH2(0),
1844 .ngpio = S5PC100_GPIO_H2_NR,
1845 .label = "GPH2",
1846 .to_irq = samsung_gpiolib_to_irq,
1847 },
1848 }, {
1849 .base = (S5P_VA_GPIO + 0xC60),
1850 .irq_base = IRQ_EINT(24),
1851 .chip = {
1852 .base = S5PC100_GPH3(0),
1853 .ngpio = S5PC100_GPIO_H3_NR,
1854 .label = "GPH3",
1855 .to_irq = samsung_gpiolib_to_irq,
1856 },
1857 },
1858#endif
1859};
1860
1861/*
1862 * Followings are the gpio banks in S5PV210/S5PC110 1173 * Followings are the gpio banks in S5PV210/S5PC110
1863 * 1174 *
1864 * The 'config' member when left to NULL, is initialized to the default 1175 * The 'config' member when left to NULL, is initialized to the default
@@ -2109,39 +1420,6 @@ static __init int samsung_gpiolib_init(void)
2109 S3C64XX_VA_GPIO); 1420 S3C64XX_VA_GPIO);
2110 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2, 1421 samsung_gpiolib_add_4bit2_chips(s3c64xx_gpios_4bit2,
2111 ARRAY_SIZE(s3c64xx_gpios_4bit2)); 1422 ARRAY_SIZE(s3c64xx_gpios_4bit2));
2112 } else if (soc_is_s5p6440()) {
2113 samsung_gpiolib_add_2bit_chips(s5p6440_gpios_2bit,
2114 ARRAY_SIZE(s5p6440_gpios_2bit), NULL, 0x0);
2115 samsung_gpiolib_add_4bit_chips(s5p6440_gpios_4bit,
2116 ARRAY_SIZE(s5p6440_gpios_4bit), S5P_VA_GPIO);
2117 samsung_gpiolib_add_4bit2_chips(s5p6440_gpios_4bit2,
2118 ARRAY_SIZE(s5p6440_gpios_4bit2));
2119 s5p64x0_gpiolib_add_rbank(s5p6440_gpios_rbank,
2120 ARRAY_SIZE(s5p6440_gpios_rbank));
2121 } else if (soc_is_s5p6450()) {
2122 samsung_gpiolib_add_2bit_chips(s5p6450_gpios_2bit,
2123 ARRAY_SIZE(s5p6450_gpios_2bit), NULL, 0x0);
2124 samsung_gpiolib_add_4bit_chips(s5p6450_gpios_4bit,
2125 ARRAY_SIZE(s5p6450_gpios_4bit), S5P_VA_GPIO);
2126 samsung_gpiolib_add_4bit2_chips(s5p6450_gpios_4bit2,
2127 ARRAY_SIZE(s5p6450_gpios_4bit2));
2128 s5p64x0_gpiolib_add_rbank(s5p6450_gpios_rbank,
2129 ARRAY_SIZE(s5p6450_gpios_rbank));
2130 } else if (soc_is_s5pc100()) {
2131 group = 0;
2132 chip = s5pc100_gpios_4bit;
2133 nr_chips = ARRAY_SIZE(s5pc100_gpios_4bit);
2134
2135 for (i = 0; i < nr_chips; i++, chip++) {
2136 if (!chip->config) {
2137 chip->config = &samsung_gpio_cfgs[3];
2138 chip->group = group++;
2139 }
2140 }
2141 samsung_gpiolib_add_4bit_chips(s5pc100_gpios_4bit, nr_chips, S5P_VA_GPIO);
2142#if defined(CONFIG_CPU_S5PC100) && defined(CONFIG_S5P_GPIO_INT)
2143 s5p_register_gpioint_bank(IRQ_GPIOINT, 0, S5P_GPIOINT_GROUP_MAXNR);
2144#endif
2145 } else if (soc_is_s5pv210()) { 1423 } else if (soc_is_s5pv210()) {
2146 group = 0; 1424 group = 0;
2147 chip = s5pv210_gpios_4bit; 1425 chip = s5pv210_gpios_4bit;
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index bbb746e35500..e7028681aa70 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -23,7 +23,6 @@ config ARM_VIC
23config ARM_VIC_NR 23config ARM_VIC_NR
24 int 24 int
25 default 4 if ARCH_S5PV210 25 default 4 if ARCH_S5PV210
26 default 3 if ARCH_S5PC100
27 default 2 26 default 2
28 depends on ARM_VIC 27 depends on ARM_VIC
29 help 28 help
diff --git a/drivers/mtd/onenand/Kconfig b/drivers/mtd/onenand/Kconfig
index ab2607273e80..dcae2f6a2b11 100644
--- a/drivers/mtd/onenand/Kconfig
+++ b/drivers/mtd/onenand/Kconfig
@@ -32,10 +32,10 @@ config MTD_ONENAND_OMAP2
32 32
33config MTD_ONENAND_SAMSUNG 33config MTD_ONENAND_SAMSUNG
34 tristate "OneNAND on Samsung SOC controller support" 34 tristate "OneNAND on Samsung SOC controller support"
35 depends on ARCH_S3C64XX || ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS4 35 depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4
36 help 36 help
37 Support for a OneNAND flash device connected to an Samsung SOC. 37 Support for a OneNAND flash device connected to an Samsung SOC.
38 S3C64XX/S5PC100 use command mapping method. 38 S3C64XX uses command mapping method.
39 S5PC110/S5PC210 use generic OneNAND method. 39 S5PC110/S5PC210 use generic OneNAND method.
40 40
41config MTD_ONENAND_OTP 41config MTD_ONENAND_OTP
diff --git a/drivers/mtd/onenand/samsung.c b/drivers/mtd/onenand/samsung.c
index efb819c3df2f..19cfb97adbc0 100644
--- a/drivers/mtd/onenand/samsung.c
+++ b/drivers/mtd/onenand/samsung.c
@@ -10,7 +10,7 @@
10 * published by the Free Software Foundation. 10 * published by the Free Software Foundation.
11 * 11 *
12 * Implementation: 12 * Implementation:
13 * S3C64XX and S5PC100: emulate the pseudo BufferRAM 13 * S3C64XX: emulate the pseudo BufferRAM
14 * S5PC110: use DMA 14 * S5PC110: use DMA
15 */ 15 */
16 16
@@ -32,7 +32,6 @@
32enum soc_type { 32enum soc_type {
33 TYPE_S3C6400, 33 TYPE_S3C6400,
34 TYPE_S3C6410, 34 TYPE_S3C6410,
35 TYPE_S5PC100,
36 TYPE_S5PC110, 35 TYPE_S5PC110,
37}; 36};
38 37
@@ -59,7 +58,6 @@ enum soc_type {
59#define MAP_11 (0x3) 58#define MAP_11 (0x3)
60 59
61#define S3C64XX_CMD_MAP_SHIFT 24 60#define S3C64XX_CMD_MAP_SHIFT 24
62#define S5PC100_CMD_MAP_SHIFT 26
63 61
64#define S3C6400_FBA_SHIFT 10 62#define S3C6400_FBA_SHIFT 10
65#define S3C6400_FPA_SHIFT 4 63#define S3C6400_FPA_SHIFT 4
@@ -69,10 +67,6 @@ enum soc_type {
69#define S3C6410_FPA_SHIFT 6 67#define S3C6410_FPA_SHIFT 6
70#define S3C6410_FSA_SHIFT 4 68#define S3C6410_FSA_SHIFT 4
71 69
72#define S5PC100_FBA_SHIFT 13
73#define S5PC100_FPA_SHIFT 7
74#define S5PC100_FSA_SHIFT 5
75
76/* S5PC110 specific definitions */ 70/* S5PC110 specific definitions */
77#define S5PC110_DMA_SRC_ADDR 0x400 71#define S5PC110_DMA_SRC_ADDR 0x400
78#define S5PC110_DMA_SRC_CFG 0x404 72#define S5PC110_DMA_SRC_CFG 0x404
@@ -195,11 +189,6 @@ static unsigned int s3c64xx_cmd_map(unsigned type, unsigned val)
195 return (type << S3C64XX_CMD_MAP_SHIFT) | val; 189 return (type << S3C64XX_CMD_MAP_SHIFT) | val;
196} 190}
197 191
198static unsigned int s5pc1xx_cmd_map(unsigned type, unsigned val)
199{
200 return (type << S5PC100_CMD_MAP_SHIFT) | val;
201}
202
203static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa) 192static unsigned int s3c6400_mem_addr(int fba, int fpa, int fsa)
204{ 193{
205 return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) | 194 return (fba << S3C6400_FBA_SHIFT) | (fpa << S3C6400_FPA_SHIFT) |
@@ -212,12 +201,6 @@ static unsigned int s3c6410_mem_addr(int fba, int fpa, int fsa)
212 (fsa << S3C6410_FSA_SHIFT); 201 (fsa << S3C6410_FSA_SHIFT);
213} 202}
214 203
215static unsigned int s5pc100_mem_addr(int fba, int fpa, int fsa)
216{
217 return (fba << S5PC100_FBA_SHIFT) | (fpa << S5PC100_FPA_SHIFT) |
218 (fsa << S5PC100_FSA_SHIFT);
219}
220
221static void s3c_onenand_reset(void) 204static void s3c_onenand_reset(void)
222{ 205{
223 unsigned long timeout = 0x10000; 206 unsigned long timeout = 0x10000;
@@ -835,9 +818,6 @@ static void s3c_onenand_setup(struct mtd_info *mtd)
835 } else if (onenand->type == TYPE_S3C6410) { 818 } else if (onenand->type == TYPE_S3C6410) {
836 onenand->mem_addr = s3c6410_mem_addr; 819 onenand->mem_addr = s3c6410_mem_addr;
837 onenand->cmd_map = s3c64xx_cmd_map; 820 onenand->cmd_map = s3c64xx_cmd_map;
838 } else if (onenand->type == TYPE_S5PC100) {
839 onenand->mem_addr = s5pc100_mem_addr;
840 onenand->cmd_map = s5pc1xx_cmd_map;
841 } else if (onenand->type == TYPE_S5PC110) { 821 } else if (onenand->type == TYPE_S5PC110) {
842 /* Use generic onenand functions */ 822 /* Use generic onenand functions */
843 this->read_bufferram = s5pc110_read_bufferram; 823 this->read_bufferram = s5pc110_read_bufferram;
@@ -1111,9 +1091,6 @@ static struct platform_device_id s3c_onenand_driver_ids[] = {
1111 .name = "s3c6410-onenand", 1091 .name = "s3c6410-onenand",
1112 .driver_data = TYPE_S3C6410, 1092 .driver_data = TYPE_S3C6410,
1113 }, { 1093 }, {
1114 .name = "s5pc100-onenand",
1115 .driver_data = TYPE_S5PC100,
1116 }, {
1117 .name = "s5pc110-onenand", 1094 .name = "s5pc110-onenand",
1118 .driver_data = TYPE_S5PC110, 1095 .driver_data = TYPE_S5PC110,
1119 }, { }, 1096 }, { },
diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 75a56968b14c..a771a3a4d321 100644
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1323,19 +1323,6 @@ static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1323 .tx_st_done = 21, 1323 .tx_st_done = 21,
1324}; 1324};
1325 1325
1326static struct s3c64xx_spi_port_config s5p64x0_spi_port_config = {
1327 .fifo_lvl_mask = { 0x1ff, 0x7F },
1328 .rx_lvl_offset = 15,
1329 .tx_st_done = 25,
1330};
1331
1332static struct s3c64xx_spi_port_config s5pc100_spi_port_config = {
1333 .fifo_lvl_mask = { 0x7f, 0x7F },
1334 .rx_lvl_offset = 13,
1335 .tx_st_done = 21,
1336 .high_speed = true,
1337};
1338
1339static struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1326static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1340 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1327 .fifo_lvl_mask = { 0x1ff, 0x7F },
1341 .rx_lvl_offset = 15, 1328 .rx_lvl_offset = 15,
@@ -1368,12 +1355,6 @@ static struct platform_device_id s3c64xx_spi_driver_ids[] = {
1368 .name = "s3c6410-spi", 1355 .name = "s3c6410-spi",
1369 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1356 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1370 }, { 1357 }, {
1371 .name = "s5p64x0-spi",
1372 .driver_data = (kernel_ulong_t)&s5p64x0_spi_port_config,
1373 }, {
1374 .name = "s5pc100-spi",
1375 .driver_data = (kernel_ulong_t)&s5pc100_spi_port_config,
1376 }, {
1377 .name = "s5pv210-spi", 1358 .name = "s5pv210-spi",
1378 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config, 1359 .driver_data = (kernel_ulong_t)&s5pv210_spi_port_config,
1379 }, { 1360 }, {
@@ -1390,9 +1371,6 @@ static const struct of_device_id s3c64xx_spi_dt_match[] = {
1390 { .compatible = "samsung,s3c6410-spi", 1371 { .compatible = "samsung,s3c6410-spi",
1391 .data = (void *)&s3c6410_spi_port_config, 1372 .data = (void *)&s3c6410_spi_port_config,
1392 }, 1373 },
1393 { .compatible = "samsung,s5pc100-spi",
1394 .data = (void *)&s5pc100_spi_port_config,
1395 },
1396 { .compatible = "samsung,s5pv210-spi", 1374 { .compatible = "samsung,s5pv210-spi",
1397 .data = (void *)&s5pv210_spi_port_config, 1375 .data = (void *)&s5pv210_spi_port_config,
1398 }, 1376 },
diff --git a/drivers/video/fbdev/Kconfig b/drivers/video/fbdev/Kconfig
index 5edc7a054e03..92026d31bb48 100644
--- a/drivers/video/fbdev/Kconfig
+++ b/drivers/video/fbdev/Kconfig
@@ -2025,8 +2025,8 @@ config FB_TMIO_ACCELL
2025 2025
2026config FB_S3C 2026config FB_S3C
2027 tristate "Samsung S3C framebuffer support" 2027 tristate "Samsung S3C framebuffer support"
2028 depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || ARCH_S5P64X0 || \ 2028 depends on FB && (CPU_S3C2416 || ARCH_S3C64XX || \
2029 ARCH_S5PC100 || ARCH_S5PV210 || ARCH_EXYNOS) 2029 ARCH_S5PV210 || ARCH_EXYNOS)
2030 select FB_CFB_FILLRECT 2030 select FB_CFB_FILLRECT
2031 select FB_CFB_COPYAREA 2031 select FB_CFB_COPYAREA
2032 select FB_CFB_IMAGEBLIT 2032 select FB_CFB_IMAGEBLIT
diff --git a/drivers/video/fbdev/s3c-fb.c b/drivers/video/fbdev/s3c-fb.c
index 62acae2694a9..b33abb0a433d 100644
--- a/drivers/video/fbdev/s3c-fb.c
+++ b/drivers/video/fbdev/s3c-fb.c
@@ -1805,38 +1805,6 @@ static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1805 .win[4] = &s3c_fb_data_64xx_wins[4], 1805 .win[4] = &s3c_fb_data_64xx_wins[4],
1806}; 1806};
1807 1807
1808static struct s3c_fb_driverdata s3c_fb_data_s5pc100 = {
1809 .variant = {
1810 .nr_windows = 5,
1811 .vidtcon = VIDTCON0,
1812 .wincon = WINCON(0),
1813 .winmap = WINxMAP(0),
1814 .keycon = WKEYCON,
1815 .osd = VIDOSD_BASE,
1816 .osd_stride = 16,
1817 .buf_start = VIDW_BUF_START(0),
1818 .buf_size = VIDW_BUF_SIZE(0),
1819 .buf_end = VIDW_BUF_END(0),
1820
1821 .palette = {
1822 [0] = 0x2400,
1823 [1] = 0x2800,
1824 [2] = 0x2c00,
1825 [3] = 0x3000,
1826 [4] = 0x3400,
1827 },
1828
1829 .has_prtcon = 1,
1830 .has_blendcon = 1,
1831 .has_clksel = 1,
1832 },
1833 .win[0] = &s3c_fb_data_s5p_wins[0],
1834 .win[1] = &s3c_fb_data_s5p_wins[1],
1835 .win[2] = &s3c_fb_data_s5p_wins[2],
1836 .win[3] = &s3c_fb_data_s5p_wins[3],
1837 .win[4] = &s3c_fb_data_s5p_wins[4],
1838};
1839
1840static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = { 1808static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
1841 .variant = { 1809 .variant = {
1842 .nr_windows = 5, 1810 .nr_windows = 5,
@@ -1970,41 +1938,11 @@ static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1970 }, 1938 },
1971}; 1939};
1972 1940
1973static struct s3c_fb_driverdata s3c_fb_data_s5p64x0 = {
1974 .variant = {
1975 .nr_windows = 3,
1976 .vidtcon = VIDTCON0,
1977 .wincon = WINCON(0),
1978 .winmap = WINxMAP(0),
1979 .keycon = WKEYCON,
1980 .osd = VIDOSD_BASE,
1981 .osd_stride = 16,
1982 .buf_start = VIDW_BUF_START(0),
1983 .buf_size = VIDW_BUF_SIZE(0),
1984 .buf_end = VIDW_BUF_END(0),
1985
1986 .palette = {
1987 [0] = 0x2400,
1988 [1] = 0x2800,
1989 [2] = 0x2c00,
1990 },
1991
1992 .has_blendcon = 1,
1993 .has_fixvclk = 1,
1994 },
1995 .win[0] = &s3c_fb_data_s5p_wins[0],
1996 .win[1] = &s3c_fb_data_s5p_wins[1],
1997 .win[2] = &s3c_fb_data_s5p_wins[2],
1998};
1999
2000static struct platform_device_id s3c_fb_driver_ids[] = { 1941static struct platform_device_id s3c_fb_driver_ids[] = {
2001 { 1942 {
2002 .name = "s3c-fb", 1943 .name = "s3c-fb",
2003 .driver_data = (unsigned long)&s3c_fb_data_64xx, 1944 .driver_data = (unsigned long)&s3c_fb_data_64xx,
2004 }, { 1945 }, {
2005 .name = "s5pc100-fb",
2006 .driver_data = (unsigned long)&s3c_fb_data_s5pc100,
2007 }, {
2008 .name = "s5pv210-fb", 1946 .name = "s5pv210-fb",
2009 .driver_data = (unsigned long)&s3c_fb_data_s5pv210, 1947 .driver_data = (unsigned long)&s3c_fb_data_s5pv210,
2010 }, { 1948 }, {
@@ -2016,9 +1954,6 @@ static struct platform_device_id s3c_fb_driver_ids[] = {
2016 }, { 1954 }, {
2017 .name = "s3c2443-fb", 1955 .name = "s3c2443-fb",
2018 .driver_data = (unsigned long)&s3c_fb_data_s3c2443, 1956 .driver_data = (unsigned long)&s3c_fb_data_s3c2443,
2019 }, {
2020 .name = "s5p64x0-fb",
2021 .driver_data = (unsigned long)&s3c_fb_data_s5p64x0,
2022 }, 1957 },
2023 {}, 1958 {},
2024}; 1959};
diff --git a/include/video/samsung_fimd.h b/include/video/samsung_fimd.h
index b0393209679b..8af0c6155eed 100644
--- a/include/video/samsung_fimd.h
+++ b/include/video/samsung_fimd.h
@@ -107,7 +107,7 @@
107#define VIDCON2_ORGYCbCr (1 << 8) 107#define VIDCON2_ORGYCbCr (1 << 8)
108#define VIDCON2_YUVORDCrCb (1 << 7) 108#define VIDCON2_YUVORDCrCb (1 << 7)
109 109
110/* PRTCON (S3C6410, S5PC100) 110/* PRTCON (S3C6410)
111 * Might not be present in the S3C6410 documentation, 111 * Might not be present in the S3C6410 documentation,
112 * but tests prove it's there almost for sure; shouldn't hurt in any case. 112 * but tests prove it's there almost for sure; shouldn't hurt in any case.
113 */ 113 */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-18 13:02:06 -0400