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authorDave Airlie <airlied@redhat.com>2013-12-17 19:39:56 -0500
committerDave Airlie <airlied@redhat.com>2013-12-17 19:39:56 -0500
commitda32cc90cbc865c6b49bdc2e0d81b2df3972e5ec (patch)
tree9ba03b105518cb5a2d66480f584c55657d9beba3
parent319e2e3f63c348a9b66db4667efa73178e18b17d (diff)
parentbe46ffd48ba34189336c6fe420ff3370dcd36c60 (diff)
Merge tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel into drm-next
- some more ppgtt prep patches from Ben - a few fbc fixes from Ville - power well rework from Imre - vlv forcewake improvements from Deepak S, Ville and Jesse - a few smaller things all over [airlied: fixup forwcewake conflict] * tag 'drm-intel-next-2013-11-29' of git://people.freedesktop.org/~danvet/drm-intel: (97 commits) drm/i915: Fix port name in vlv_wait_port_ready() timeout warning drm/i915: Return a drm_mode_status enum in the mode_valid vfuncs drm/i915: add intel_display_power_enabled_sw() for use in atomic ctx drm/i915: drop DRM_ERROR in intel_fbdev init drm/i915/vlv: use parallel context restore when coming out of RC6 drm/i915/vlv: use a lower RC6 timeout on VLV drm/i915/sdvo: Fix up debug output to not split lines drm/i915: make sparse happy for the new vlv mmio read function drm/i915: drop the right force-wake engine in the vlv mmio funcs drm/i915: Fix GT wake FIFO free entries for VLV drm/i915: Report all GTFIFODBG errors drm/i915: Enabling DebugFS for valleyview forcewake counts drm/i915/vlv: Valleyview support for forcewake Individual power wells. drm/i915: Add power well arguments to force wake routines. drm/i915: Do not attempt to re-enable an unconnected primary plane drm/i915: add a debugfs entry for power domain info drm/i915: add a default always-on power well drm/i915: don't do BDW/HSW specific powerdomains init on other platforms drm/i915: protect HSW power well check with IS_HASWELL in redisable_vga drm/i915: use IS_HASWELL/BROADWELL instead of HAS_POWER_WELL ... Conflicts: drivers/gpu/drm/i915/intel_display.c
Diffstat
-rw-r--r--drivers/char/Makefile2
-rw-r--r--drivers/char/agp/Kconfig5
-rw-r--r--drivers/char/agp/Makefile2
-rw-r--r--drivers/char/agp/intel-agp.c5
-rw-r--r--drivers/char/agp/intel-gtt.c18
-rw-r--r--drivers/gpu/drm/i915/Kconfig32
-rw-r--r--drivers/gpu/drm/i915/dvo_ns2501.c73
-rw-r--r--drivers/gpu/drm/i915/i915_debugfs.c163
-rw-r--r--drivers/gpu/drm/i915/i915_dma.c22
-rw-r--r--drivers/gpu/drm/i915/i915_drv.c42
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h143
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c8
-rw-r--r--drivers/gpu/drm/i915/i915_gem_context.c45
-rw-r--r--drivers/gpu/drm/i915/i915_gem_execbuffer.c11
-rw-r--r--drivers/gpu/drm/i915/i915_gem_gtt.c26
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c17
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h217
-rw-r--r--drivers/gpu/drm/i915/i915_suspend.c45
-rw-r--r--drivers/gpu/drm/i915/i915_sysfs.c35
-rw-r--r--drivers/gpu/drm/i915/i915_ums.c27
-rw-r--r--drivers/gpu/drm/i915/intel_crt.c5
-rw-r--r--drivers/gpu/drm/i915/intel_ddi.c37
-rw-r--r--drivers/gpu/drm/i915/intel_display.c319
-rw-r--r--drivers/gpu/drm/i915/intel_dp.c44
-rw-r--r--drivers/gpu/drm/i915/intel_drv.h25
-rw-r--r--drivers/gpu/drm/i915/intel_dsi.c5
-rw-r--r--drivers/gpu/drm/i915/intel_dvo.c5
-rw-r--r--drivers/gpu/drm/i915/intel_fbdev.c63
-rw-r--r--drivers/gpu/drm/i915/intel_hdmi.c67
-rw-r--r--drivers/gpu/drm/i915/intel_i2c.c15
-rw-r--r--drivers/gpu/drm/i915/intel_lvds.c5
-rw-r--r--drivers/gpu/drm/i915/intel_opregion.c43
-rw-r--r--drivers/gpu/drm/i915/intel_panel.c882
-rw-r--r--drivers/gpu/drm/i915/intel_pm.c396
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c22
-rw-r--r--drivers/gpu/drm/i915/intel_sdvo.c60
-rw-r--r--drivers/gpu/drm/i915/intel_sideband.c29
-rw-r--r--drivers/gpu/drm/i915/intel_sprite.c18
-rw-r--r--drivers/gpu/drm/i915/intel_uncore.c275
-rw-r--r--include/uapi/drm/i915_drm.h19
40 files changed, 2088 insertions, 1184 deletions
diff --git a/drivers/char/Makefile b/drivers/char/Makefile
index 7ff1d0d208a7..2d68054f9795 100644
--- a/drivers/char/Makefile
+++ b/drivers/char/Makefile
@@ -50,7 +50,7 @@ obj-$(CONFIG_GPIO_TB0219) += tb0219.o
50obj-$(CONFIG_TELCLOCK) += tlclk.o 50obj-$(CONFIG_TELCLOCK) += tlclk.o
51 51
52obj-$(CONFIG_MWAVE) += mwave/ 52obj-$(CONFIG_MWAVE) += mwave/
53obj-$(CONFIG_AGP) += agp/ 53obj-y += agp/
54obj-$(CONFIG_PCMCIA) += pcmcia/ 54obj-$(CONFIG_PCMCIA) += pcmcia/
55 55
56obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o 56obj-$(CONFIG_HANGCHECK_TIMER) += hangcheck-timer.o
diff --git a/drivers/char/agp/Kconfig b/drivers/char/agp/Kconfig
index d8b1b576556c..c528f96ee204 100644
--- a/drivers/char/agp/Kconfig
+++ b/drivers/char/agp/Kconfig
@@ -68,6 +68,7 @@ config AGP_AMD64
68config AGP_INTEL 68config AGP_INTEL
69 tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support" 69 tristate "Intel 440LX/BX/GX, I8xx and E7x05 chipset support"
70 depends on AGP && X86 70 depends on AGP && X86
71 select INTEL_GTT
71 help 72 help
72 This option gives you AGP support for the GLX component of X 73 This option gives you AGP support for the GLX component of X
73 on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875, 74 on Intel 440LX/BX/GX, 815, 820, 830, 840, 845, 850, 860, 875,
@@ -155,3 +156,7 @@ config AGP_SGI_TIOCA
155 This option gives you AGP GART support for the SGI TIO chipset 156 This option gives you AGP GART support for the SGI TIO chipset
156 for IA64 processors. 157 for IA64 processors.
157 158
159config INTEL_GTT
160 tristate
161 depends on X86 && PCI
162
diff --git a/drivers/char/agp/Makefile b/drivers/char/agp/Makefile
index 8eb56e273e75..604489bcdbf9 100644
--- a/drivers/char/agp/Makefile
+++ b/drivers/char/agp/Makefile
@@ -13,7 +13,7 @@ obj-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o 13obj-$(CONFIG_AGP_PARISC) += parisc-agp.o
14obj-$(CONFIG_AGP_I460) += i460-agp.o 14obj-$(CONFIG_AGP_I460) += i460-agp.o
15obj-$(CONFIG_AGP_INTEL) += intel-agp.o 15obj-$(CONFIG_AGP_INTEL) += intel-agp.o
16obj-$(CONFIG_AGP_INTEL) += intel-gtt.o 16obj-$(CONFIG_INTEL_GTT) += intel-gtt.o
17obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o 17obj-$(CONFIG_AGP_NVIDIA) += nvidia-agp.o
18obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o 18obj-$(CONFIG_AGP_SGI_TIOCA) += sgi-agp.o
19obj-$(CONFIG_AGP_SIS) += sis-agp.o 19obj-$(CONFIG_AGP_SIS) += sis-agp.o
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index a426ee1f57a6..9ef0a48a5b28 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -14,9 +14,6 @@
14#include "intel-agp.h" 14#include "intel-agp.h"
15#include <drm/intel-gtt.h> 15#include <drm/intel-gtt.h>
16 16
17int intel_agp_enabled;
18EXPORT_SYMBOL(intel_agp_enabled);
19
20static int intel_fetch_size(void) 17static int intel_fetch_size(void)
21{ 18{
22 int i; 19 int i;
@@ -814,8 +811,6 @@ static int agp_intel_probe(struct pci_dev *pdev,
814found_gmch: 811found_gmch:
815 pci_set_drvdata(pdev, bridge); 812 pci_set_drvdata(pdev, bridge);
816 err = agp_add_bridge(bridge); 813 err = agp_add_bridge(bridge);
817 if (!err)
818 intel_agp_enabled = 1;
819 return err; 814 return err;
820} 815}
821 816
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index b8e2014cb9cb..078968d8d07d 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -94,6 +94,7 @@ static struct _intel_private {
94#define IS_IRONLAKE intel_private.driver->is_ironlake 94#define IS_IRONLAKE intel_private.driver->is_ironlake
95#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable 95#define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable
96 96
97#if IS_ENABLED(CONFIG_AGP_INTEL)
97static int intel_gtt_map_memory(struct page **pages, 98static int intel_gtt_map_memory(struct page **pages,
98 unsigned int num_entries, 99 unsigned int num_entries,
99 struct sg_table *st) 100 struct sg_table *st)
@@ -168,6 +169,7 @@ static void i8xx_destroy_pages(struct page *page)
168 __free_pages(page, 2); 169 __free_pages(page, 2);
169 atomic_dec(&agp_bridge->current_memory_agp); 170 atomic_dec(&agp_bridge->current_memory_agp);
170} 171}
172#endif
171 173
172#define I810_GTT_ORDER 4 174#define I810_GTT_ORDER 4
173static int i810_setup(void) 175static int i810_setup(void)
@@ -209,6 +211,7 @@ static void i810_cleanup(void)
209 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); 211 free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER);
210} 212}
211 213
214#if IS_ENABLED(CONFIG_AGP_INTEL)
212static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, 215static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start,
213 int type) 216 int type)
214{ 217{
@@ -289,6 +292,7 @@ static void intel_i810_free_by_type(struct agp_memory *curr)
289 } 292 }
290 kfree(curr); 293 kfree(curr);
291} 294}
295#endif
292 296
293static int intel_gtt_setup_scratch_page(void) 297static int intel_gtt_setup_scratch_page(void)
294{ 298{
@@ -647,7 +651,9 @@ static int intel_gtt_init(void)
647 return -ENOMEM; 651 return -ENOMEM;
648 } 652 }
649 653
654#if IS_ENABLED(CONFIG_AGP_INTEL)
650 global_cache_flush(); /* FIXME: ? */ 655 global_cache_flush(); /* FIXME: ? */
656#endif
651 657
652 intel_private.stolen_size = intel_gtt_stolen_size(); 658 intel_private.stolen_size = intel_gtt_stolen_size();
653 659
@@ -671,6 +677,7 @@ static int intel_gtt_init(void)
671 return 0; 677 return 0;
672} 678}
673 679
680#if IS_ENABLED(CONFIG_AGP_INTEL)
674static int intel_fake_agp_fetch_size(void) 681static int intel_fake_agp_fetch_size(void)
675{ 682{
676 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); 683 int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes);
@@ -689,6 +696,7 @@ static int intel_fake_agp_fetch_size(void)
689 696
690 return 0; 697 return 0;
691} 698}
699#endif
692 700
693static void i830_cleanup(void) 701static void i830_cleanup(void)
694{ 702{
@@ -801,6 +809,7 @@ static int i830_setup(void)
801 return 0; 809 return 0;
802} 810}
803 811
812#if IS_ENABLED(CONFIG_AGP_INTEL)
804static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) 813static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge)
805{ 814{
806 agp_bridge->gatt_table_real = NULL; 815 agp_bridge->gatt_table_real = NULL;
@@ -825,6 +834,7 @@ static int intel_fake_agp_configure(void)
825 834
826 return 0; 835 return 0;
827} 836}
837#endif
828 838
829static bool i830_check_flags(unsigned int flags) 839static bool i830_check_flags(unsigned int flags)
830{ 840{
@@ -863,6 +873,7 @@ void intel_gtt_insert_sg_entries(struct sg_table *st,
863} 873}
864EXPORT_SYMBOL(intel_gtt_insert_sg_entries); 874EXPORT_SYMBOL(intel_gtt_insert_sg_entries);
865 875
876#if IS_ENABLED(CONFIG_AGP_INTEL)
866static void intel_gtt_insert_pages(unsigned int first_entry, 877static void intel_gtt_insert_pages(unsigned int first_entry,
867 unsigned int num_entries, 878 unsigned int num_entries,
868 struct page **pages, 879 struct page **pages,
@@ -928,6 +939,7 @@ out_err:
928 mem->is_flushed = true; 939 mem->is_flushed = true;
929 return ret; 940 return ret;
930} 941}
942#endif
931 943
932void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) 944void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
933{ 945{
@@ -941,6 +953,7 @@ void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries)
941} 953}
942EXPORT_SYMBOL(intel_gtt_clear_range); 954EXPORT_SYMBOL(intel_gtt_clear_range);
943 955
956#if IS_ENABLED(CONFIG_AGP_INTEL)
944static int intel_fake_agp_remove_entries(struct agp_memory *mem, 957static int intel_fake_agp_remove_entries(struct agp_memory *mem,
945 off_t pg_start, int type) 958 off_t pg_start, int type)
946{ 959{
@@ -982,6 +995,7 @@ static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count,
982 /* always return NULL for other allocation types for now */ 995 /* always return NULL for other allocation types for now */
983 return NULL; 996 return NULL;
984} 997}
998#endif
985 999
986static int intel_alloc_chipset_flush_resource(void) 1000static int intel_alloc_chipset_flush_resource(void)
987{ 1001{
@@ -1138,6 +1152,7 @@ static int i9xx_setup(void)
1138 return 0; 1152 return 0;
1139} 1153}
1140 1154
1155#if IS_ENABLED(CONFIG_AGP_INTEL)
1141static const struct agp_bridge_driver intel_fake_agp_driver = { 1156static const struct agp_bridge_driver intel_fake_agp_driver = {
1142 .owner = THIS_MODULE, 1157 .owner = THIS_MODULE,
1143 .size_type = FIXED_APER_SIZE, 1158 .size_type = FIXED_APER_SIZE,
@@ -1159,6 +1174,7 @@ static const struct agp_bridge_driver intel_fake_agp_driver = {
1159 .agp_destroy_page = agp_generic_destroy_page, 1174 .agp_destroy_page = agp_generic_destroy_page,
1160 .agp_destroy_pages = agp_generic_destroy_pages, 1175 .agp_destroy_pages = agp_generic_destroy_pages,
1161}; 1176};
1177#endif
1162 1178
1163static const struct intel_gtt_driver i81x_gtt_driver = { 1179static const struct intel_gtt_driver i81x_gtt_driver = {
1164 .gen = 1, 1180 .gen = 1,
@@ -1376,11 +1392,13 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
1376 1392
1377 intel_private.refcount++; 1393 intel_private.refcount++;
1378 1394
1395#if IS_ENABLED(CONFIG_AGP_INTEL)
1379 if (bridge) { 1396 if (bridge) {
1380 bridge->driver = &intel_fake_agp_driver; 1397 bridge->driver = &intel_fake_agp_driver;
1381 bridge->dev_private_data = &intel_private; 1398 bridge->dev_private_data = &intel_private;
1382 bridge->dev = bridge_pdev; 1399 bridge->dev = bridge_pdev;
1383 } 1400 }
1401#endif
1384 1402
1385 intel_private.bridge_dev = pci_dev_get(bridge_pdev); 1403 intel_private.bridge_dev = pci_dev_get(bridge_pdev);
1386 1404
diff --git a/drivers/gpu/drm/i915/Kconfig b/drivers/gpu/drm/i915/Kconfig
index 6199d0b5b958..73ed59eff139 100644
--- a/drivers/gpu/drm/i915/Kconfig
+++ b/drivers/gpu/drm/i915/Kconfig
@@ -1,8 +1,10 @@
1config DRM_I915 1config DRM_I915
2 tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics" 2 tristate "Intel 8xx/9xx/G3x/G4x/HD Graphics"
3 depends on DRM 3 depends on DRM
4 depends on AGP 4 depends on X86 && PCI
5 depends on AGP_INTEL 5 depends on (AGP || AGP=n)
6 select INTEL_GTT
7 select AGP_INTEL if AGP
6 # we need shmfs for the swappable backing store, and in particular 8 # we need shmfs for the swappable backing store, and in particular
7 # the shmem_readpage() which depends upon tmpfs 9 # the shmem_readpage() which depends upon tmpfs
8 select SHMEM 10 select SHMEM
@@ -35,15 +37,14 @@ config DRM_I915
35config DRM_I915_KMS 37config DRM_I915_KMS
36 bool "Enable modesetting on intel by default" 38 bool "Enable modesetting on intel by default"
37 depends on DRM_I915 39 depends on DRM_I915
40 default y
38 help 41 help
39 Choose this option if you want kernel modesetting enabled by default, 42 Choose this option if you want kernel modesetting enabled by default.
40 and you have a new enough userspace to support this. Running old 43
41 userspaces with this enabled will cause pain. Note that this causes 44 If in doubt, say "Y".
42 the driver to bind to PCI devices, which precludes loading things
43 like intelfb.
44 45
45config DRM_I915_FBDEV 46config DRM_I915_FBDEV
46 bool "Enable legacy fbdev support for the modesettting intel driver" 47 bool "Enable legacy fbdev support for the modesetting intel driver"
47 depends on DRM_I915 48 depends on DRM_I915
48 select DRM_KMS_FB_HELPER 49 select DRM_KMS_FB_HELPER
49 select FB_CFB_FILLRECT 50 select FB_CFB_FILLRECT
@@ -55,9 +56,12 @@ config DRM_I915_FBDEV
55 support. Note that this support also provide the linux console 56 support. Note that this support also provide the linux console
56 support on top of the intel modesetting driver. 57 support on top of the intel modesetting driver.
57 58
59 If in doubt, say "Y".
60
58config DRM_I915_PRELIMINARY_HW_SUPPORT 61config DRM_I915_PRELIMINARY_HW_SUPPORT
59 bool "Enable preliminary support for prerelease Intel hardware by default" 62 bool "Enable preliminary support for prerelease Intel hardware by default"
60 depends on DRM_I915 63 depends on DRM_I915
64 default n
61 help 65 help
62 Choose this option if you have prerelease Intel hardware and want the 66 Choose this option if you have prerelease Intel hardware and want the
63 i915 driver to support it by default. You can enable such support at 67 i915 driver to support it by default. You can enable such support at
@@ -65,3 +69,15 @@ config DRM_I915_PRELIMINARY_HW_SUPPORT
65 option changes the default for that module option. 69 option changes the default for that module option.
66 70
67 If in doubt, say "N". 71 If in doubt, say "N".
72
73config DRM_I915_UMS
74 bool "Enable userspace modesetting on Intel hardware (DEPRECATED)"
75 depends on DRM_I915
76 default n
77 help
78 Choose this option if you still need userspace modesetting.
79
80 Userspace modesetting is deprecated for quite some time now, so
81 enable this only if you have ancient versions of the DDX drivers.
82
83 If in doubt, say "N".
diff --git a/drivers/gpu/drm/i915/dvo_ns2501.c b/drivers/gpu/drm/i915/dvo_ns2501.c
index c4a255be6979..954acb2c7021 100644
--- a/drivers/gpu/drm/i915/dvo_ns2501.c
+++ b/drivers/gpu/drm/i915/dvo_ns2501.c
@@ -87,49 +87,6 @@ struct ns2501_priv {
87 * when switching the resolution. 87 * when switching the resolution.
88 */ 88 */
89 89
90static void enable_dvo(struct intel_dvo_device *dvo)
91{
92 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
93 struct i2c_adapter *adapter = dvo->i2c_bus;
94 struct intel_gmbus *bus = container_of(adapter,
95 struct intel_gmbus,
96 adapter);
97 struct drm_i915_private *dev_priv = bus->dev_priv;
98
99 DRM_DEBUG_KMS("%s: Trying to re-enable the DVO\n", __FUNCTION__);
100
101 ns->dvoc = I915_READ(DVO_C);
102 ns->pll_a = I915_READ(_DPLL_A);
103 ns->srcdim = I915_READ(DVOC_SRCDIM);
104 ns->fw_blc = I915_READ(FW_BLC);
105
106 I915_WRITE(DVOC, 0x10004084);
107 I915_WRITE(_DPLL_A, 0xd0820000);
108 I915_WRITE(DVOC_SRCDIM, 0x400300); // 1024x768
109 I915_WRITE(FW_BLC, 0x1080304);
110
111 I915_WRITE(DVOC, 0x90004084);
112}
113
114/*
115 * Restore the I915 registers modified by the above
116 * trigger function.
117 */
118static void restore_dvo(struct intel_dvo_device *dvo)
119{
120 struct i2c_adapter *adapter = dvo->i2c_bus;
121 struct intel_gmbus *bus = container_of(adapter,
122 struct intel_gmbus,
123 adapter);
124 struct drm_i915_private *dev_priv = bus->dev_priv;
125 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
126
127 I915_WRITE(DVOC, ns->dvoc);
128 I915_WRITE(_DPLL_A, ns->pll_a);
129 I915_WRITE(DVOC_SRCDIM, ns->srcdim);
130 I915_WRITE(FW_BLC, ns->fw_blc);
131}
132
133/* 90/*
134** Read a register from the ns2501. 91** Read a register from the ns2501.
135** Returns true if successful, false otherwise. 92** Returns true if successful, false otherwise.
@@ -300,7 +257,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
300 struct drm_display_mode *adjusted_mode) 257 struct drm_display_mode *adjusted_mode)
301{ 258{
302 bool ok; 259 bool ok;
303 bool restore = false; 260 int retries = 10;
304 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 261 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
305 262
306 DRM_DEBUG_KMS 263 DRM_DEBUG_KMS
@@ -476,20 +433,7 @@ static void ns2501_mode_set(struct intel_dvo_device *dvo,
476 ns->reg_8_shadow |= NS2501_8_BPAS; 433 ns->reg_8_shadow |= NS2501_8_BPAS;
477 } 434 }
478 ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow); 435 ok &= ns2501_writeb(dvo, NS2501_REG8, ns->reg_8_shadow);
479 436 } while (!ok && retries--);
480 if (!ok) {
481 if (restore)
482 restore_dvo(dvo);
483 enable_dvo(dvo);
484 restore = true;
485 }
486 } while (!ok);
487 /*
488 * Restore the old i915 registers before
489 * forcing the ns2501 on.
490 */
491 if (restore)
492 restore_dvo(dvo);
493} 437}
494 438
495/* set the NS2501 power state */ 439/* set the NS2501 power state */
@@ -510,7 +454,7 @@ static bool ns2501_get_hw_state(struct intel_dvo_device *dvo)
510static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable) 454static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
511{ 455{
512 bool ok; 456 bool ok;
513 bool restore = false; 457 int retries = 10;
514 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv); 458 struct ns2501_priv *ns = (struct ns2501_priv *)(dvo->dev_priv);
515 unsigned char ch; 459 unsigned char ch;
516 460
@@ -537,16 +481,7 @@ static void ns2501_dpms(struct intel_dvo_device *dvo, bool enable)
537 ok &= 481 ok &=
538 ns2501_writeb(dvo, 0x35, 482 ns2501_writeb(dvo, 0x35,
539 enable ? 0xff : 0x00); 483 enable ? 0xff : 0x00);
540 if (!ok) { 484 } while (!ok && retries--);
541 if (restore)
542 restore_dvo(dvo);
543 enable_dvo(dvo);
544 restore = true;
545 }
546 } while (!ok);
547
548 if (restore)
549 restore_dvo(dvo);
550 } 485 }
551} 486}
552 487
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6ed45a984230..13accf795548 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -947,7 +947,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
947 if (ret) 947 if (ret)
948 return ret; 948 return ret;
949 949
950 gen6_gt_force_wake_get(dev_priv); 950 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
951 951
952 reqf = I915_READ(GEN6_RPNSWREQ); 952 reqf = I915_READ(GEN6_RPNSWREQ);
953 reqf &= ~GEN6_TURBO_DISABLE; 953 reqf &= ~GEN6_TURBO_DISABLE;
@@ -970,7 +970,7 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
970 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT; 970 cagf = (rpstat & GEN6_CAGF_MASK) >> GEN6_CAGF_SHIFT;
971 cagf *= GT_FREQUENCY_MULTIPLIER; 971 cagf *= GT_FREQUENCY_MULTIPLIER;
972 972
973 gen6_gt_force_wake_put(dev_priv); 973 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
974 mutex_unlock(&dev->struct_mutex); 974 mutex_unlock(&dev->struct_mutex);
975 975
976 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status); 976 seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
@@ -1018,17 +1018,16 @@ static int i915_cur_delayinfo(struct seq_file *m, void *unused)
1018 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts); 1018 seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
1019 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq); 1019 seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
1020 1020
1021 val = vlv_punit_read(dev_priv, PUNIT_FUSE_BUS1); 1021 val = valleyview_rps_max_freq(dev_priv);
1022 seq_printf(m, "max GPU freq: %d MHz\n", 1022 seq_printf(m, "max GPU freq: %d MHz\n",
1023 vlv_gpu_freq(dev_priv->mem_freq, val)); 1023 vlv_gpu_freq(dev_priv, val));
1024 1024
1025 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM); 1025 val = valleyview_rps_min_freq(dev_priv);
1026 seq_printf(m, "min GPU freq: %d MHz\n", 1026 seq_printf(m, "min GPU freq: %d MHz\n",
1027 vlv_gpu_freq(dev_priv->mem_freq, val)); 1027 vlv_gpu_freq(dev_priv, val));
1028 1028
1029 seq_printf(m, "current GPU freq: %d MHz\n", 1029 seq_printf(m, "current GPU freq: %d MHz\n",
1030 vlv_gpu_freq(dev_priv->mem_freq, 1030 vlv_gpu_freq(dev_priv, (freq_sts >> 8) & 0xff));
1031 (freq_sts >> 8) & 0xff));
1032 mutex_unlock(&dev_priv->rps.hw_lock); 1031 mutex_unlock(&dev_priv->rps.hw_lock);
1033 } else { 1032 } else {
1034 seq_puts(m, "no P-state info available\n"); 1033 seq_puts(m, "no P-state info available\n");
@@ -1565,13 +1564,21 @@ static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
1565 struct drm_info_node *node = (struct drm_info_node *) m->private; 1564 struct drm_info_node *node = (struct drm_info_node *) m->private;
1566 struct drm_device *dev = node->minor->dev; 1565 struct drm_device *dev = node->minor->dev;
1567 struct drm_i915_private *dev_priv = dev->dev_private; 1566 struct drm_i915_private *dev_priv = dev->dev_private;
1568 unsigned forcewake_count; 1567 unsigned forcewake_count = 0, fw_rendercount = 0, fw_mediacount = 0;
1569 1568
1570 spin_lock_irq(&dev_priv->uncore.lock); 1569 spin_lock_irq(&dev_priv->uncore.lock);
1571 forcewake_count = dev_priv->uncore.forcewake_count; 1570 if (IS_VALLEYVIEW(dev)) {
1571 fw_rendercount = dev_priv->uncore.fw_rendercount;
1572 fw_mediacount = dev_priv->uncore.fw_mediacount;
1573 } else
1574 forcewake_count = dev_priv->uncore.forcewake_count;
1572 spin_unlock_irq(&dev_priv->uncore.lock); 1575 spin_unlock_irq(&dev_priv->uncore.lock);
1573 1576
1574 seq_printf(m, "forcewake count = %u\n", forcewake_count); 1577 if (IS_VALLEYVIEW(dev)) {
1578 seq_printf(m, "fw_rendercount = %u\n", fw_rendercount);
1579 seq_printf(m, "fw_mediacount = %u\n", fw_mediacount);
1580 } else
1581 seq_printf(m, "forcewake count = %u\n", forcewake_count);
1575 1582
1576 return 0; 1583 return 0;
1577} 1584}
@@ -1735,28 +1742,28 @@ static int i915_dpio_info(struct seq_file *m, void *data)
1735 1742
1736 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL)); 1743 seq_printf(m, "DPIO_CTL: 0x%08x\n", I915_READ(DPIO_CTL));
1737 1744
1738 seq_printf(m, "DPIO_DIV_A: 0x%08x\n", 1745 seq_printf(m, "DPIO PLL DW3 CH0 : 0x%08x\n",
1739 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_A)); 1746 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(0)));
1740 seq_printf(m, "DPIO_DIV_B: 0x%08x\n", 1747 seq_printf(m, "DPIO PLL DW3 CH1: 0x%08x\n",
1741 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_DIV_B)); 1748 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW3(1)));
1742 1749
1743 seq_printf(m, "DPIO_REFSFR_A: 0x%08x\n", 1750 seq_printf(m, "DPIO PLL DW5 CH0: 0x%08x\n",
1744 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_A)); 1751 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(0)));
1745 seq_printf(m, "DPIO_REFSFR_B: 0x%08x\n", 1752 seq_printf(m, "DPIO PLL DW5 CH1: 0x%08x\n",
1746 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_REFSFR_B)); 1753 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW5(1)));
1747 1754
1748 seq_printf(m, "DPIO_CORE_CLK_A: 0x%08x\n", 1755 seq_printf(m, "DPIO PLL DW7 CH0: 0x%08x\n",
1749 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_A)); 1756 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(0)));
1750 seq_printf(m, "DPIO_CORE_CLK_B: 0x%08x\n", 1757 seq_printf(m, "DPIO PLL DW7 CH1: 0x%08x\n",
1751 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_CORE_CLK_B)); 1758 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW7(1)));
1752 1759
1753 seq_printf(m, "DPIO_LPF_COEFF_A: 0x%08x\n", 1760 seq_printf(m, "DPIO PLL DW10 CH0: 0x%08x\n",
1754 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_A)); 1761 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(0)));
1755 seq_printf(m, "DPIO_LPF_COEFF_B: 0x%08x\n", 1762 seq_printf(m, "DPIO PLL DW10 CH1: 0x%08x\n",
1756 vlv_dpio_read(dev_priv, PIPE_A, _DPIO_LPF_COEFF_B)); 1763 vlv_dpio_read(dev_priv, PIPE_A, VLV_PLL_DW10(1)));
1757 1764
1758 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n", 1765 seq_printf(m, "DPIO_FASTCLK_DISABLE: 0x%08x\n",
1759 vlv_dpio_read(dev_priv, PIPE_A, DPIO_FASTCLK_DISABLE)); 1766 vlv_dpio_read(dev_priv, PIPE_A, VLV_CMN_DW0));
1760 1767
1761 mutex_unlock(&dev_priv->dpio_lock); 1768 mutex_unlock(&dev_priv->dpio_lock);
1762 1769
@@ -1845,6 +1852,76 @@ static int i915_pc8_status(struct seq_file *m, void *unused)
1845 return 0; 1852 return 0;
1846} 1853}
1847 1854
1855static const char *power_domain_str(enum intel_display_power_domain domain)
1856{
1857 switch (domain) {
1858 case POWER_DOMAIN_PIPE_A:
1859 return "PIPE_A";
1860 case POWER_DOMAIN_PIPE_B:
1861 return "PIPE_B";
1862 case POWER_DOMAIN_PIPE_C:
1863 return "PIPE_C";
1864 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
1865 return "PIPE_A_PANEL_FITTER";
1866 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
1867 return "PIPE_B_PANEL_FITTER";
1868 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
1869 return "PIPE_C_PANEL_FITTER";
1870 case POWER_DOMAIN_TRANSCODER_A:
1871 return "TRANSCODER_A";
1872 case POWER_DOMAIN_TRANSCODER_B:
1873 return "TRANSCODER_B";
1874 case POWER_DOMAIN_TRANSCODER_C:
1875 return "TRANSCODER_C";
1876 case POWER_DOMAIN_TRANSCODER_EDP:
1877 return "TRANSCODER_EDP";
1878 case POWER_DOMAIN_VGA:
1879 return "VGA";
1880 case POWER_DOMAIN_AUDIO:
1881 return "AUDIO";
1882 case POWER_DOMAIN_INIT:
1883 return "INIT";
1884 default:
1885 WARN_ON(1);
1886 return "?";
1887 }
1888}
1889
1890static int i915_power_domain_info(struct seq_file *m, void *unused)
1891{
1892 struct drm_info_node *node = (struct drm_info_node *) m->private;
1893 struct drm_device *dev = node->minor->dev;
1894 struct drm_i915_private *dev_priv = dev->dev_private;
1895 struct i915_power_domains *power_domains = &dev_priv->power_domains;
1896 int i;
1897
1898 mutex_lock(&power_domains->lock);
1899
1900 seq_printf(m, "%-25s %s\n", "Power well/domain", "Use count");
1901 for (i = 0; i < power_domains->power_well_count; i++) {
1902 struct i915_power_well *power_well;
1903 enum intel_display_power_domain power_domain;
1904
1905 power_well = &power_domains->power_wells[i];
1906 seq_printf(m, "%-25s %d\n", power_well->name,
1907 power_well->count);
1908
1909 for (power_domain = 0; power_domain < POWER_DOMAIN_NUM;
1910 power_domain++) {
1911 if (!(BIT(power_domain) & power_well->domains))
1912 continue;
1913
1914 seq_printf(m, " %-23s %d\n",
1915 power_domain_str(power_domain),
1916 power_domains->domain_use_count[power_domain]);
1917 }
1918 }
1919
1920 mutex_unlock(&power_domains->lock);
1921
1922 return 0;
1923}
1924
1848struct pipe_crc_info { 1925struct pipe_crc_info {
1849 const char *name; 1926 const char *name;
1850 struct drm_device *dev; 1927 struct drm_device *dev;
@@ -1857,6 +1934,9 @@ static int i915_pipe_crc_open(struct inode *inode, struct file *filep)
1857 struct drm_i915_private *dev_priv = info->dev->dev_private; 1934 struct drm_i915_private *dev_priv = info->dev->dev_private;
1858 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; 1935 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe];
1859 1936
1937 if (info->pipe >= INTEL_INFO(info->dev)->num_pipes)
1938 return -ENODEV;
1939
1860 spin_lock_irq(&pipe_crc->lock); 1940 spin_lock_irq(&pipe_crc->lock);
1861 1941
1862 if (pipe_crc->opened) { 1942 if (pipe_crc->opened) {
@@ -2347,7 +2427,7 @@ static int pipe_crc_set_source(struct drm_device *dev, enum pipe pipe,
2347{ 2427{
2348 struct drm_i915_private *dev_priv = dev->dev_private; 2428 struct drm_i915_private *dev_priv = dev->dev_private;
2349 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; 2429 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
2350 u32 val; 2430 u32 val = 0; /* shut up gcc */
2351 int ret; 2431 int ret;
2352 2432
2353 if (pipe_crc->source == source) 2433 if (pipe_crc->source == source)
@@ -2742,7 +2822,7 @@ i915_drop_caches_set(void *data, u64 val)
2742 struct i915_vma *vma, *x; 2822 struct i915_vma *vma, *x;
2743 int ret; 2823 int ret;
2744 2824
2745 DRM_DEBUG_DRIVER("Dropping caches: 0x%08llx\n", val); 2825 DRM_DEBUG("Dropping caches: 0x%08llx\n", val);
2746 2826
2747 /* No need to check and wait for gpu resets, only libdrm auto-restarts 2827 /* No need to check and wait for gpu resets, only libdrm auto-restarts
2748 * on ioctls on -EAGAIN. */ 2828 * on ioctls on -EAGAIN. */
@@ -2810,8 +2890,7 @@ i915_max_freq_get(void *data, u64 *val)
2810 return ret; 2890 return ret;
2811 2891
2812 if (IS_VALLEYVIEW(dev)) 2892 if (IS_VALLEYVIEW(dev))
2813 *val = vlv_gpu_freq(dev_priv->mem_freq, 2893 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
2814 dev_priv->rps.max_delay);
2815 else 2894 else
2816 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; 2895 *val = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
2817 mutex_unlock(&dev_priv->rps.hw_lock); 2896 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -2841,9 +2920,9 @@ i915_max_freq_set(void *data, u64 val)
2841 * Turbo will still be enabled, but won't go above the set value. 2920 * Turbo will still be enabled, but won't go above the set value.
2842 */ 2921 */
2843 if (IS_VALLEYVIEW(dev)) { 2922 if (IS_VALLEYVIEW(dev)) {
2844 val = vlv_freq_opcode(dev_priv->mem_freq, val); 2923 val = vlv_freq_opcode(dev_priv, val);
2845 dev_priv->rps.max_delay = val; 2924 dev_priv->rps.max_delay = val;
2846 gen6_set_rps(dev, val); 2925 valleyview_set_rps(dev, val);
2847 } else { 2926 } else {
2848 do_div(val, GT_FREQUENCY_MULTIPLIER); 2927 do_div(val, GT_FREQUENCY_MULTIPLIER);
2849 dev_priv->rps.max_delay = val; 2928 dev_priv->rps.max_delay = val;
@@ -2876,8 +2955,7 @@ i915_min_freq_get(void *data, u64 *val)
2876 return ret; 2955 return ret;
2877 2956
2878 if (IS_VALLEYVIEW(dev)) 2957 if (IS_VALLEYVIEW(dev))
2879 *val = vlv_gpu_freq(dev_priv->mem_freq, 2958 *val = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
2880 dev_priv->rps.min_delay);
2881 else 2959 else
2882 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; 2960 *val = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
2883 mutex_unlock(&dev_priv->rps.hw_lock); 2961 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -2907,7 +2985,7 @@ i915_min_freq_set(void *data, u64 val)
2907 * Turbo will still be enabled, but won't go below the set value. 2985 * Turbo will still be enabled, but won't go below the set value.
2908 */ 2986 */
2909 if (IS_VALLEYVIEW(dev)) { 2987 if (IS_VALLEYVIEW(dev)) {
2910 val = vlv_freq_opcode(dev_priv->mem_freq, val); 2988 val = vlv_freq_opcode(dev_priv, val);
2911 dev_priv->rps.min_delay = val; 2989 dev_priv->rps.min_delay = val;
2912 valleyview_set_rps(dev, val); 2990 valleyview_set_rps(dev, val);
2913 } else { 2991 } else {
@@ -2983,7 +3061,7 @@ static int i915_forcewake_open(struct inode *inode, struct file *file)
2983 if (INTEL_INFO(dev)->gen < 6) 3061 if (INTEL_INFO(dev)->gen < 6)
2984 return 0; 3062 return 0;
2985 3063
2986 gen6_gt_force_wake_get(dev_priv); 3064 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
2987 3065
2988 return 0; 3066 return 0;
2989} 3067}
@@ -2996,7 +3074,7 @@ static int i915_forcewake_release(struct inode *inode, struct file *file)
2996 if (INTEL_INFO(dev)->gen < 6) 3074 if (INTEL_INFO(dev)->gen < 6)
2997 return 0; 3075 return 0;
2998 3076
2999 gen6_gt_force_wake_put(dev_priv); 3077 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3000 3078
3001 return 0; 3079 return 0;
3002} 3080}
@@ -3079,6 +3157,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
3079 {"i915_edp_psr_status", i915_edp_psr_status, 0}, 3157 {"i915_edp_psr_status", i915_edp_psr_status, 0},
3080 {"i915_energy_uJ", i915_energy_uJ, 0}, 3158 {"i915_energy_uJ", i915_energy_uJ, 0},
3081 {"i915_pc8_status", i915_pc8_status, 0}, 3159 {"i915_pc8_status", i915_pc8_status, 0},
3160 {"i915_power_domain_info", i915_power_domain_info, 0},
3082}; 3161};
3083#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list) 3162#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
3084 3163
@@ -3102,10 +3181,10 @@ static const struct i915_debugfs_files {
3102void intel_display_crc_init(struct drm_device *dev) 3181void intel_display_crc_init(struct drm_device *dev)
3103{ 3182{
3104 struct drm_i915_private *dev_priv = dev->dev_private; 3183 struct drm_i915_private *dev_priv = dev->dev_private;
3105 int i; 3184 enum pipe pipe;
3106 3185
3107 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) { 3186 for_each_pipe(pipe) {
3108 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[i]; 3187 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
3109 3188
3110 pipe_crc->opened = false; 3189 pipe_crc->opened = false;
3111 spin_lock_init(&pipe_crc->lock); 3190 spin_lock_init(&pipe_crc->lock);
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 0cab2d045135..89e4cf1bb073 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -1486,7 +1486,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1486 1486
1487 spin_lock_init(&dev_priv->irq_lock); 1487 spin_lock_init(&dev_priv->irq_lock);
1488 spin_lock_init(&dev_priv->gpu_error.lock); 1488 spin_lock_init(&dev_priv->gpu_error.lock);
1489 spin_lock_init(&dev_priv->backlight.lock); 1489 spin_lock_init(&dev_priv->backlight_lock);
1490 spin_lock_init(&dev_priv->uncore.lock); 1490 spin_lock_init(&dev_priv->uncore.lock);
1491 spin_lock_init(&dev_priv->mm.object_stat_lock); 1491 spin_lock_init(&dev_priv->mm.object_stat_lock);
1492 mutex_init(&dev_priv->dpio_lock); 1492 mutex_init(&dev_priv->dpio_lock);
@@ -1639,8 +1639,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1639 goto out_gem_unload; 1639 goto out_gem_unload;
1640 } 1640 }
1641 1641
1642 if (HAS_POWER_WELL(dev)) 1642 intel_power_domains_init(dev);
1643 intel_power_domains_init(dev);
1644 1643
1645 if (drm_core_check_feature(dev, DRIVER_MODESET)) { 1644 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1646 ret = i915_load_modeset_init(dev); 1645 ret = i915_load_modeset_init(dev);
@@ -1667,8 +1666,7 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags)
1667 return 0; 1666 return 0;
1668 1667
1669out_power_well: 1668out_power_well:
1670 if (HAS_POWER_WELL(dev)) 1669 intel_power_domains_remove(dev);
1671 intel_power_domains_remove(dev);
1672 drm_vblank_cleanup(dev); 1670 drm_vblank_cleanup(dev);
1673out_gem_unload: 1671out_gem_unload:
1674 if (dev_priv->mm.inactive_shrinker.scan_objects) 1672 if (dev_priv->mm.inactive_shrinker.scan_objects)
@@ -1706,13 +1704,11 @@ int i915_driver_unload(struct drm_device *dev)
1706 1704
1707 intel_gpu_ips_teardown(); 1705 intel_gpu_ips_teardown();
1708 1706
1709 if (HAS_POWER_WELL(dev)) { 1707 /* The i915.ko module is still not prepared to be loaded when
1710 /* The i915.ko module is still not prepared to be loaded when 1708 * the power well is not enabled, so just enable it in case
1711 * the power well is not enabled, so just enable it in case 1709 * we're going to unload/reload. */
1712 * we're going to unload/reload. */ 1710 intel_display_set_init_power(dev, true);
1713 intel_display_set_init_power(dev, true); 1711 intel_power_domains_remove(dev);
1714 intel_power_domains_remove(dev);
1715 }
1716 1712
1717 i915_teardown_sysfs(dev); 1713 i915_teardown_sysfs(dev);
1718 1714
@@ -1777,7 +1773,6 @@ int i915_driver_unload(struct drm_device *dev)
1777 1773
1778 list_del(&dev_priv->gtt.base.global_link); 1774 list_del(&dev_priv->gtt.base.global_link);
1779 WARN_ON(!list_empty(&dev_priv->vm_list)); 1775 WARN_ON(!list_empty(&dev_priv->vm_list));
1780 drm_mm_takedown(&dev_priv->gtt.base.mm);
1781 1776
1782 drm_vblank_cleanup(dev); 1777 drm_vblank_cleanup(dev);
1783 1778
@@ -1908,6 +1903,7 @@ const struct drm_ioctl_desc i915_ioctls[] = {
1908 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), 1903 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1909 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), 1904 DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1910 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW), 1905 DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1906 DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1911}; 1907};
1912 1908
1913int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls); 1909int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2e367a1c6a64..0ec0fb32a103 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -114,7 +114,7 @@ MODULE_PARM_DESC(enable_hangcheck,
114 "(default: true)"); 114 "(default: true)");
115 115
116int i915_enable_ppgtt __read_mostly = -1; 116int i915_enable_ppgtt __read_mostly = -1;
117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600); 117module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0400);
118MODULE_PARM_DESC(i915_enable_ppgtt, 118MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)"); 119 "Enable PPGTT (default: true)");
120 120
@@ -155,7 +155,6 @@ MODULE_PARM_DESC(prefault_disable,
155 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only."); 155 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
156 156
157static struct drm_driver driver; 157static struct drm_driver driver;
158extern int intel_agp_enabled;
159 158
160static const struct intel_device_info intel_i830_info = { 159static const struct intel_device_info intel_i830_info = {
161 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2, 160 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
@@ -265,6 +264,7 @@ static const struct intel_device_info intel_ironlake_m_info = {
265static const struct intel_device_info intel_sandybridge_d_info = { 264static const struct intel_device_info intel_sandybridge_d_info = {
266 .gen = 6, .num_pipes = 2, 265 .gen = 6, .num_pipes = 2,
267 .need_gfx_hws = 1, .has_hotplug = 1, 266 .need_gfx_hws = 1, .has_hotplug = 1,
267 .has_fbc = 1,
268 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, 268 .ring_mask = RENDER_RING | BSD_RING | BLT_RING,
269 .has_llc = 1, 269 .has_llc = 1,
270}; 270};
@@ -280,6 +280,7 @@ static const struct intel_device_info intel_sandybridge_m_info = {
280#define GEN7_FEATURES \ 280#define GEN7_FEATURES \
281 .gen = 7, .num_pipes = 3, \ 281 .gen = 7, .num_pipes = 3, \
282 .need_gfx_hws = 1, .has_hotplug = 1, \ 282 .need_gfx_hws = 1, .has_hotplug = 1, \
283 .has_fbc = 1, \
283 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \ 284 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
284 .has_llc = 1 285 .has_llc = 1
285 286
@@ -292,7 +293,6 @@ static const struct intel_device_info intel_ivybridge_m_info = {
292 GEN7_FEATURES, 293 GEN7_FEATURES,
293 .is_ivybridge = 1, 294 .is_ivybridge = 1,
294 .is_mobile = 1, 295 .is_mobile = 1,
295 .has_fbc = 1,
296}; 296};
297 297
298static const struct intel_device_info intel_ivybridge_q_info = { 298static const struct intel_device_info intel_ivybridge_q_info = {
@@ -307,6 +307,7 @@ static const struct intel_device_info intel_valleyview_m_info = {
307 .num_pipes = 2, 307 .num_pipes = 2,
308 .is_valleyview = 1, 308 .is_valleyview = 1,
309 .display_mmio_offset = VLV_DISPLAY_BASE, 309 .display_mmio_offset = VLV_DISPLAY_BASE,
310 .has_fbc = 0, /* legal, last one wins */
310 .has_llc = 0, /* legal, last one wins */ 311 .has_llc = 0, /* legal, last one wins */
311}; 312};
312 313
@@ -315,6 +316,7 @@ static const struct intel_device_info intel_valleyview_d_info = {
315 .num_pipes = 2, 316 .num_pipes = 2,
316 .is_valleyview = 1, 317 .is_valleyview = 1,
317 .display_mmio_offset = VLV_DISPLAY_BASE, 318 .display_mmio_offset = VLV_DISPLAY_BASE,
319 .has_fbc = 0, /* legal, last one wins */
318 .has_llc = 0, /* legal, last one wins */ 320 .has_llc = 0, /* legal, last one wins */
319}; 321};
320 322
@@ -332,7 +334,6 @@ static const struct intel_device_info intel_haswell_m_info = {
332 .is_mobile = 1, 334 .is_mobile = 1,
333 .has_ddi = 1, 335 .has_ddi = 1,
334 .has_fpga_dbg = 1, 336 .has_fpga_dbg = 1,
335 .has_fbc = 1,
336 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, 337 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING,
337}; 338};
338 339
@@ -761,14 +762,14 @@ int i915_reset(struct drm_device *dev)
761 DRM_INFO("Simulated gpu hang, resetting stop_rings\n"); 762 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
762 dev_priv->gpu_error.stop_rings = 0; 763 dev_priv->gpu_error.stop_rings = 0;
763 if (ret == -ENODEV) { 764 if (ret == -ENODEV) {
764 DRM_ERROR("Reset not implemented, but ignoring " 765 DRM_INFO("Reset not implemented, but ignoring "
765 "error for simulated gpu hangs\n"); 766 "error for simulated gpu hangs\n");
766 ret = 0; 767 ret = 0;
767 } 768 }
768 } 769 }
769 770
770 if (ret) { 771 if (ret) {
771 DRM_ERROR("Failed to reset chip.\n"); 772 DRM_ERROR("Failed to reset chip: %i\n", ret);
772 mutex_unlock(&dev->struct_mutex); 773 mutex_unlock(&dev->struct_mutex);
773 return ret; 774 return ret;
774 } 775 }
@@ -789,12 +790,9 @@ int i915_reset(struct drm_device *dev)
789 */ 790 */
790 if (drm_core_check_feature(dev, DRIVER_MODESET) || 791 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
791 !dev_priv->ums.mm_suspended) { 792 !dev_priv->ums.mm_suspended) {
792 bool hw_contexts_disabled = dev_priv->hw_contexts_disabled;
793 dev_priv->ums.mm_suspended = 0; 793 dev_priv->ums.mm_suspended = 0;
794 794
795 ret = i915_gem_init_hw(dev); 795 ret = i915_gem_init_hw(dev);
796 if (!hw_contexts_disabled && dev_priv->hw_contexts_disabled)
797 DRM_ERROR("HW contexts didn't survive reset\n");
798 mutex_unlock(&dev->struct_mutex); 796 mutex_unlock(&dev->struct_mutex);
799 if (ret) { 797 if (ret) {
800 DRM_ERROR("Failed hw init on reset %d\n", ret); 798 DRM_ERROR("Failed hw init on reset %d\n", ret);
@@ -830,17 +828,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
830 if (PCI_FUNC(pdev->devfn)) 828 if (PCI_FUNC(pdev->devfn))
831 return -ENODEV; 829 return -ENODEV;
832 830
833 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC 831 driver.driver_features &= ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
834 * implementation for gen3 (and only gen3) that used legacy drm maps
835 * (gasp!) to share buffers between X and the client. Hence we need to
836 * keep around the fake agp stuff for gen3, even when kms is enabled. */
837 if (intel_info->gen != 3) {
838 driver.driver_features &=
839 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
840 } else if (!intel_agp_enabled) {
841 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
842 return -ENODEV;
843 }
844 832
845 return drm_get_pci_dev(pdev, ent, &driver); 833 return drm_get_pci_dev(pdev, ent, &driver);
846} 834}
@@ -1023,14 +1011,24 @@ static int __init i915_init(void)
1023 driver.driver_features &= ~DRIVER_MODESET; 1011 driver.driver_features &= ~DRIVER_MODESET;
1024#endif 1012#endif
1025 1013
1026 if (!(driver.driver_features & DRIVER_MODESET)) 1014 if (!(driver.driver_features & DRIVER_MODESET)) {
1027 driver.get_vblank_timestamp = NULL; 1015 driver.get_vblank_timestamp = NULL;
1016#ifndef CONFIG_DRM_I915_UMS
1017 /* Silently fail loading to not upset userspace. */
1018 return 0;
1019#endif
1020 }
1028 1021
1029 return drm_pci_init(&driver, &i915_pci_driver); 1022 return drm_pci_init(&driver, &i915_pci_driver);
1030} 1023}
1031 1024
1032static void __exit i915_exit(void) 1025static void __exit i915_exit(void)
1033{ 1026{
1027#ifndef CONFIG_DRM_I915_UMS
1028 if (!(driver.driver_features & DRIVER_MODESET))
1029 return; /* Never loaded a driver. */
1030#endif
1031
1034 drm_pci_exit(&driver, &i915_pci_driver); 1032 drm_pci_exit(&driver, &i915_pci_driver);
1035} 1033}
1036 1034
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index ccdbecca070d..780f815b6c9f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -89,6 +89,18 @@ enum port {
89}; 89};
90#define port_name(p) ((p) + 'A') 90#define port_name(p) ((p) + 'A')
91 91
92#define I915_NUM_PHYS_VLV 1
93
94enum dpio_channel {
95 DPIO_CH0,
96 DPIO_CH1
97};
98
99enum dpio_phy {
100 DPIO_PHY0,
101 DPIO_PHY1
102};
103
92enum intel_display_power_domain { 104enum intel_display_power_domain {
93 POWER_DOMAIN_PIPE_A, 105 POWER_DOMAIN_PIPE_A,
94 POWER_DOMAIN_PIPE_B, 106 POWER_DOMAIN_PIPE_B,
@@ -101,6 +113,7 @@ enum intel_display_power_domain {
101 POWER_DOMAIN_TRANSCODER_C, 113 POWER_DOMAIN_TRANSCODER_C,
102 POWER_DOMAIN_TRANSCODER_EDP, 114 POWER_DOMAIN_TRANSCODER_EDP,
103 POWER_DOMAIN_VGA, 115 POWER_DOMAIN_VGA,
116 POWER_DOMAIN_AUDIO,
104 POWER_DOMAIN_INIT, 117 POWER_DOMAIN_INIT,
105 118
106 POWER_DOMAIN_NUM, 119 POWER_DOMAIN_NUM,
@@ -351,6 +364,7 @@ struct drm_i915_error_state {
351 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS]; 364 enum intel_ring_hangcheck_action hangcheck_action[I915_NUM_RINGS];
352}; 365};
353 366
367struct intel_connector;
354struct intel_crtc_config; 368struct intel_crtc_config;
355struct intel_crtc; 369struct intel_crtc;
356struct intel_limit; 370struct intel_limit;
@@ -413,11 +427,20 @@ struct drm_i915_display_funcs {
413 /* render clock increase/decrease */ 427 /* render clock increase/decrease */
414 /* display clock increase/decrease */ 428 /* display clock increase/decrease */
415 /* pll clock increase/decrease */ 429 /* pll clock increase/decrease */
430
431 int (*setup_backlight)(struct intel_connector *connector);
432 uint32_t (*get_backlight)(struct intel_connector *connector);
433 void (*set_backlight)(struct intel_connector *connector,
434 uint32_t level);
435 void (*disable_backlight)(struct intel_connector *connector);
436 void (*enable_backlight)(struct intel_connector *connector);
416}; 437};
417 438
418struct intel_uncore_funcs { 439struct intel_uncore_funcs {
419 void (*force_wake_get)(struct drm_i915_private *dev_priv); 440 void (*force_wake_get)(struct drm_i915_private *dev_priv,
420 void (*force_wake_put)(struct drm_i915_private *dev_priv); 441 int fw_engine);
442 void (*force_wake_put)(struct drm_i915_private *dev_priv,
443 int fw_engine);
421 444
422 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 445 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
423 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace); 446 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
@@ -442,6 +465,9 @@ struct intel_uncore {
442 unsigned fifo_count; 465 unsigned fifo_count;
443 unsigned forcewake_count; 466 unsigned forcewake_count;
444 467
468 unsigned fw_rendercount;
469 unsigned fw_mediacount;
470
445 struct delayed_work force_wake_work; 471 struct delayed_work force_wake_work;
446}; 472};
447 473
@@ -708,7 +734,6 @@ enum intel_sbi_destination {
708#define QUIRK_PIPEA_FORCE (1<<0) 734#define QUIRK_PIPEA_FORCE (1<<0)
709#define QUIRK_LVDS_SSC_DISABLE (1<<1) 735#define QUIRK_LVDS_SSC_DISABLE (1<<1)
710#define QUIRK_INVERT_BRIGHTNESS (1<<2) 736#define QUIRK_INVERT_BRIGHTNESS (1<<2)
711#define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
712 737
713struct intel_fbdev; 738struct intel_fbdev;
714struct intel_fbc_work; 739struct intel_fbc_work;
@@ -761,8 +786,6 @@ struct i915_suspend_saved_registers {
761 u32 saveBLC_PWM_CTL; 786 u32 saveBLC_PWM_CTL;
762 u32 saveBLC_PWM_CTL2; 787 u32 saveBLC_PWM_CTL2;
763 u32 saveBLC_HIST_CTL_B; 788 u32 saveBLC_HIST_CTL_B;
764 u32 saveBLC_PWM_CTL_B;
765 u32 saveBLC_PWM_CTL2_B;
766 u32 saveBLC_CPU_PWM_CTL; 789 u32 saveBLC_CPU_PWM_CTL;
767 u32 saveBLC_CPU_PWM_CTL2; 790 u32 saveBLC_CPU_PWM_CTL2;
768 u32 saveFPB0; 791 u32 saveFPB0;
@@ -932,21 +955,29 @@ struct intel_ilk_power_mgmt {
932 955
933/* Power well structure for haswell */ 956/* Power well structure for haswell */
934struct i915_power_well { 957struct i915_power_well {
958 const char *name;
959 bool always_on;
935 /* power well enable/disable usage count */ 960 /* power well enable/disable usage count */
936 int count; 961 int count;
962 unsigned long domains;
963 void *data;
964 void (*set)(struct drm_device *dev, struct i915_power_well *power_well,
965 bool enable);
966 bool (*is_enabled)(struct drm_device *dev,
967 struct i915_power_well *power_well);
937}; 968};
938 969
939#define I915_MAX_POWER_WELLS 1
940
941struct i915_power_domains { 970struct i915_power_domains {
942 /* 971 /*
943 * Power wells needed for initialization at driver init and suspend 972 * Power wells needed for initialization at driver init and suspend
944 * time are on. They are kept on until after the first modeset. 973 * time are on. They are kept on until after the first modeset.
945 */ 974 */
946 bool init_power_on; 975 bool init_power_on;
976 int power_well_count;
947 977
948 struct mutex lock; 978 struct mutex lock;
949 struct i915_power_well power_wells[I915_MAX_POWER_WELLS]; 979 int domain_use_count[POWER_DOMAIN_NUM];
980 struct i915_power_well *power_wells;
950}; 981};
951 982
952struct i915_dri1_state { 983struct i915_dri1_state {
@@ -1077,34 +1108,30 @@ struct i915_gpu_error {
1077 unsigned long missed_irq_rings; 1108 unsigned long missed_irq_rings;
1078 1109
1079 /** 1110 /**
1080 * State variable and reset counter controlling the reset flow 1111 * State variable controlling the reset flow and count
1081 * 1112 *
1082 * Upper bits are for the reset counter. This counter is used by the 1113 * This is a counter which gets incremented when reset is triggered,
1083 * wait_seqno code to race-free noticed that a reset event happened and 1114 * and again when reset has been handled. So odd values (lowest bit set)
1084 * that it needs to restart the entire ioctl (since most likely the 1115 * means that reset is in progress and even values that
1085 * seqno it waited for won't ever signal anytime soon). 1116 * (reset_counter >> 1):th reset was successfully completed.
1117 *
1118 * If reset is not completed succesfully, the I915_WEDGE bit is
1119 * set meaning that hardware is terminally sour and there is no
1120 * recovery. All waiters on the reset_queue will be woken when
1121 * that happens.
1122 *
1123 * This counter is used by the wait_seqno code to notice that reset
1124 * event happened and it needs to restart the entire ioctl (since most
1125 * likely the seqno it waited for won't ever signal anytime soon).
1086 * 1126 *
1087 * This is important for lock-free wait paths, where no contended lock 1127 * This is important for lock-free wait paths, where no contended lock
1088 * naturally enforces the correct ordering between the bail-out of the 1128 * naturally enforces the correct ordering between the bail-out of the
1089 * waiter and the gpu reset work code. 1129 * waiter and the gpu reset work code.
1090 *
1091 * Lowest bit controls the reset state machine: Set means a reset is in
1092 * progress. This state will (presuming we don't have any bugs) decay
1093 * into either unset (successful reset) or the special WEDGED value (hw
1094 * terminally sour). All waiters on the reset_queue will be woken when
1095 * that happens.
1096 */ 1130 */
1097 atomic_t reset_counter; 1131 atomic_t reset_counter;
1098 1132
1099 /**
1100 * Special values/flags for reset_counter
1101 *
1102 * Note that the code relies on
1103 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1104 * being true.
1105 */
1106#define I915_RESET_IN_PROGRESS_FLAG 1 1133#define I915_RESET_IN_PROGRESS_FLAG 1
1107#define I915_WEDGED 0xffffffff 1134#define I915_WEDGED (1 << 31)
1108 1135
1109 /** 1136 /**
1110 * Waitqueue to signal when the reset has completed. Used by clients 1137 * Waitqueue to signal when the reset has completed. Used by clients
@@ -1368,13 +1395,8 @@ typedef struct drm_i915_private {
1368 struct intel_overlay *overlay; 1395 struct intel_overlay *overlay;
1369 unsigned int sprite_scaling_enabled; 1396 unsigned int sprite_scaling_enabled;
1370 1397
1371 /* backlight */ 1398 /* backlight registers and fields in struct intel_panel */
1372 struct { 1399 spinlock_t backlight_lock;
1373 int level;
1374 bool enabled;
1375 spinlock_t lock; /* bl registers and the above bl fields */
1376 struct backlight_device *device;
1377 } backlight;
1378 1400
1379 /* LVDS info */ 1401 /* LVDS info */
1380 bool no_aux_handshake; 1402 bool no_aux_handshake;
@@ -1426,6 +1448,7 @@ typedef struct drm_i915_private {
1426 int num_shared_dpll; 1448 int num_shared_dpll;
1427 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS]; 1449 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1428 struct intel_ddi_plls ddi_plls; 1450 struct intel_ddi_plls ddi_plls;
1451 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1429 1452
1430 /* Reclocking support */ 1453 /* Reclocking support */
1431 bool render_reclock_avail; 1454 bool render_reclock_avail;
@@ -1470,7 +1493,6 @@ typedef struct drm_i915_private {
1470 struct drm_property *broadcast_rgb_property; 1493 struct drm_property *broadcast_rgb_property;
1471 struct drm_property *force_audio_property; 1494 struct drm_property *force_audio_property;
1472 1495
1473 bool hw_contexts_disabled;
1474 uint32_t hw_context_size; 1496 uint32_t hw_context_size;
1475 struct list_head context_list; 1497 struct list_head context_list;
1476 1498
@@ -1755,8 +1777,13 @@ struct drm_i915_file_private {
1755#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile) 1777#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1756#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \ 1778#define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1757 ((dev)->pdev->device & 0xFF00) == 0x0C00) 1779 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1758#define IS_ULT(dev) (IS_HASWELL(dev) && \ 1780#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1781 (((dev)->pdev->device & 0xf) == 0x2 || \
1782 ((dev)->pdev->device & 0xf) == 0x6 || \
1783 ((dev)->pdev->device & 0xf) == 0xe))
1784#define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1759 ((dev)->pdev->device & 0xFF00) == 0x0A00) 1785 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1786#define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1760#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \ 1787#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1761 ((dev)->pdev->device & 0x00F0) == 0x0020) 1788 ((dev)->pdev->device & 0x00F0) == 0x0020)
1762#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary) 1789#define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
@@ -1813,7 +1840,6 @@ struct drm_i915_file_private {
1813#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev)) 1840#define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1814 1841
1815#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi) 1842#define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1816#define HAS_POWER_WELL(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1817#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg) 1843#define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1818#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev)) 1844#define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1819#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */ 1845#define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
@@ -1908,7 +1934,6 @@ extern void intel_pm_init(struct drm_device *dev);
1908extern void intel_uncore_sanitize(struct drm_device *dev); 1934extern void intel_uncore_sanitize(struct drm_device *dev);
1909extern void intel_uncore_early_sanitize(struct drm_device *dev); 1935extern void intel_uncore_early_sanitize(struct drm_device *dev);
1910extern void intel_uncore_init(struct drm_device *dev); 1936extern void intel_uncore_init(struct drm_device *dev);
1911extern void intel_uncore_clear_errors(struct drm_device *dev);
1912extern void intel_uncore_check_errors(struct drm_device *dev); 1937extern void intel_uncore_check_errors(struct drm_device *dev);
1913extern void intel_uncore_fini(struct drm_device *dev); 1938extern void intel_uncore_fini(struct drm_device *dev);
1914 1939
@@ -2060,12 +2085,17 @@ int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2060static inline bool i915_reset_in_progress(struct i915_gpu_error *error) 2085static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2061{ 2086{
2062 return unlikely(atomic_read(&error->reset_counter) 2087 return unlikely(atomic_read(&error->reset_counter)
2063 & I915_RESET_IN_PROGRESS_FLAG); 2088 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2064} 2089}
2065 2090
2066static inline bool i915_terminally_wedged(struct i915_gpu_error *error) 2091static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2067{ 2092{
2068 return atomic_read(&error->reset_counter) == I915_WEDGED; 2093 return atomic_read(&error->reset_counter) & I915_WEDGED;
2094}
2095
2096static inline u32 i915_reset_count(struct i915_gpu_error *error)
2097{
2098 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2069} 2099}
2070 2100
2071void i915_gem_reset(struct drm_device *dev); 2101void i915_gem_reset(struct drm_device *dev);
@@ -2177,7 +2207,7 @@ i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2177} 2207}
2178 2208
2179/* i915_gem_context.c */ 2209/* i915_gem_context.c */
2180void i915_gem_context_init(struct drm_device *dev); 2210int __must_check i915_gem_context_init(struct drm_device *dev);
2181void i915_gem_context_fini(struct drm_device *dev); 2211void i915_gem_context_fini(struct drm_device *dev);
2182void i915_gem_context_close(struct drm_device *dev, struct drm_file *file); 2212void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2183int i915_switch_context(struct intel_ring_buffer *ring, 2213int i915_switch_context(struct intel_ring_buffer *ring,
@@ -2395,6 +2425,8 @@ extern int intel_enable_rc6(const struct drm_device *dev);
2395extern bool i915_semaphore_is_enabled(struct drm_device *dev); 2425extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2396int i915_reg_read_ioctl(struct drm_device *dev, void *data, 2426int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2397 struct drm_file *file); 2427 struct drm_file *file);
2428int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2429 struct drm_file *file);
2398 2430
2399/* overlay */ 2431/* overlay */
2400extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev); 2432extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
@@ -2410,8 +2442,8 @@ extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2410 * must be set to prevent GT core from power down and stale values being 2442 * must be set to prevent GT core from power down and stale values being
2411 * returned. 2443 * returned.
2412 */ 2444 */
2413void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv); 2445void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2414void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv); 2446void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2415 2447
2416int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); 2448int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2417int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); 2449int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
@@ -2426,6 +2458,8 @@ u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2426void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2458void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2427u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg); 2459u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2428void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2460void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2461u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2462void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2429u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg); 2463u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2430void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val); 2464void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2431u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg); 2465u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
@@ -2435,8 +2469,27 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2435void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, 2469void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2436 enum intel_sbi_destination destination); 2470 enum intel_sbi_destination destination);
2437 2471
2438int vlv_gpu_freq(int ddr_freq, int val); 2472int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2439int vlv_freq_opcode(int ddr_freq, int val); 2473int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2474
2475void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2476void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2477
2478#define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2479 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2480 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2481 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2482 ((reg) >= 0x2E000 && (reg) < 0x30000))
2483
2484#define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2485 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2486 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2487 ((reg) >= 0x30000 && (reg) < 0x40000))
2488
2489#define FORCEWAKE_RENDER (1 << 0)
2490#define FORCEWAKE_MEDIA (1 << 1)
2491#define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2492
2440 2493
2441#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true) 2494#define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2442#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true) 2495#define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 621c7c67a643..182c521ec392 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4465,7 +4465,13 @@ i915_gem_init_hw(struct drm_device *dev)
4465 * XXX: There was some w/a described somewhere suggesting loading 4465 * XXX: There was some w/a described somewhere suggesting loading
4466 * contexts before PPGTT. 4466 * contexts before PPGTT.
4467 */ 4467 */
4468 i915_gem_context_init(dev); 4468 ret = i915_gem_context_init(dev);
4469 if (ret) {
4470 i915_gem_cleanup_ringbuffer(dev);
4471 DRM_ERROR("Context initialization failed %d\n", ret);
4472 return ret;
4473 }
4474
4469 if (dev_priv->mm.aliasing_ppgtt) { 4475 if (dev_priv->mm.aliasing_ppgtt) {
4470 ret = dev_priv->mm.aliasing_ppgtt->enable(dev); 4476 ret = dev_priv->mm.aliasing_ppgtt->enable(dev);
4471 if (ret) { 4477 if (ret) {
diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c
index 72a3df32292f..41877045a1a0 100644
--- a/drivers/gpu/drm/i915/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/i915_gem_context.c
@@ -247,36 +247,34 @@ err_destroy:
247 return ret; 247 return ret;
248} 248}
249 249
250void i915_gem_context_init(struct drm_device *dev) 250int i915_gem_context_init(struct drm_device *dev)
251{ 251{
252 struct drm_i915_private *dev_priv = dev->dev_private; 252 struct drm_i915_private *dev_priv = dev->dev_private;
253 int ret;
253 254
254 if (!HAS_HW_CONTEXTS(dev)) { 255 if (!HAS_HW_CONTEXTS(dev))
255 dev_priv->hw_contexts_disabled = true; 256 return 0;
256 DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
257 return;
258 }
259 257
260 /* If called from reset, or thaw... we've been here already */ 258 /* If called from reset, or thaw... we've been here already */
261 if (dev_priv->hw_contexts_disabled || 259 if (dev_priv->ring[RCS].default_context)
262 dev_priv->ring[RCS].default_context) 260 return 0;
263 return;
264 261
265 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096); 262 dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
266 263
267 if (dev_priv->hw_context_size > (1<<20)) { 264 if (dev_priv->hw_context_size > (1<<20)) {
268 dev_priv->hw_contexts_disabled = true;
269 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n"); 265 DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
270 return; 266 return -E2BIG;
271 } 267 }
272 268
273 if (create_default_context(dev_priv)) { 269 ret = create_default_context(dev_priv);
274 dev_priv->hw_contexts_disabled = true; 270 if (ret) {
275 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n"); 271 DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed %d\n",
276 return; 272 ret);
273 return ret;
277 } 274 }
278 275
279 DRM_DEBUG_DRIVER("HW context support initialized\n"); 276 DRM_DEBUG_DRIVER("HW context support initialized\n");
277 return 0;
280} 278}
281 279
282void i915_gem_context_fini(struct drm_device *dev) 280void i915_gem_context_fini(struct drm_device *dev)
@@ -284,7 +282,7 @@ void i915_gem_context_fini(struct drm_device *dev)
284 struct drm_i915_private *dev_priv = dev->dev_private; 282 struct drm_i915_private *dev_priv = dev->dev_private;
285 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context; 283 struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
286 284
287 if (dev_priv->hw_contexts_disabled) 285 if (!HAS_HW_CONTEXTS(dev))
288 return; 286 return;
289 287
290 /* The only known way to stop the gpu from accessing the hw context is 288 /* The only known way to stop the gpu from accessing the hw context is
@@ -327,16 +325,16 @@ i915_gem_context_get_hang_stats(struct drm_device *dev,
327 struct drm_file *file, 325 struct drm_file *file,
328 u32 id) 326 u32 id)
329{ 327{
330 struct drm_i915_private *dev_priv = dev->dev_private;
331 struct drm_i915_file_private *file_priv = file->driver_priv; 328 struct drm_i915_file_private *file_priv = file->driver_priv;
332 struct i915_hw_context *ctx; 329 struct i915_hw_context *ctx;
333 330
334 if (id == DEFAULT_CONTEXT_ID) 331 if (id == DEFAULT_CONTEXT_ID)
335 return &file_priv->hang_stats; 332 return &file_priv->hang_stats;
336 333
337 ctx = NULL; 334 if (!HAS_HW_CONTEXTS(dev))
338 if (!dev_priv->hw_contexts_disabled) 335 return ERR_PTR(-ENOENT);
339 ctx = i915_gem_context_get(file->driver_priv, id); 336
337 ctx = i915_gem_context_get(file->driver_priv, id);
340 if (ctx == NULL) 338 if (ctx == NULL)
341 return ERR_PTR(-ENOENT); 339 return ERR_PTR(-ENOENT);
342 340
@@ -494,8 +492,6 @@ static int do_switch(struct i915_hw_context *to)
494 * @ring: ring for which we'll execute the context switch 492 * @ring: ring for which we'll execute the context switch
495 * @file_priv: file_priv associated with the context, may be NULL 493 * @file_priv: file_priv associated with the context, may be NULL
496 * @id: context id number 494 * @id: context id number
497 * @seqno: sequence number by which the new context will be switched to
498 * @flags:
499 * 495 *
500 * The context life cycle is simple. The context refcount is incremented and 496 * The context life cycle is simple. The context refcount is incremented and
501 * decremented by 1 and create and destroy. If the context is in use by the GPU, 497 * decremented by 1 and create and destroy. If the context is in use by the GPU,
@@ -509,7 +505,7 @@ int i915_switch_context(struct intel_ring_buffer *ring,
509 struct drm_i915_private *dev_priv = ring->dev->dev_private; 505 struct drm_i915_private *dev_priv = ring->dev->dev_private;
510 struct i915_hw_context *to; 506 struct i915_hw_context *to;
511 507
512 if (dev_priv->hw_contexts_disabled) 508 if (!HAS_HW_CONTEXTS(ring->dev))
513 return 0; 509 return 0;
514 510
515 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex)); 511 WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
@@ -534,7 +530,6 @@ int i915_switch_context(struct intel_ring_buffer *ring,
534int i915_gem_context_create_ioctl(struct drm_device *dev, void *data, 530int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
535 struct drm_file *file) 531 struct drm_file *file)
536{ 532{
537 struct drm_i915_private *dev_priv = dev->dev_private;
538 struct drm_i915_gem_context_create *args = data; 533 struct drm_i915_gem_context_create *args = data;
539 struct drm_i915_file_private *file_priv = file->driver_priv; 534 struct drm_i915_file_private *file_priv = file->driver_priv;
540 struct i915_hw_context *ctx; 535 struct i915_hw_context *ctx;
@@ -543,7 +538,7 @@ int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
543 if (!(dev->driver->driver_features & DRIVER_GEM)) 538 if (!(dev->driver->driver_features & DRIVER_GEM))
544 return -ENODEV; 539 return -ENODEV;
545 540
546 if (dev_priv->hw_contexts_disabled) 541 if (!HAS_HW_CONTEXTS(dev))
547 return -ENODEV; 542 return -ENODEV;
548 543
549 ret = i915_mutex_lock_interruptible(dev); 544 ret = i915_mutex_lock_interruptible(dev);
diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
index b7e787fb4649..3c90dd1a3bbd 100644
--- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
@@ -46,7 +46,7 @@ struct eb_vmas {
46}; 46};
47 47
48static struct eb_vmas * 48static struct eb_vmas *
49eb_create(struct drm_i915_gem_execbuffer2 *args, struct i915_address_space *vm) 49eb_create(struct drm_i915_gem_execbuffer2 *args)
50{ 50{
51 struct eb_vmas *eb = NULL; 51 struct eb_vmas *eb = NULL;
52 52
@@ -332,7 +332,7 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
332 target_i915_obj = target_vma->obj; 332 target_i915_obj = target_vma->obj;
333 target_obj = &target_vma->obj->base; 333 target_obj = &target_vma->obj->base;
334 334
335 target_offset = i915_gem_obj_ggtt_offset(target_i915_obj); 335 target_offset = target_vma->node.start;
336 336
337 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and 337 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
338 * pipe_control writes because the gpu doesn't properly redirect them 338 * pipe_control writes because the gpu doesn't properly redirect them
@@ -479,8 +479,7 @@ i915_gem_execbuffer_relocate_vma_slow(struct i915_vma *vma,
479} 479}
480 480
481static int 481static int
482i915_gem_execbuffer_relocate(struct eb_vmas *eb, 482i915_gem_execbuffer_relocate(struct eb_vmas *eb)
483 struct i915_address_space *vm)
484{ 483{
485 struct i915_vma *vma; 484 struct i915_vma *vma;
486 int ret = 0; 485 int ret = 0;
@@ -1106,7 +1105,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1106 goto pre_mutex_err; 1105 goto pre_mutex_err;
1107 } 1106 }
1108 1107
1109 eb = eb_create(args, vm); 1108 eb = eb_create(args);
1110 if (eb == NULL) { 1109 if (eb == NULL) {
1111 mutex_unlock(&dev->struct_mutex); 1110 mutex_unlock(&dev->struct_mutex);
1112 ret = -ENOMEM; 1111 ret = -ENOMEM;
@@ -1129,7 +1128,7 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
1129 1128
1130 /* The objects are in their final locations, apply the relocations. */ 1129 /* The objects are in their final locations, apply the relocations. */
1131 if (need_relocs) 1130 if (need_relocs)
1132 ret = i915_gem_execbuffer_relocate(eb, vm); 1131 ret = i915_gem_execbuffer_relocate(eb);
1133 if (ret) { 1132 if (ret) {
1134 if (ret == -EFAULT) { 1133 if (ret == -EFAULT) {
1135 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring, 1134 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 38cb8d44a013..a54eaabb3a3e 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -240,10 +240,16 @@ static int gen8_ppgtt_enable(struct drm_device *dev)
240 for_each_ring(ring, dev_priv, j) { 240 for_each_ring(ring, dev_priv, j) {
241 ret = gen8_write_pdp(ring, i, addr); 241 ret = gen8_write_pdp(ring, i, addr);
242 if (ret) 242 if (ret)
243 return ret; 243 goto err_out;
244 } 244 }
245 } 245 }
246 return 0; 246 return 0;
247
248err_out:
249 for_each_ring(ring, dev_priv, j)
250 I915_WRITE(RING_MODE_GEN7(ring),
251 _MASKED_BIT_DISABLE(GFX_PPGTT_ENABLE));
252 return ret;
247} 253}
248 254
249static void gen8_ppgtt_clear_range(struct i915_address_space *vm, 255static void gen8_ppgtt_clear_range(struct i915_address_space *vm,
@@ -318,6 +324,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
318 container_of(vm, struct i915_hw_ppgtt, base); 324 container_of(vm, struct i915_hw_ppgtt, base);
319 int i, j; 325 int i, j;
320 326
327 drm_mm_takedown(&vm->mm);
328
321 for (i = 0; i < ppgtt->num_pd_pages ; i++) { 329 for (i = 0; i < ppgtt->num_pd_pages ; i++) {
322 if (ppgtt->pd_dma_addr[i]) { 330 if (ppgtt->pd_dma_addr[i]) {
323 pci_unmap_page(ppgtt->base.dev->pdev, 331 pci_unmap_page(ppgtt->base.dev->pdev,
@@ -337,8 +345,8 @@ static void gen8_ppgtt_cleanup(struct i915_address_space *vm)
337 kfree(ppgtt->gen8_pt_dma_addr[i]); 345 kfree(ppgtt->gen8_pt_dma_addr[i]);
338 } 346 }
339 347
340 __free_pages(ppgtt->gen8_pt_pages, ppgtt->num_pt_pages << PAGE_SHIFT); 348 __free_pages(ppgtt->gen8_pt_pages, get_order(ppgtt->num_pt_pages << PAGE_SHIFT));
341 __free_pages(ppgtt->pd_pages, ppgtt->num_pd_pages << PAGE_SHIFT); 349 __free_pages(ppgtt->pd_pages, get_order(ppgtt->num_pd_pages << PAGE_SHIFT));
342} 350}
343 351
344/** 352/**
@@ -381,6 +389,8 @@ static int gen8_ppgtt_init(struct i915_hw_ppgtt *ppgtt, uint64_t size)
381 ppgtt->base.clear_range = gen8_ppgtt_clear_range; 389 ppgtt->base.clear_range = gen8_ppgtt_clear_range;
382 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries; 390 ppgtt->base.insert_entries = gen8_ppgtt_insert_entries;
383 ppgtt->base.cleanup = gen8_ppgtt_cleanup; 391 ppgtt->base.cleanup = gen8_ppgtt_cleanup;
392 ppgtt->base.start = 0;
393 ppgtt->base.total = ppgtt->num_pt_pages * GEN8_PTES_PER_PAGE * PAGE_SIZE;
384 394
385 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS); 395 BUG_ON(ppgtt->num_pd_pages > GEN8_LEGACY_PDPS);
386 396
@@ -632,6 +642,8 @@ static int gen6_ppgtt_init(struct i915_hw_ppgtt *ppgtt)
632 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries; 642 ppgtt->base.insert_entries = gen6_ppgtt_insert_entries;
633 ppgtt->base.cleanup = gen6_ppgtt_cleanup; 643 ppgtt->base.cleanup = gen6_ppgtt_cleanup;
634 ppgtt->base.scratch = dev_priv->gtt.base.scratch; 644 ppgtt->base.scratch = dev_priv->gtt.base.scratch;
645 ppgtt->base.start = 0;
646 ppgtt->base.total = GEN6_PPGTT_PD_ENTRIES * I915_PPGTT_PT_ENTRIES * PAGE_SIZE;
635 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *), 647 ppgtt->pt_pages = kcalloc(ppgtt->num_pd_entries, sizeof(struct page *),
636 GFP_KERNEL); 648 GFP_KERNEL);
637 if (!ppgtt->pt_pages) 649 if (!ppgtt->pt_pages)
@@ -1126,7 +1138,6 @@ void i915_gem_setup_global_gtt(struct drm_device *dev,
1126 if (ret) 1138 if (ret)
1127 DRM_DEBUG_KMS("Reservation failed\n"); 1139 DRM_DEBUG_KMS("Reservation failed\n");
1128 obj->has_global_gtt_mapping = 1; 1140 obj->has_global_gtt_mapping = 1;
1129 list_add(&vma->vma_link, &obj->vma_list);
1130 } 1141 }
1131 1142
1132 dev_priv->gtt.base.start = start; 1143 dev_priv->gtt.base.start = start;
@@ -1241,6 +1252,11 @@ static inline unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl)
1241 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK; 1252 bdw_gmch_ctl &= BDW_GMCH_GGMS_MASK;
1242 if (bdw_gmch_ctl) 1253 if (bdw_gmch_ctl)
1243 bdw_gmch_ctl = 1 << bdw_gmch_ctl; 1254 bdw_gmch_ctl = 1 << bdw_gmch_ctl;
1255 if (bdw_gmch_ctl > 4) {
1256 WARN_ON(!i915_preliminary_hw_support);
1257 return 4<<20;
1258 }
1259
1244 return bdw_gmch_ctl << 20; 1260 return bdw_gmch_ctl << 20;
1245} 1261}
1246 1262
@@ -1397,6 +1413,8 @@ static void gen6_gmch_remove(struct i915_address_space *vm)
1397{ 1413{
1398 1414
1399 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base); 1415 struct i915_gtt *gtt = container_of(vm, struct i915_gtt, base);
1416
1417 drm_mm_takedown(&vm->mm);
1400 iounmap(gtt->gsm); 1418 iounmap(gtt->gsm);
1401 teardown_scratch_page(vm->dev); 1419 teardown_scratch_page(vm->dev);
1402} 1420}
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 5d1dedc02f15..271560080ad5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -600,7 +600,7 @@ static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
600 * Cook up a vblank counter by also checking the pixel 600 * Cook up a vblank counter by also checking the pixel
601 * counter against vblank start. 601 * counter against vblank start.
602 */ 602 */
603 return ((high1 << 8) | low) + (pixel >= vbl_start); 603 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
604} 604}
605 605
606static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe) 606static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
@@ -1015,10 +1015,8 @@ static void gen6_pm_rps_work(struct work_struct *work)
1015 /* sysfs frequency interfaces may have snuck in while servicing the 1015 /* sysfs frequency interfaces may have snuck in while servicing the
1016 * interrupt 1016 * interrupt
1017 */ 1017 */
1018 if (new_delay < (int)dev_priv->rps.min_delay) 1018 new_delay = clamp_t(int, new_delay,
1019 new_delay = dev_priv->rps.min_delay; 1019 dev_priv->rps.min_delay, dev_priv->rps.max_delay);
1020 if (new_delay > (int)dev_priv->rps.max_delay)
1021 new_delay = dev_priv->rps.max_delay;
1022 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay; 1020 dev_priv->rps.last_adj = new_delay - dev_priv->rps.cur_delay;
1023 1021
1024 if (IS_VALLEYVIEW(dev_priv->dev)) 1022 if (IS_VALLEYVIEW(dev_priv->dev))
@@ -1474,6 +1472,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1474 1472
1475 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915); 1473 intel_hpd_irq_handler(dev, hotplug_trigger, hpd_status_i915);
1476 1474
1475 if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1476 dp_aux_irq_handler(dev);
1477
1477 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 1478 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1478 I915_READ(PORT_HOTPLUG_STAT); 1479 I915_READ(PORT_HOTPLUG_STAT);
1479 } 1480 }
@@ -1993,7 +1994,7 @@ static void i915_error_work_func(struct work_struct *work)
1993 kobject_uevent_env(&dev->primary->kdev->kobj, 1994 kobject_uevent_env(&dev->primary->kdev->kobj,
1994 KOBJ_CHANGE, reset_done_event); 1995 KOBJ_CHANGE, reset_done_event);
1995 } else { 1996 } else {
1996 atomic_set(&error->reset_counter, I915_WEDGED); 1997 atomic_set_mask(I915_WEDGED, &error->reset_counter);
1997 } 1998 }
1998 1999
1999 /* 2000 /*
@@ -3655,6 +3656,10 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
3655 intel_hpd_irq_handler(dev, hotplug_trigger, 3656 intel_hpd_irq_handler(dev, hotplug_trigger,
3656 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915); 3657 IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i915);
3657 3658
3659 if (IS_G4X(dev) &&
3660 (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X))
3661 dp_aux_irq_handler(dev);
3662
3658 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); 3663 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
3659 I915_READ(PORT_HOTPLUG_STAT); 3664 I915_READ(PORT_HOTPLUG_STAT);
3660 } 3665 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ee2742122a02..3be449d884a7 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -354,6 +354,7 @@
354#define IOSF_BYTE_ENABLES_SHIFT 4 354#define IOSF_BYTE_ENABLES_SHIFT 4
355#define IOSF_BAR_SHIFT 1 355#define IOSF_BAR_SHIFT 1
356#define IOSF_SB_BUSY (1<<0) 356#define IOSF_SB_BUSY (1<<0)
357#define IOSF_PORT_BUNIT 0x3
357#define IOSF_PORT_PUNIT 0x4 358#define IOSF_PORT_PUNIT 0x4
358#define IOSF_PORT_NC 0x11 359#define IOSF_PORT_NC 0x11
359#define IOSF_PORT_DPIO 0x12 360#define IOSF_PORT_DPIO 0x12
@@ -364,9 +365,17 @@
364#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104) 365#define VLV_IOSF_DATA (VLV_DISPLAY_BASE + 0x2104)
365#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108) 366#define VLV_IOSF_ADDR (VLV_DISPLAY_BASE + 0x2108)
366 367
368/* See configdb bunit SB addr map */
369#define BUNIT_REG_BISOC 0x11
370
367#define PUNIT_OPCODE_REG_READ 6 371#define PUNIT_OPCODE_REG_READ 6
368#define PUNIT_OPCODE_REG_WRITE 7 372#define PUNIT_OPCODE_REG_WRITE 7
369 373
374#define PUNIT_REG_DSPFREQ 0x36
375#define DSPFREQSTAT_SHIFT 30
376#define DSPFREQSTAT_MASK (0x3 << DSPFREQSTAT_SHIFT)
377#define DSPFREQGUAR_SHIFT 14
378#define DSPFREQGUAR_MASK (0x3 << DSPFREQGUAR_SHIFT)
370#define PUNIT_REG_PWRGT_CTRL 0x60 379#define PUNIT_REG_PWRGT_CTRL 0x60
371#define PUNIT_REG_PWRGT_STATUS 0x61 380#define PUNIT_REG_PWRGT_STATUS 0x61
372#define PUNIT_CLK_GATE 1 381#define PUNIT_CLK_GATE 1
@@ -429,6 +438,7 @@
429#define DSI_PLL_N1_DIV_MASK (3 << 16) 438#define DSI_PLL_N1_DIV_MASK (3 << 16)
430#define DSI_PLL_M1_DIV_SHIFT 0 439#define DSI_PLL_M1_DIV_SHIFT 0
431#define DSI_PLL_M1_DIV_MASK (0x1ff << 0) 440#define DSI_PLL_M1_DIV_MASK (0x1ff << 0)
441#define CCK_DISPLAY_CLOCK_CONTROL 0x6b
432 442
433/* 443/*
434 * DPIO - a special bus for various display related registers to hide behind 444 * DPIO - a special bus for various display related registers to hide behind
@@ -447,15 +457,13 @@
447#define DPIO_SFR_BYPASS (1<<1) 457#define DPIO_SFR_BYPASS (1<<1)
448#define DPIO_CMNRST (1<<0) 458#define DPIO_CMNRST (1<<0)
449 459
450#define _DPIO_TX3_SWING_CTL4_A 0x690 460#define DPIO_PHY(pipe) ((pipe) >> 1)
451#define _DPIO_TX3_SWING_CTL4_B 0x2a90 461#define DPIO_PHY_IOSF_PORT(phy) (dev_priv->dpio_phy_iosf_port[phy])
452#define DPIO_TX3_SWING_CTL4(pipe) _PIPE(pipe, _DPIO_TX3_SWING_CTL4_A, \
453 _DPIO_TX3_SWING_CTL4_B)
454 462
455/* 463/*
456 * Per pipe/PLL DPIO regs 464 * Per pipe/PLL DPIO regs
457 */ 465 */
458#define _DPIO_DIV_A 0x800c 466#define _VLV_PLL_DW3_CH0 0x800c
459#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */ 467#define DPIO_POST_DIV_SHIFT (28) /* 3 bits */
460#define DPIO_POST_DIV_DAC 0 468#define DPIO_POST_DIV_DAC 0
461#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */ 469#define DPIO_POST_DIV_HDMIDP 1 /* DAC 225-400M rate */
@@ -468,10 +476,10 @@
468#define DPIO_ENABLE_CALIBRATION (1<<11) 476#define DPIO_ENABLE_CALIBRATION (1<<11)
469#define DPIO_M1DIV_SHIFT (8) /* 3 bits */ 477#define DPIO_M1DIV_SHIFT (8) /* 3 bits */
470#define DPIO_M2DIV_MASK 0xff 478#define DPIO_M2DIV_MASK 0xff
471#define _DPIO_DIV_B 0x802c 479#define _VLV_PLL_DW3_CH1 0x802c
472#define DPIO_DIV(pipe) _PIPE(pipe, _DPIO_DIV_A, _DPIO_DIV_B) 480#define VLV_PLL_DW3(ch) _PIPE(ch, _VLV_PLL_DW3_CH0, _VLV_PLL_DW3_CH1)
473 481
474#define _DPIO_REFSFR_A 0x8014 482#define _VLV_PLL_DW5_CH0 0x8014
475#define DPIO_REFSEL_OVERRIDE 27 483#define DPIO_REFSEL_OVERRIDE 27
476#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */ 484#define DPIO_PLL_MODESEL_SHIFT 24 /* 3 bits */
477#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */ 485#define DPIO_BIAS_CURRENT_CTL_SHIFT 21 /* 3 bits, always 0x7 */
@@ -479,118 +487,112 @@
479#define DPIO_PLL_REFCLK_SEL_MASK 3 487#define DPIO_PLL_REFCLK_SEL_MASK 3
480#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */ 488#define DPIO_DRIVER_CTL_SHIFT 12 /* always set to 0x8 */
481#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */ 489#define DPIO_CLK_BIAS_CTL_SHIFT 8 /* always set to 0x5 */
482#define _DPIO_REFSFR_B 0x8034 490#define _VLV_PLL_DW5_CH1 0x8034
483#define DPIO_REFSFR(pipe) _PIPE(pipe, _DPIO_REFSFR_A, _DPIO_REFSFR_B) 491#define VLV_PLL_DW5(ch) _PIPE(ch, _VLV_PLL_DW5_CH0, _VLV_PLL_DW5_CH1)
484 492
485#define _DPIO_CORE_CLK_A 0x801c 493#define _VLV_PLL_DW7_CH0 0x801c
486#define _DPIO_CORE_CLK_B 0x803c 494#define _VLV_PLL_DW7_CH1 0x803c
487#define DPIO_CORE_CLK(pipe) _PIPE(pipe, _DPIO_CORE_CLK_A, _DPIO_CORE_CLK_B) 495#define VLV_PLL_DW7(ch) _PIPE(ch, _VLV_PLL_DW7_CH0, _VLV_PLL_DW7_CH1)
488 496
489#define _DPIO_IREF_CTL_A 0x8040 497#define _VLV_PLL_DW8_CH0 0x8040
490#define _DPIO_IREF_CTL_B 0x8060 498#define _VLV_PLL_DW8_CH1 0x8060
491#define DPIO_IREF_CTL(pipe) _PIPE(pipe, _DPIO_IREF_CTL_A, _DPIO_IREF_CTL_B) 499#define VLV_PLL_DW8(ch) _PIPE(ch, _VLV_PLL_DW8_CH0, _VLV_PLL_DW8_CH1)
492 500
493#define DPIO_IREF_BCAST 0xc044 501#define VLV_PLL_DW9_BCAST 0xc044
494#define _DPIO_IREF_A 0x8044 502#define _VLV_PLL_DW9_CH0 0x8044
495#define _DPIO_IREF_B 0x8064 503#define _VLV_PLL_DW9_CH1 0x8064
496#define DPIO_IREF(pipe) _PIPE(pipe, _DPIO_IREF_A, _DPIO_IREF_B) 504#define VLV_PLL_DW9(ch) _PIPE(ch, _VLV_PLL_DW9_CH0, _VLV_PLL_DW9_CH1)
497 505
498#define _DPIO_PLL_CML_A 0x804c 506#define _VLV_PLL_DW10_CH0 0x8048
499#define _DPIO_PLL_CML_B 0x806c 507#define _VLV_PLL_DW10_CH1 0x8068
500#define DPIO_PLL_CML(pipe) _PIPE(pipe, _DPIO_PLL_CML_A, _DPIO_PLL_CML_B) 508#define VLV_PLL_DW10(ch) _PIPE(ch, _VLV_PLL_DW10_CH0, _VLV_PLL_DW10_CH1)
501 509
502#define _DPIO_LPF_COEFF_A 0x8048 510#define _VLV_PLL_DW11_CH0 0x804c
503#define _DPIO_LPF_COEFF_B 0x8068 511#define _VLV_PLL_DW11_CH1 0x806c
504#define DPIO_LPF_COEFF(pipe) _PIPE(pipe, _DPIO_LPF_COEFF_A, _DPIO_LPF_COEFF_B) 512#define VLV_PLL_DW11(ch) _PIPE(ch, _VLV_PLL_DW11_CH0, _VLV_PLL_DW11_CH1)
505 513
506#define DPIO_CALIBRATION 0x80ac 514/* Spec for ref block start counts at DW10 */
515#define VLV_REF_DW13 0x80ac
507 516
508#define DPIO_FASTCLK_DISABLE 0x8100 517#define VLV_CMN_DW0 0x8100
509 518
510/* 519/*
511 * Per DDI channel DPIO regs 520 * Per DDI channel DPIO regs
512 */ 521 */
513 522
514#define _DPIO_PCS_TX_0 0x8200 523#define _VLV_PCS_DW0_CH0 0x8200
515#define _DPIO_PCS_TX_1 0x8400 524#define _VLV_PCS_DW0_CH1 0x8400
516#define DPIO_PCS_TX_LANE2_RESET (1<<16) 525#define DPIO_PCS_TX_LANE2_RESET (1<<16)
517#define DPIO_PCS_TX_LANE1_RESET (1<<7) 526#define DPIO_PCS_TX_LANE1_RESET (1<<7)
518#define DPIO_PCS_TX(port) _PORT(port, _DPIO_PCS_TX_0, _DPIO_PCS_TX_1) 527#define VLV_PCS_DW0(ch) _PORT(ch, _VLV_PCS_DW0_CH0, _VLV_PCS_DW0_CH1)
519 528
520#define _DPIO_PCS_CLK_0 0x8204 529#define _VLV_PCS_DW1_CH0 0x8204
521#define _DPIO_PCS_CLK_1 0x8404 530#define _VLV_PCS_DW1_CH1 0x8404
522#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22) 531#define DPIO_PCS_CLK_CRI_RXEB_EIOS_EN (1<<22)
523#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21) 532#define DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN (1<<21)
524#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6) 533#define DPIO_PCS_CLK_DATAWIDTH_SHIFT (6)
525#define DPIO_PCS_CLK_SOFT_RESET (1<<5) 534#define DPIO_PCS_CLK_SOFT_RESET (1<<5)
526#define DPIO_PCS_CLK(port) _PORT(port, _DPIO_PCS_CLK_0, _DPIO_PCS_CLK_1) 535#define VLV_PCS_DW1(ch) _PORT(ch, _VLV_PCS_DW1_CH0, _VLV_PCS_DW1_CH1)
527 536
528#define _DPIO_PCS_CTL_OVR1_A 0x8224 537#define _VLV_PCS_DW8_CH0 0x8220
529#define _DPIO_PCS_CTL_OVR1_B 0x8424 538#define _VLV_PCS_DW8_CH1 0x8420
530#define DPIO_PCS_CTL_OVER1(port) _PORT(port, _DPIO_PCS_CTL_OVR1_A, \ 539#define VLV_PCS_DW8(ch) _PORT(ch, _VLV_PCS_DW8_CH0, _VLV_PCS_DW8_CH1)
531 _DPIO_PCS_CTL_OVR1_B) 540
532 541#define _VLV_PCS01_DW8_CH0 0x0220
533#define _DPIO_PCS_STAGGER0_A 0x822c 542#define _VLV_PCS23_DW8_CH0 0x0420
534#define _DPIO_PCS_STAGGER0_B 0x842c 543#define _VLV_PCS01_DW8_CH1 0x2620
535#define DPIO_PCS_STAGGER0(port) _PORT(port, _DPIO_PCS_STAGGER0_A, \ 544#define _VLV_PCS23_DW8_CH1 0x2820
536 _DPIO_PCS_STAGGER0_B) 545#define VLV_PCS01_DW8(port) _PORT(port, _VLV_PCS01_DW8_CH0, _VLV_PCS01_DW8_CH1)
537 546#define VLV_PCS23_DW8(port) _PORT(port, _VLV_PCS23_DW8_CH0, _VLV_PCS23_DW8_CH1)
538#define _DPIO_PCS_STAGGER1_A 0x8230 547
539#define _DPIO_PCS_STAGGER1_B 0x8430 548#define _VLV_PCS_DW9_CH0 0x8224
540#define DPIO_PCS_STAGGER1(port) _PORT(port, _DPIO_PCS_STAGGER1_A, \ 549#define _VLV_PCS_DW9_CH1 0x8424
541 _DPIO_PCS_STAGGER1_B) 550#define VLV_PCS_DW9(ch) _PORT(ch, _VLV_PCS_DW9_CH0, _VLV_PCS_DW9_CH1)
542 551
543#define _DPIO_PCS_CLOCKBUF0_A 0x8238 552#define _VLV_PCS_DW11_CH0 0x822c
544#define _DPIO_PCS_CLOCKBUF0_B 0x8438 553#define _VLV_PCS_DW11_CH1 0x842c
545#define DPIO_PCS_CLOCKBUF0(port) _PORT(port, _DPIO_PCS_CLOCKBUF0_A, \ 554#define VLV_PCS_DW11(ch) _PORT(ch, _VLV_PCS_DW11_CH0, _VLV_PCS_DW11_CH1)
546 _DPIO_PCS_CLOCKBUF0_B) 555
547 556#define _VLV_PCS_DW12_CH0 0x8230
548#define _DPIO_PCS_CLOCKBUF8_A 0x825c 557#define _VLV_PCS_DW12_CH1 0x8430
549#define _DPIO_PCS_CLOCKBUF8_B 0x845c 558#define VLV_PCS_DW12(ch) _PORT(ch, _VLV_PCS_DW12_CH0, _VLV_PCS_DW12_CH1)
550#define DPIO_PCS_CLOCKBUF8(port) _PORT(port, _DPIO_PCS_CLOCKBUF8_A, \ 559
551 _DPIO_PCS_CLOCKBUF8_B) 560#define _VLV_PCS_DW14_CH0 0x8238
552 561#define _VLV_PCS_DW14_CH1 0x8438
553#define _DPIO_TX_SWING_CTL2_A 0x8288 562#define VLV_PCS_DW14(ch) _PORT(ch, _VLV_PCS_DW14_CH0, _VLV_PCS_DW14_CH1)
554#define _DPIO_TX_SWING_CTL2_B 0x8488 563
555#define DPIO_TX_SWING_CTL2(port) _PORT(port, _DPIO_TX_SWING_CTL2_A, \ 564#define _VLV_PCS_DW23_CH0 0x825c
556 _DPIO_TX_SWING_CTL2_B) 565#define _VLV_PCS_DW23_CH1 0x845c
557 566#define VLV_PCS_DW23(ch) _PORT(ch, _VLV_PCS_DW23_CH0, _VLV_PCS_DW23_CH1)
558#define _DPIO_TX_SWING_CTL3_A 0x828c 567
559#define _DPIO_TX_SWING_CTL3_B 0x848c 568#define _VLV_TX_DW2_CH0 0x8288
560#define DPIO_TX_SWING_CTL3(port) _PORT(port, _DPIO_TX_SWING_CTL3_A, \ 569#define _VLV_TX_DW2_CH1 0x8488
561 _DPIO_TX_SWING_CTL3_B) 570#define VLV_TX_DW2(ch) _PORT(ch, _VLV_TX_DW2_CH0, _VLV_TX_DW2_CH1)
562 571
563#define _DPIO_TX_SWING_CTL4_A 0x8290 572#define _VLV_TX_DW3_CH0 0x828c
564#define _DPIO_TX_SWING_CTL4_B 0x8490 573#define _VLV_TX_DW3_CH1 0x848c
565#define DPIO_TX_SWING_CTL4(port) _PORT(port, _DPIO_TX_SWING_CTL4_A, \ 574#define VLV_TX_DW3(ch) _PORT(ch, _VLV_TX_DW3_CH0, _VLV_TX_DW3_CH1)
566 _DPIO_TX_SWING_CTL4_B) 575
567 576#define _VLV_TX_DW4_CH0 0x8290
568#define _DPIO_TX_OCALINIT_0 0x8294 577#define _VLV_TX_DW4_CH1 0x8490
569#define _DPIO_TX_OCALINIT_1 0x8494 578#define VLV_TX_DW4(ch) _PORT(ch, _VLV_TX_DW4_CH0, _VLV_TX_DW4_CH1)
579
580#define _VLV_TX3_DW4_CH0 0x690
581#define _VLV_TX3_DW4_CH1 0x2a90
582#define VLV_TX3_DW4(ch) _PORT(ch, _VLV_TX3_DW4_CH0, _VLV_TX3_DW4_CH1)
583
584#define _VLV_TX_DW5_CH0 0x8294
585#define _VLV_TX_DW5_CH1 0x8494
570#define DPIO_TX_OCALINIT_EN (1<<31) 586#define DPIO_TX_OCALINIT_EN (1<<31)
571#define DPIO_TX_OCALINIT(port) _PORT(port, _DPIO_TX_OCALINIT_0, \ 587#define VLV_TX_DW5(ch) _PORT(ch, _VLV_TX_DW5_CH0, _VLV_TX_DW5_CH1)
572 _DPIO_TX_OCALINIT_1) 588
573 589#define _VLV_TX_DW11_CH0 0x82ac
574#define _DPIO_TX_CTL_0 0x82ac 590#define _VLV_TX_DW11_CH1 0x84ac
575#define _DPIO_TX_CTL_1 0x84ac 591#define VLV_TX_DW11(ch) _PORT(ch, _VLV_TX_DW11_CH0, _VLV_TX_DW11_CH1)
576#define DPIO_TX_CTL(port) _PORT(port, _DPIO_TX_CTL_0, _DPIO_TX_CTL_1) 592
577 593#define _VLV_TX_DW14_CH0 0x82b8
578#define _DPIO_TX_LANE_0 0x82b8 594#define _VLV_TX_DW14_CH1 0x84b8
579#define _DPIO_TX_LANE_1 0x84b8 595#define VLV_TX_DW14(ch) _PORT(ch, _VLV_TX_DW14_CH0, _VLV_TX_DW14_CH1)
580#define DPIO_TX_LANE(port) _PORT(port, _DPIO_TX_LANE_0, _DPIO_TX_LANE_1)
581
582#define _DPIO_DATA_CHANNEL1 0x8220
583#define _DPIO_DATA_CHANNEL2 0x8420
584#define DPIO_DATA_CHANNEL(port) _PORT(port, _DPIO_DATA_CHANNEL1, _DPIO_DATA_CHANNEL2)
585
586#define _DPIO_PORT0_PCS0 0x0220
587#define _DPIO_PORT0_PCS1 0x0420
588#define _DPIO_PORT1_PCS2 0x2620
589#define _DPIO_PORT1_PCS3 0x2820
590#define DPIO_DATA_LANE_A(port) _PORT(port, _DPIO_PORT0_PCS0, _DPIO_PORT1_PCS2)
591#define DPIO_DATA_LANE_B(port) _PORT(port, _DPIO_PORT0_PCS1, _DPIO_PORT1_PCS3)
592#define DPIO_DATA_CHANNEL1 0x8220
593#define DPIO_DATA_CHANNEL2 0x8420
594 596
595/* 597/*
596 * Fence registers 598 * Fence registers
@@ -2130,6 +2132,10 @@
2130#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8) 2132#define CRT_HOTPLUG_MONITOR_COLOR (3 << 8)
2131#define CRT_HOTPLUG_MONITOR_MONO (2 << 8) 2133#define CRT_HOTPLUG_MONITOR_MONO (2 << 8)
2132#define CRT_HOTPLUG_MONITOR_NONE (0 << 8) 2134#define CRT_HOTPLUG_MONITOR_NONE (0 << 8)
2135#define DP_AUX_CHANNEL_D_INT_STATUS_G4X (1 << 6)
2136#define DP_AUX_CHANNEL_C_INT_STATUS_G4X (1 << 5)
2137#define DP_AUX_CHANNEL_B_INT_STATUS_G4X (1 << 4)
2138#define DP_AUX_CHANNEL_MASK_INT_STATUS_G4X (1 << 4)
2133/* SDVO is different across gen3/4 */ 2139/* SDVO is different across gen3/4 */
2134#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3) 2140#define SDVOC_HOTPLUG_INT_STATUS_G4X (1 << 3)
2135#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2) 2141#define SDVOB_HOTPLUG_INT_STATUS_G4X (1 << 2)
@@ -3787,7 +3793,7 @@
3787 3793
3788#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180) 3794#define _SPACNTR (VLV_DISPLAY_BASE + 0x72180)
3789#define SP_ENABLE (1<<31) 3795#define SP_ENABLE (1<<31)
3790#define SP_GEAMMA_ENABLE (1<<30) 3796#define SP_GAMMA_ENABLE (1<<30)
3791#define SP_PIXFORMAT_MASK (0xf<<26) 3797#define SP_PIXFORMAT_MASK (0xf<<26)
3792#define SP_FORMAT_YUV422 (0<<26) 3798#define SP_FORMAT_YUV422 (0<<26)
3793#define SP_FORMAT_BGR565 (5<<26) 3799#define SP_FORMAT_BGR565 (5<<26)
@@ -4851,12 +4857,16 @@
4851#define FORCEWAKE_MT_ENABLE (1<<5) 4857#define FORCEWAKE_MT_ENABLE (1<<5)
4852 4858
4853#define GTFIFODBG 0x120000 4859#define GTFIFODBG 0x120000
4854#define GT_FIFO_CPU_ERROR_MASK 7 4860#define GT_FIFO_SBDROPERR (1<<6)
4861#define GT_FIFO_BLOBDROPERR (1<<5)
4862#define GT_FIFO_SB_READ_ABORTERR (1<<4)
4863#define GT_FIFO_DROPERR (1<<3)
4855#define GT_FIFO_OVFERR (1<<2) 4864#define GT_FIFO_OVFERR (1<<2)
4856#define GT_FIFO_IAWRERR (1<<1) 4865#define GT_FIFO_IAWRERR (1<<1)
4857#define GT_FIFO_IARDERR (1<<0) 4866#define GT_FIFO_IARDERR (1<<0)
4858 4867
4859#define GT_FIFO_FREE_ENTRIES 0x120008 4868#define GTFIFOCTL 0x120008
4869#define GT_FIFO_FREE_ENTRIES_MASK 0x7f
4860#define GT_FIFO_NUM_RESERVED_ENTRIES 20 4870#define GT_FIFO_NUM_RESERVED_ENTRIES 20
4861 4871
4862#define HSW_IDICR 0x9008 4872#define HSW_IDICR 0x9008
@@ -4890,6 +4900,7 @@
4890#define GEN6_RC_CTL_RC6_ENABLE (1<<18) 4900#define GEN6_RC_CTL_RC6_ENABLE (1<<18)
4891#define GEN6_RC_CTL_RC1e_ENABLE (1<<20) 4901#define GEN6_RC_CTL_RC1e_ENABLE (1<<20)
4892#define GEN6_RC_CTL_RC7_ENABLE (1<<22) 4902#define GEN6_RC_CTL_RC7_ENABLE (1<<22)
4903#define VLV_RC_CTL_CTX_RST_PARALLEL (1<<24)
4893#define GEN7_RC_CTL_TO_MODE (1<<28) 4904#define GEN7_RC_CTL_TO_MODE (1<<28)
4894#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27) 4905#define GEN6_RC_CTL_EI_MODE(x) ((x)<<27)
4895#define GEN6_RC_CTL_HW_ENABLE (1<<31) 4906#define GEN6_RC_CTL_HW_ENABLE (1<<31)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 98790c7cccb1..6b8fef7fb3bb 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -192,7 +192,6 @@ static void i915_restore_vga(struct drm_device *dev)
192static void i915_save_display(struct drm_device *dev) 192static void i915_save_display(struct drm_device *dev)
193{ 193{
194 struct drm_i915_private *dev_priv = dev->dev_private; 194 struct drm_i915_private *dev_priv = dev->dev_private;
195 unsigned long flags;
196 195
197 /* Display arbitration control */ 196 /* Display arbitration control */
198 if (INTEL_INFO(dev)->gen <= 4) 197 if (INTEL_INFO(dev)->gen <= 4)
@@ -203,46 +202,27 @@ static void i915_save_display(struct drm_device *dev)
203 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 202 if (!drm_core_check_feature(dev, DRIVER_MODESET))
204 i915_save_display_reg(dev); 203 i915_save_display_reg(dev);
205 204
206 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
207
208 /* LVDS state */ 205 /* LVDS state */
209 if (HAS_PCH_SPLIT(dev)) { 206 if (HAS_PCH_SPLIT(dev)) {
210 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL); 207 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
211 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
212 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
213 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
214 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
215 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) 208 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
216 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); 209 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
217 } else if (IS_VALLEYVIEW(dev)) { 210 } else if (IS_VALLEYVIEW(dev)) {
218 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); 211 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
219 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 212 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
220 213
221 dev_priv->regfile.saveBLC_PWM_CTL =
222 I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
223 dev_priv->regfile.saveBLC_HIST_CTL = 214 dev_priv->regfile.saveBLC_HIST_CTL =
224 I915_READ(VLV_BLC_HIST_CTL(PIPE_A)); 215 I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
225 dev_priv->regfile.saveBLC_PWM_CTL2 =
226 I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
227 dev_priv->regfile.saveBLC_PWM_CTL_B =
228 I915_READ(VLV_BLC_PWM_CTL(PIPE_B));
229 dev_priv->regfile.saveBLC_HIST_CTL_B = 216 dev_priv->regfile.saveBLC_HIST_CTL_B =
230 I915_READ(VLV_BLC_HIST_CTL(PIPE_B)); 217 I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
231 dev_priv->regfile.saveBLC_PWM_CTL2_B =
232 I915_READ(VLV_BLC_PWM_CTL2(PIPE_B));
233 } else { 218 } else {
234 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL); 219 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
235 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS); 220 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
236 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
237 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL); 221 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
238 if (INTEL_INFO(dev)->gen >= 4)
239 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
240 if (IS_MOBILE(dev) && !IS_I830(dev)) 222 if (IS_MOBILE(dev) && !IS_I830(dev))
241 dev_priv->regfile.saveLVDS = I915_READ(LVDS); 223 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
242 } 224 }
243 225
244 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
245
246 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) 226 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
247 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL); 227 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
248 228
@@ -278,7 +258,6 @@ static void i915_restore_display(struct drm_device *dev)
278{ 258{
279 struct drm_i915_private *dev_priv = dev->dev_private; 259 struct drm_i915_private *dev_priv = dev->dev_private;
280 u32 mask = 0xffffffff; 260 u32 mask = 0xffffffff;
281 unsigned long flags;
282 261
283 /* Display arbitration */ 262 /* Display arbitration */
284 if (INTEL_INFO(dev)->gen <= 4) 263 if (INTEL_INFO(dev)->gen <= 4)
@@ -287,12 +266,6 @@ static void i915_restore_display(struct drm_device *dev)
287 if (!drm_core_check_feature(dev, DRIVER_MODESET)) 266 if (!drm_core_check_feature(dev, DRIVER_MODESET))
288 i915_restore_display_reg(dev); 267 i915_restore_display_reg(dev);
289 268
290 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
291
292 /* LVDS state */
293 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
294 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
295
296 if (drm_core_check_feature(dev, DRIVER_MODESET)) 269 if (drm_core_check_feature(dev, DRIVER_MODESET))
297 mask = ~LVDS_PORT_EN; 270 mask = ~LVDS_PORT_EN;
298 271
@@ -305,13 +278,6 @@ static void i915_restore_display(struct drm_device *dev)
305 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL); 278 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
306 279
307 if (HAS_PCH_SPLIT(dev)) { 280 if (HAS_PCH_SPLIT(dev)) {
308 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
309 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
310 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
311 * otherwise we get blank eDP screen after S3 on some machines
312 */
313 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
314 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
315 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); 281 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
316 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); 282 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
317 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); 283 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
@@ -319,21 +285,12 @@ static void i915_restore_display(struct drm_device *dev)
319 I915_WRITE(RSTDBYCTL, 285 I915_WRITE(RSTDBYCTL,
320 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY); 286 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
321 } else if (IS_VALLEYVIEW(dev)) { 287 } else if (IS_VALLEYVIEW(dev)) {
322 I915_WRITE(VLV_BLC_PWM_CTL(PIPE_A),
323 dev_priv->regfile.saveBLC_PWM_CTL);
324 I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A), 288 I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
325 dev_priv->regfile.saveBLC_HIST_CTL); 289 dev_priv->regfile.saveBLC_HIST_CTL);
326 I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_A),
327 dev_priv->regfile.saveBLC_PWM_CTL2);
328 I915_WRITE(VLV_BLC_PWM_CTL(PIPE_B),
329 dev_priv->regfile.saveBLC_PWM_CTL);
330 I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B), 290 I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
331 dev_priv->regfile.saveBLC_HIST_CTL); 291 dev_priv->regfile.saveBLC_HIST_CTL);
332 I915_WRITE(VLV_BLC_PWM_CTL2(PIPE_B),
333 dev_priv->regfile.saveBLC_PWM_CTL2);
334 } else { 292 } else {
335 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS); 293 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
336 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
337 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL); 294 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
338 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); 295 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
339 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); 296 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
@@ -341,8 +298,6 @@ static void i915_restore_display(struct drm_device *dev)
341 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL); 298 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
342 } 299 }
343 300
344 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
345
346 /* only restore FBC info on the platform that supports FBC*/ 301 /* only restore FBC info on the platform that supports FBC*/
347 intel_disable_fbc(dev); 302 intel_disable_fbc(dev);
348 if (I915_HAS_FBC(dev)) { 303 if (I915_HAS_FBC(dev)) {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index cef38fd320a7..05d8b1680c22 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -183,13 +183,13 @@ i915_l3_write(struct file *filp, struct kobject *kobj,
183 int slice = (int)(uintptr_t)attr->private; 183 int slice = (int)(uintptr_t)attr->private;
184 int ret; 184 int ret;
185 185
186 if (!HAS_HW_CONTEXTS(drm_dev))
187 return -ENXIO;
188
186 ret = l3_access_valid(drm_dev, offset); 189 ret = l3_access_valid(drm_dev, offset);
187 if (ret) 190 if (ret)
188 return ret; 191 return ret;
189 192
190 if (dev_priv->hw_contexts_disabled)
191 return -ENXIO;
192
193 ret = i915_mutex_lock_interruptible(drm_dev); 193 ret = i915_mutex_lock_interruptible(drm_dev);
194 if (ret) 194 if (ret)
195 return ret; 195 return ret;
@@ -259,7 +259,7 @@ static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
259 if (IS_VALLEYVIEW(dev_priv->dev)) { 259 if (IS_VALLEYVIEW(dev_priv->dev)) {
260 u32 freq; 260 u32 freq;
261 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 261 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
262 ret = vlv_gpu_freq(dev_priv->mem_freq, (freq >> 8) & 0xff); 262 ret = vlv_gpu_freq(dev_priv, (freq >> 8) & 0xff);
263 } else { 263 } else {
264 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER; 264 ret = dev_priv->rps.cur_delay * GT_FREQUENCY_MULTIPLIER;
265 } 265 }
@@ -276,8 +276,7 @@ static ssize_t vlv_rpe_freq_mhz_show(struct device *kdev,
276 struct drm_i915_private *dev_priv = dev->dev_private; 276 struct drm_i915_private *dev_priv = dev->dev_private;
277 277
278 return snprintf(buf, PAGE_SIZE, "%d\n", 278 return snprintf(buf, PAGE_SIZE, "%d\n",
279 vlv_gpu_freq(dev_priv->mem_freq, 279 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay));
280 dev_priv->rps.rpe_delay));
281} 280}
282 281
283static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf) 282static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute *attr, char *buf)
@@ -291,7 +290,7 @@ static ssize_t gt_max_freq_mhz_show(struct device *kdev, struct device_attribute
291 290
292 mutex_lock(&dev_priv->rps.hw_lock); 291 mutex_lock(&dev_priv->rps.hw_lock);
293 if (IS_VALLEYVIEW(dev_priv->dev)) 292 if (IS_VALLEYVIEW(dev_priv->dev))
294 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.max_delay); 293 ret = vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay);
295 else 294 else
296 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER; 295 ret = dev_priv->rps.max_delay * GT_FREQUENCY_MULTIPLIER;
297 mutex_unlock(&dev_priv->rps.hw_lock); 296 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -318,7 +317,7 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
318 mutex_lock(&dev_priv->rps.hw_lock); 317 mutex_lock(&dev_priv->rps.hw_lock);
319 318
320 if (IS_VALLEYVIEW(dev_priv->dev)) { 319 if (IS_VALLEYVIEW(dev_priv->dev)) {
321 val = vlv_freq_opcode(dev_priv->mem_freq, val); 320 val = vlv_freq_opcode(dev_priv, val);
322 321
323 hw_max = valleyview_rps_max_freq(dev_priv); 322 hw_max = valleyview_rps_max_freq(dev_priv);
324 hw_min = valleyview_rps_min_freq(dev_priv); 323 hw_min = valleyview_rps_min_freq(dev_priv);
@@ -342,15 +341,15 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
342 DRM_DEBUG("User requested overclocking to %d\n", 341 DRM_DEBUG("User requested overclocking to %d\n",
343 val * GT_FREQUENCY_MULTIPLIER); 342 val * GT_FREQUENCY_MULTIPLIER);
344 343
344 dev_priv->rps.max_delay = val;
345
345 if (dev_priv->rps.cur_delay > val) { 346 if (dev_priv->rps.cur_delay > val) {
346 if (IS_VALLEYVIEW(dev_priv->dev)) 347 if (IS_VALLEYVIEW(dev))
347 valleyview_set_rps(dev_priv->dev, val); 348 valleyview_set_rps(dev, val);
348 else 349 else
349 gen6_set_rps(dev_priv->dev, val); 350 gen6_set_rps(dev, val);
350 } 351 }
351 352
352 dev_priv->rps.max_delay = val;
353
354 mutex_unlock(&dev_priv->rps.hw_lock); 353 mutex_unlock(&dev_priv->rps.hw_lock);
355 354
356 return count; 355 return count;
@@ -367,7 +366,7 @@ static ssize_t gt_min_freq_mhz_show(struct device *kdev, struct device_attribute
367 366
368 mutex_lock(&dev_priv->rps.hw_lock); 367 mutex_lock(&dev_priv->rps.hw_lock);
369 if (IS_VALLEYVIEW(dev_priv->dev)) 368 if (IS_VALLEYVIEW(dev_priv->dev))
370 ret = vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.min_delay); 369 ret = vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay);
371 else 370 else
372 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER; 371 ret = dev_priv->rps.min_delay * GT_FREQUENCY_MULTIPLIER;
373 mutex_unlock(&dev_priv->rps.hw_lock); 372 mutex_unlock(&dev_priv->rps.hw_lock);
@@ -394,7 +393,7 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
394 mutex_lock(&dev_priv->rps.hw_lock); 393 mutex_lock(&dev_priv->rps.hw_lock);
395 394
396 if (IS_VALLEYVIEW(dev)) { 395 if (IS_VALLEYVIEW(dev)) {
397 val = vlv_freq_opcode(dev_priv->mem_freq, val); 396 val = vlv_freq_opcode(dev_priv, val);
398 397
399 hw_max = valleyview_rps_max_freq(dev_priv); 398 hw_max = valleyview_rps_max_freq(dev_priv);
400 hw_min = valleyview_rps_min_freq(dev_priv); 399 hw_min = valleyview_rps_min_freq(dev_priv);
@@ -411,15 +410,15 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
411 return -EINVAL; 410 return -EINVAL;
412 } 411 }
413 412
413 dev_priv->rps.min_delay = val;
414
414 if (dev_priv->rps.cur_delay < val) { 415 if (dev_priv->rps.cur_delay < val) {
415 if (IS_VALLEYVIEW(dev)) 416 if (IS_VALLEYVIEW(dev))
416 valleyview_set_rps(dev, val); 417 valleyview_set_rps(dev, val);
417 else 418 else
418 gen6_set_rps(dev_priv->dev, val); 419 gen6_set_rps(dev, val);
419 } 420 }
420 421
421 dev_priv->rps.min_delay = val;
422
423 mutex_unlock(&dev_priv->rps.hw_lock); 422 mutex_unlock(&dev_priv->rps.hw_lock);
424 423
425 return count; 424 return count;
diff --git a/drivers/gpu/drm/i915/i915_ums.c b/drivers/gpu/drm/i915/i915_ums.c
index 967da4772c44..caa18e855815 100644
--- a/drivers/gpu/drm/i915/i915_ums.c
+++ b/drivers/gpu/drm/i915/i915_ums.c
@@ -270,6 +270,18 @@ void i915_save_display_reg(struct drm_device *dev)
270 } 270 }
271 /* FIXME: regfile.save TV & SDVO state */ 271 /* FIXME: regfile.save TV & SDVO state */
272 272
273 /* Backlight */
274 if (HAS_PCH_SPLIT(dev)) {
275 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
276 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
277 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
278 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
279 } else {
280 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
281 if (INTEL_INFO(dev)->gen >= 4)
282 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
283 }
284
273 return; 285 return;
274} 286}
275 287
@@ -280,6 +292,21 @@ void i915_restore_display_reg(struct drm_device *dev)
280 int dpll_b_reg, fpb0_reg, fpb1_reg; 292 int dpll_b_reg, fpb0_reg, fpb1_reg;
281 int i; 293 int i;
282 294
295 /* Backlight */
296 if (HAS_PCH_SPLIT(dev)) {
297 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
298 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
299 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
300 * otherwise we get blank eDP screen after S3 on some machines
301 */
302 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
303 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
304 } else {
305 if (INTEL_INFO(dev)->gen >= 4)
306 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
307 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
308 }
309
283 /* Display port ratios (must be done before clock is set) */ 310 /* Display port ratios (must be done before clock is set) */
284 if (SUPPORTS_INTEGRATED_DP(dev)) { 311 if (SUPPORTS_INTEGRATED_DP(dev)) {
285 I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M); 312 I915_WRITE(_PIPEA_DATA_M_G4X, dev_priv->regfile.savePIPEA_GMCH_DATA_M);
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index b5b1b9b23adf..e2e39e65f109 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -222,8 +222,9 @@ static void intel_crt_dpms(struct drm_connector *connector, int mode)
222 intel_modeset_check_state(connector->dev); 222 intel_modeset_check_state(connector->dev);
223} 223}
224 224
225static int intel_crt_mode_valid(struct drm_connector *connector, 225static enum drm_mode_status
226 struct drm_display_mode *mode) 226intel_crt_mode_valid(struct drm_connector *connector,
227 struct drm_display_mode *mode)
227{ 228{
228 struct drm_device *dev = connector->dev; 229 struct drm_device *dev = connector->dev;
229 230
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 526c8ded16b0..c8382f55870c 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -713,8 +713,6 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
713 uint32_t reg, val; 713 uint32_t reg, val;
714 int clock = intel_crtc->config.port_clock; 714 int clock = intel_crtc->config.port_clock;
715 715
716 /* TODO: reuse PLLs when possible (compare values) */
717
718 intel_ddi_put_crtc_pll(crtc); 716 intel_ddi_put_crtc_pll(crtc);
719 717
720 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { 718 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
@@ -742,31 +740,40 @@ bool intel_ddi_pll_mode_set(struct drm_crtc *crtc)
742 } else if (type == INTEL_OUTPUT_HDMI) { 740 } else if (type == INTEL_OUTPUT_HDMI) {
743 unsigned p, n2, r2; 741 unsigned p, n2, r2;
744 742
745 if (plls->wrpll1_refcount == 0) { 743 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
744
745 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 |
746 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
747 WRPLL_DIVIDER_POST(p);
748
749 if (val == I915_READ(WRPLL_CTL1)) {
750 DRM_DEBUG_KMS("Reusing WRPLL 1 on pipe %c\n",
751 pipe_name(pipe));
752 reg = WRPLL_CTL1;
753 } else if (val == I915_READ(WRPLL_CTL2)) {
754 DRM_DEBUG_KMS("Reusing WRPLL 2 on pipe %c\n",
755 pipe_name(pipe));
756 reg = WRPLL_CTL2;
757 } else if (plls->wrpll1_refcount == 0) {
746 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n", 758 DRM_DEBUG_KMS("Using WRPLL 1 on pipe %c\n",
747 pipe_name(pipe)); 759 pipe_name(pipe));
748 plls->wrpll1_refcount++;
749 reg = WRPLL_CTL1; 760 reg = WRPLL_CTL1;
750 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
751 } else if (plls->wrpll2_refcount == 0) { 761 } else if (plls->wrpll2_refcount == 0) {
752 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n", 762 DRM_DEBUG_KMS("Using WRPLL 2 on pipe %c\n",
753 pipe_name(pipe)); 763 pipe_name(pipe));
754 plls->wrpll2_refcount++;
755 reg = WRPLL_CTL2; 764 reg = WRPLL_CTL2;
756 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
757 } else { 765 } else {
758 DRM_ERROR("No WRPLLs available!\n"); 766 DRM_ERROR("No WRPLLs available!\n");
759 return false; 767 return false;
760 } 768 }
761 769
762 WARN(I915_READ(reg) & WRPLL_PLL_ENABLE, 770 if (reg == WRPLL_CTL1) {
763 "WRPLL already enabled\n"); 771 plls->wrpll1_refcount++;
764 772 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL1;
765 intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); 773 } else {
766 774 plls->wrpll2_refcount++;
767 val = WRPLL_PLL_ENABLE | WRPLL_PLL_SELECT_LCPLL_2700 | 775 intel_crtc->ddi_pll_sel = PORT_CLK_SEL_WRPLL2;
768 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | 776 }
769 WRPLL_DIVIDER_POST(p);
770 777
771 } else if (type == INTEL_OUTPUT_ANALOG) { 778 } else if (type == INTEL_OUTPUT_ANALOG) {
772 if (plls->spll_refcount == 0) { 779 if (plls->spll_refcount == 0) {
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 080f6fd4e839..0bb3d6d596d9 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -748,10 +748,10 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
748 return intel_crtc->config.cpu_transcoder; 748 return intel_crtc->config.cpu_transcoder;
749} 749}
750 750
751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe) 751static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
752{ 752{
753 struct drm_i915_private *dev_priv = dev->dev_private; 753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe); 754 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
755 755
756 frame = I915_READ(frame_reg); 756 frame = I915_READ(frame_reg);
757 757
@@ -772,8 +772,8 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
772 struct drm_i915_private *dev_priv = dev->dev_private; 772 struct drm_i915_private *dev_priv = dev->dev_private;
773 int pipestat_reg = PIPESTAT(pipe); 773 int pipestat_reg = PIPESTAT(pipe);
774 774
775 if (INTEL_INFO(dev)->gen >= 5) { 775 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe); 776 g4x_wait_for_vblank(dev, pipe);
777 return; 777 return;
778 } 778 }
779 779
@@ -1361,6 +1361,7 @@ static void intel_init_dpio(struct drm_device *dev)
1361 if (!IS_VALLEYVIEW(dev)) 1361 if (!IS_VALLEYVIEW(dev))
1362 return; 1362 return;
1363 1363
1364 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1364 /* 1365 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - 1366 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0. 1367 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
@@ -1494,18 +1495,25 @@ static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1494 POSTING_READ(DPLL(pipe)); 1495 POSTING_READ(DPLL(pipe));
1495} 1496}
1496 1497
1497void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port) 1498void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1499 struct intel_digital_port *dport)
1498{ 1500{
1499 u32 port_mask; 1501 u32 port_mask;
1500 1502
1501 if (!port) 1503 switch (dport->port) {
1504 case PORT_B:
1502 port_mask = DPLL_PORTB_READY_MASK; 1505 port_mask = DPLL_PORTB_READY_MASK;
1503 else 1506 break;
1507 case PORT_C:
1504 port_mask = DPLL_PORTC_READY_MASK; 1508 port_mask = DPLL_PORTC_READY_MASK;
1509 break;
1510 default:
1511 BUG();
1512 }
1505 1513
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000)) 1514 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n", 1515 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0))); 1516 port_name(dport->port), I915_READ(DPLL(0)));
1509} 1517}
1510 1518
1511/** 1519/**
@@ -2233,7 +2241,12 @@ void intel_display_handle_reset(struct drm_device *dev)
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc); 2241 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234 2242
2235 mutex_lock(&crtc->mutex); 2243 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active) 2244 /*
2245 * FIXME: Once we have proper support for primary planes (and
2246 * disabling them without disabling the entire crtc) allow again
2247 * a NULL crtc->fb.
2248 */
2249 if (intel_crtc->active && crtc->fb)
2237 dev_priv->display.update_plane(crtc, crtc->fb, 2250 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y); 2251 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex); 2252 mutex_unlock(&crtc->mutex);
@@ -3910,6 +3923,174 @@ static void i9xx_pfit_enable(struct intel_crtc *crtc)
3910 I915_WRITE(BCLRPAT(crtc->pipe), 0); 3923 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3911} 3924}
3912 3925
3926int valleyview_get_vco(struct drm_i915_private *dev_priv)
3927{
3928 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
3929
3930 /* Obtain SKU information */
3931 mutex_lock(&dev_priv->dpio_lock);
3932 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
3933 CCK_FUSE_HPLL_FREQ_MASK;
3934 mutex_unlock(&dev_priv->dpio_lock);
3935
3936 return vco_freq[hpll_freq];
3937}
3938
3939/* Adjust CDclk dividers to allow high res or save power if possible */
3940static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
3941{
3942 struct drm_i915_private *dev_priv = dev->dev_private;
3943 u32 val, cmd;
3944
3945 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
3946 cmd = 2;
3947 else if (cdclk == 266)
3948 cmd = 1;
3949 else
3950 cmd = 0;
3951
3952 mutex_lock(&dev_priv->rps.hw_lock);
3953 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3954 val &= ~DSPFREQGUAR_MASK;
3955 val |= (cmd << DSPFREQGUAR_SHIFT);
3956 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
3957 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
3958 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
3959 50)) {
3960 DRM_ERROR("timed out waiting for CDclk change\n");
3961 }
3962 mutex_unlock(&dev_priv->rps.hw_lock);
3963
3964 if (cdclk == 400) {
3965 u32 divider, vco;
3966
3967 vco = valleyview_get_vco(dev_priv);
3968 divider = ((vco << 1) / cdclk) - 1;
3969
3970 mutex_lock(&dev_priv->dpio_lock);
3971 /* adjust cdclk divider */
3972 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
3973 val &= ~0xf;
3974 val |= divider;
3975 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
3976 mutex_unlock(&dev_priv->dpio_lock);
3977 }
3978
3979 mutex_lock(&dev_priv->dpio_lock);
3980 /* adjust self-refresh exit latency value */
3981 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
3982 val &= ~0x7f;
3983
3984 /*
3985 * For high bandwidth configs, we set a higher latency in the bunit
3986 * so that the core display fetch happens in time to avoid underruns.
3987 */
3988 if (cdclk == 400)
3989 val |= 4500 / 250; /* 4.5 usec */
3990 else
3991 val |= 3000 / 250; /* 3.0 usec */
3992 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
3993 mutex_unlock(&dev_priv->dpio_lock);
3994
3995 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
3996 intel_i2c_reset(dev);
3997}
3998
3999static int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4000{
4001 int cur_cdclk, vco;
4002 int divider;
4003
4004 vco = valleyview_get_vco(dev_priv);
4005
4006 mutex_lock(&dev_priv->dpio_lock);
4007 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4008 mutex_unlock(&dev_priv->dpio_lock);
4009
4010 divider &= 0xf;
4011
4012 cur_cdclk = (vco << 1) / (divider + 1);
4013
4014 return cur_cdclk;
4015}
4016
4017static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4018 int max_pixclk)
4019{
4020 int cur_cdclk;
4021
4022 cur_cdclk = valleyview_cur_cdclk(dev_priv);
4023
4024 /*
4025 * Really only a few cases to deal with, as only 4 CDclks are supported:
4026 * 200MHz
4027 * 267MHz
4028 * 320MHz
4029 * 400MHz
4030 * So we check to see whether we're above 90% of the lower bin and
4031 * adjust if needed.
4032 */
4033 if (max_pixclk > 288000) {
4034 return 400;
4035 } else if (max_pixclk > 240000) {
4036 return 320;
4037 } else
4038 return 266;
4039 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4040}
4041
4042static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv,
4043 unsigned modeset_pipes,
4044 struct intel_crtc_config *pipe_config)
4045{
4046 struct drm_device *dev = dev_priv->dev;
4047 struct intel_crtc *intel_crtc;
4048 int max_pixclk = 0;
4049
4050 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4051 base.head) {
4052 if (modeset_pipes & (1 << intel_crtc->pipe))
4053 max_pixclk = max(max_pixclk,
4054 pipe_config->adjusted_mode.crtc_clock);
4055 else if (intel_crtc->base.enabled)
4056 max_pixclk = max(max_pixclk,
4057 intel_crtc->config.adjusted_mode.crtc_clock);
4058 }
4059
4060 return max_pixclk;
4061}
4062
4063static void valleyview_modeset_global_pipes(struct drm_device *dev,
4064 unsigned *prepare_pipes,
4065 unsigned modeset_pipes,
4066 struct intel_crtc_config *pipe_config)
4067{
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 struct intel_crtc *intel_crtc;
4070 int max_pixclk = intel_mode_max_pixclk(dev_priv, modeset_pipes,
4071 pipe_config);
4072 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4073
4074 if (valleyview_calc_cdclk(dev_priv, max_pixclk) == cur_cdclk)
4075 return;
4076
4077 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
4078 base.head)
4079 if (intel_crtc->base.enabled)
4080 *prepare_pipes |= (1 << intel_crtc->pipe);
4081}
4082
4083static void valleyview_modeset_global_resources(struct drm_device *dev)
4084{
4085 struct drm_i915_private *dev_priv = dev->dev_private;
4086 int max_pixclk = intel_mode_max_pixclk(dev_priv, 0, NULL);
4087 int cur_cdclk = valleyview_cur_cdclk(dev_priv);
4088 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4089
4090 if (req_cdclk != cur_cdclk)
4091 valleyview_set_cdclk(dev, req_cdclk);
4092}
4093
3913static void valleyview_crtc_enable(struct drm_crtc *crtc) 4094static void valleyview_crtc_enable(struct drm_crtc *crtc)
3914{ 4095{
3915 struct drm_device *dev = crtc->dev; 4096 struct drm_device *dev = crtc->dev;
@@ -4634,24 +4815,24 @@ static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4634 * PLLB opamp always calibrates to max value of 0x3f, force enable it 4815 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4635 * and set it to a reasonable value instead. 4816 * and set it to a reasonable value instead.
4636 */ 4817 */
4637 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); 4818 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4638 reg_val &= 0xffffff00; 4819 reg_val &= 0xffffff00;
4639 reg_val |= 0x00000030; 4820 reg_val |= 0x00000030;
4640 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); 4821 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4641 4822
4642 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); 4823 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4643 reg_val &= 0x8cffffff; 4824 reg_val &= 0x8cffffff;
4644 reg_val = 0x8c000000; 4825 reg_val = 0x8c000000;
4645 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); 4826 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4646 4827
4647 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1)); 4828 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
4648 reg_val &= 0xffffff00; 4829 reg_val &= 0xffffff00;
4649 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val); 4830 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
4650 4831
4651 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION); 4832 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
4652 reg_val &= 0x00ffffff; 4833 reg_val &= 0x00ffffff;
4653 reg_val |= 0xb0000000; 4834 reg_val |= 0xb0000000;
4654 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val); 4835 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
4655} 4836}
4656 4837
4657static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, 4838static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
@@ -4720,15 +4901,15 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4720 vlv_pllb_recal_opamp(dev_priv, pipe); 4901 vlv_pllb_recal_opamp(dev_priv, pipe);
4721 4902
4722 /* Set up Tx target for periodic Rcomp update */ 4903 /* Set up Tx target for periodic Rcomp update */
4723 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f); 4904 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
4724 4905
4725 /* Disable target IRef on PLL */ 4906 /* Disable target IRef on PLL */
4726 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe)); 4907 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
4727 reg_val &= 0x00ffffff; 4908 reg_val &= 0x00ffffff;
4728 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val); 4909 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
4729 4910
4730 /* Disable fast lock */ 4911 /* Disable fast lock */
4731 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610); 4912 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
4732 4913
4733 /* Set idtafcrecal before PLL is enabled */ 4914 /* Set idtafcrecal before PLL is enabled */
4734 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 4915 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
@@ -4742,48 +4923,48 @@ static void vlv_update_pll(struct intel_crtc *crtc)
4742 * Note: don't use the DAC post divider as it seems unstable. 4923 * Note: don't use the DAC post divider as it seems unstable.
4743 */ 4924 */
4744 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 4925 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4745 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); 4926 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4746 4927
4747 mdiv |= DPIO_ENABLE_CALIBRATION; 4928 mdiv |= DPIO_ENABLE_CALIBRATION;
4748 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv); 4929 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
4749 4930
4750 /* Set HBR and RBR LPF coefficients */ 4931 /* Set HBR and RBR LPF coefficients */
4751 if (crtc->config.port_clock == 162000 || 4932 if (crtc->config.port_clock == 162000 ||
4752 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || 4933 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4753 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) 4934 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4754 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), 4935 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4755 0x009f0003); 4936 0x009f0003);
4756 else 4937 else
4757 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe), 4938 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
4758 0x00d0000f); 4939 0x00d0000f);
4759 4940
4760 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || 4941 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4761 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { 4942 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4762 /* Use SSC source */ 4943 /* Use SSC source */
4763 if (!pipe) 4944 if (!pipe)
4764 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), 4945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4765 0x0df40000); 4946 0x0df40000);
4766 else 4947 else
4767 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), 4948 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4768 0x0df70000); 4949 0x0df70000);
4769 } else { /* HDMI or VGA */ 4950 } else { /* HDMI or VGA */
4770 /* Use bend source */ 4951 /* Use bend source */
4771 if (!pipe) 4952 if (!pipe)
4772 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), 4953 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4773 0x0df70000); 4954 0x0df70000);
4774 else 4955 else
4775 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe), 4956 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
4776 0x0df40000); 4957 0x0df40000);
4777 } 4958 }
4778 4959
4779 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe)); 4960 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
4780 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 4961 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4781 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || 4962 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4782 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) 4963 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4783 coreclk |= 0x01000000; 4964 coreclk |= 0x01000000;
4784 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk); 4965 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
4785 4966
4786 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000); 4967 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
4787 4968
4788 /* Enable DPIO clock input */ 4969 /* Enable DPIO clock input */
4789 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | 4970 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
@@ -5261,7 +5442,7 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5261 int refclk = 100000; 5442 int refclk = 100000;
5262 5443
5263 mutex_lock(&dev_priv->dpio_lock); 5444 mutex_lock(&dev_priv->dpio_lock);
5264 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe)); 5445 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
5265 mutex_unlock(&dev_priv->dpio_lock); 5446 mutex_unlock(&dev_priv->dpio_lock);
5266 5447
5267 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; 5448 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
@@ -6402,7 +6583,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6402 6583
6403 /* Make sure we're not on PC8 state before disabling PC8, otherwise 6584 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6404 * we'll hang the machine! */ 6585 * we'll hang the machine! */
6405 gen6_gt_force_wake_get(dev_priv); 6586 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
6406 6587
6407 if (val & LCPLL_POWER_DOWN_ALLOW) { 6588 if (val & LCPLL_POWER_DOWN_ALLOW) {
6408 val &= ~LCPLL_POWER_DOWN_ALLOW; 6589 val &= ~LCPLL_POWER_DOWN_ALLOW;
@@ -6436,7 +6617,7 @@ static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6436 DRM_ERROR("Switching back to LCPLL failed\n"); 6617 DRM_ERROR("Switching back to LCPLL failed\n");
6437 } 6618 }
6438 6619
6439 gen6_gt_force_wake_put(dev_priv); 6620 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
6440} 6621}
6441 6622
6442void hsw_enable_pc8_work(struct work_struct *__work) 6623void hsw_enable_pc8_work(struct work_struct *__work)
@@ -9402,6 +9583,21 @@ static int __intel_set_mode(struct drm_crtc *crtc,
9402 "[modeset]"); 9583 "[modeset]");
9403 } 9584 }
9404 9585
9586 /*
9587 * See if the config requires any additional preparation, e.g.
9588 * to adjust global state with pipes off. We need to do this
9589 * here so we can get the modeset_pipe updated config for the new
9590 * mode set on this crtc. For other crtcs we need to use the
9591 * adjusted_mode bits in the crtc directly.
9592 */
9593 if (IS_VALLEYVIEW(dev)) {
9594 valleyview_modeset_global_pipes(dev, &prepare_pipes,
9595 modeset_pipes, pipe_config);
9596
9597 /* may have added more to prepare_pipes than we should */
9598 prepare_pipes &= ~disable_pipes;
9599 }
9600
9405 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) 9601 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9406 intel_crtc_disable(&intel_crtc->base); 9602 intel_crtc_disable(&intel_crtc->base);
9407 9603
@@ -10412,8 +10608,11 @@ static void intel_init_display(struct drm_device *dev)
10412 } 10608 }
10413 } else if (IS_G4X(dev)) { 10609 } else if (IS_G4X(dev)) {
10414 dev_priv->display.write_eld = g4x_write_eld; 10610 dev_priv->display.write_eld = g4x_write_eld;
10415 } else if (IS_VALLEYVIEW(dev)) 10611 } else if (IS_VALLEYVIEW(dev)) {
10612 dev_priv->display.modeset_global_resources =
10613 valleyview_modeset_global_resources;
10416 dev_priv->display.write_eld = ironlake_write_eld; 10614 dev_priv->display.write_eld = ironlake_write_eld;
10615 }
10417 10616
10418 /* Default just returns -ENODEV to indicate unsupported */ 10617 /* Default just returns -ENODEV to indicate unsupported */
10419 dev_priv->display.queue_flip = intel_default_queue_flip; 10618 dev_priv->display.queue_flip = intel_default_queue_flip;
@@ -10440,6 +10639,8 @@ static void intel_init_display(struct drm_device *dev)
10440 dev_priv->display.queue_flip = intel_gen7_queue_flip; 10639 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10441 break; 10640 break;
10442 } 10641 }
10642
10643 intel_panel_init_backlight_funcs(dev);
10443} 10644}
10444 10645
10445/* 10646/*
@@ -10476,17 +10677,6 @@ static void quirk_invert_brightness(struct drm_device *dev)
10476 DRM_INFO("applying inverted panel brightness quirk\n"); 10677 DRM_INFO("applying inverted panel brightness quirk\n");
10477} 10678}
10478 10679
10479/*
10480 * Some machines (Dell XPS13) suffer broken backlight controls if
10481 * BLM_PCH_PWM_ENABLE is set.
10482 */
10483static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10484{
10485 struct drm_i915_private *dev_priv = dev->dev_private;
10486 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10487 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10488}
10489
10490struct intel_quirk { 10680struct intel_quirk {
10491 int device; 10681 int device;
10492 int subsystem_vendor; 10682 int subsystem_vendor;
@@ -10546,11 +10736,6 @@ static struct intel_quirk intel_quirks[] = {
10546 * seem to use inverted backlight PWM. 10736 * seem to use inverted backlight PWM.
10547 */ 10737 */
10548 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness }, 10738 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
10549
10550 /* Dell XPS13 HD Sandy Bridge */
10551 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10552 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10553 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
10554}; 10739};
10555 10740
10556static void intel_init_quirks(struct drm_device *dev) 10741static void intel_init_quirks(struct drm_device *dev)
@@ -10870,7 +11055,7 @@ void i915_redisable_vga(struct drm_device *dev)
10870 * level, just check if the power well is enabled instead of trying to 11055 * level, just check if the power well is enabled instead of trying to
10871 * follow the "don't touch the power well if we don't need it" policy 11056 * follow the "don't touch the power well if we don't need it" policy
10872 * the rest of the driver uses. */ 11057 * the rest of the driver uses. */
10873 if (HAS_POWER_WELL(dev) && 11058 if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) &&
10874 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0) 11059 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
10875 return; 11060 return;
10876 11061
@@ -11091,12 +11276,11 @@ void intel_modeset_cleanup(struct drm_device *dev)
11091 /* flush any delayed tasks or pending work */ 11276 /* flush any delayed tasks or pending work */
11092 flush_scheduled_work(); 11277 flush_scheduled_work();
11093 11278
11094 /* destroy backlight, if any, before the connectors */ 11279 /* destroy the backlight and sysfs files before encoders/connectors */
11095 intel_panel_destroy_backlight(dev); 11280 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11096 11281 intel_panel_destroy_backlight(connector);
11097 /* destroy the sysfs files before encoders/connectors */
11098 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
11099 drm_sysfs_connector_remove(connector); 11282 drm_sysfs_connector_remove(connector);
11283 }
11100 11284
11101 drm_mode_config_cleanup(dev); 11285 drm_mode_config_cleanup(dev);
11102 11286
@@ -11150,6 +11334,7 @@ struct intel_display_error_state {
11150 } cursor[I915_MAX_PIPES]; 11334 } cursor[I915_MAX_PIPES];
11151 11335
11152 struct intel_pipe_error_state { 11336 struct intel_pipe_error_state {
11337 bool power_domain_on;
11153 u32 source; 11338 u32 source;
11154 } pipe[I915_MAX_PIPES]; 11339 } pipe[I915_MAX_PIPES];
11155 11340
@@ -11164,6 +11349,7 @@ struct intel_display_error_state {
11164 } plane[I915_MAX_PIPES]; 11349 } plane[I915_MAX_PIPES];
11165 11350
11166 struct intel_transcoder_error_state { 11351 struct intel_transcoder_error_state {
11352 bool power_domain_on;
11167 enum transcoder cpu_transcoder; 11353 enum transcoder cpu_transcoder;
11168 11354
11169 u32 conf; 11355 u32 conf;
@@ -11197,11 +11383,13 @@ intel_display_capture_error_state(struct drm_device *dev)
11197 if (error == NULL) 11383 if (error == NULL)
11198 return NULL; 11384 return NULL;
11199 11385
11200 if (HAS_POWER_WELL(dev)) 11386 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11201 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); 11387 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11202 11388
11203 for_each_pipe(i) { 11389 for_each_pipe(i) {
11204 if (!intel_display_power_enabled(dev, POWER_DOMAIN_PIPE(i))) 11390 error->pipe[i].power_domain_on =
11391 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11392 if (!error->pipe[i].power_domain_on)
11205 continue; 11393 continue;
11206 11394
11207 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) { 11395 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
@@ -11237,8 +11425,9 @@ intel_display_capture_error_state(struct drm_device *dev)
11237 for (i = 0; i < error->num_transcoders; i++) { 11425 for (i = 0; i < error->num_transcoders; i++) {
11238 enum transcoder cpu_transcoder = transcoders[i]; 11426 enum transcoder cpu_transcoder = transcoders[i];
11239 11427
11240 if (!intel_display_power_enabled(dev, 11428 error->transcoder[i].power_domain_on =
11241 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) 11429 intel_display_power_enabled_sw(dev, POWER_DOMAIN_PIPE(i));
11430 if (!error->transcoder[i].power_domain_on)
11242 continue; 11431 continue;
11243 11432
11244 error->transcoder[i].cpu_transcoder = cpu_transcoder; 11433 error->transcoder[i].cpu_transcoder = cpu_transcoder;
@@ -11268,11 +11457,13 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11268 return; 11457 return;
11269 11458
11270 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); 11459 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
11271 if (HAS_POWER_WELL(dev)) 11460 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
11272 err_printf(m, "PWR_WELL_CTL2: %08x\n", 11461 err_printf(m, "PWR_WELL_CTL2: %08x\n",
11273 error->power_well_driver); 11462 error->power_well_driver);
11274 for_each_pipe(i) { 11463 for_each_pipe(i) {
11275 err_printf(m, "Pipe [%d]:\n", i); 11464 err_printf(m, "Pipe [%d]:\n", i);
11465 err_printf(m, " Power: %s\n",
11466 error->pipe[i].power_domain_on ? "on" : "off");
11276 err_printf(m, " SRC: %08x\n", error->pipe[i].source); 11467 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
11277 11468
11278 err_printf(m, "Plane [%d]:\n", i); 11469 err_printf(m, "Plane [%d]:\n", i);
@@ -11298,6 +11489,8 @@ intel_display_print_error_state(struct drm_i915_error_state_buf *m,
11298 for (i = 0; i < error->num_transcoders; i++) { 11489 for (i = 0; i < error->num_transcoders; i++) {
11299 err_printf(m, "CPU transcoder: %c\n", 11490 err_printf(m, "CPU transcoder: %c\n",
11300 transcoder_name(error->transcoder[i].cpu_transcoder)); 11491 transcoder_name(error->transcoder[i].cpu_transcoder));
11492 err_printf(m, " Power: %s\n",
11493 error->transcoder[i].power_domain_on ? "on" : "off");
11301 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); 11494 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11302 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); 11495 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11303 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); 11496 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 30c627c7b7ba..7c54f6267a1f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -142,7 +142,7 @@ intel_dp_max_data_rate(int max_link_clock, int max_lanes)
142 return (max_link_clock * max_lanes * 8) / 10; 142 return (max_link_clock * max_lanes * 8) / 10;
143} 143}
144 144
145static int 145static enum drm_mode_status
146intel_dp_mode_valid(struct drm_connector *connector, 146intel_dp_mode_valid(struct drm_connector *connector,
147 struct drm_display_mode *mode) 147 struct drm_display_mode *mode)
148{ 148{
@@ -404,7 +404,7 @@ intel_dp_aux_ch(struct intel_dp *intel_dp,
404 int i, ret, recv_bytes; 404 int i, ret, recv_bytes;
405 uint32_t status; 405 uint32_t status;
406 int try, precharge, clock = 0; 406 int try, precharge, clock = 0;
407 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); 407 bool has_aux_irq = true;
408 uint32_t timeout; 408 uint32_t timeout;
409 409
410 /* dp aux is extremely sensitive to irq latency, hence request the 410 /* dp aux is extremely sensitive to irq latency, hence request the
@@ -1845,23 +1845,23 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1845 struct drm_device *dev = encoder->base.dev; 1845 struct drm_device *dev = encoder->base.dev;
1846 struct drm_i915_private *dev_priv = dev->dev_private; 1846 struct drm_i915_private *dev_priv = dev->dev_private;
1847 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); 1847 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
1848 int port = vlv_dport_to_channel(dport); 1848 enum dpio_channel port = vlv_dport_to_channel(dport);
1849 int pipe = intel_crtc->pipe; 1849 int pipe = intel_crtc->pipe;
1850 struct edp_power_seq power_seq; 1850 struct edp_power_seq power_seq;
1851 u32 val; 1851 u32 val;
1852 1852
1853 mutex_lock(&dev_priv->dpio_lock); 1853 mutex_lock(&dev_priv->dpio_lock);
1854 1854
1855 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); 1855 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1856 val = 0; 1856 val = 0;
1857 if (pipe) 1857 if (pipe)
1858 val |= (1<<21); 1858 val |= (1<<21);
1859 else 1859 else
1860 val &= ~(1<<21); 1860 val &= ~(1<<21);
1861 val |= 0x001000c4; 1861 val |= 0x001000c4;
1862 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); 1862 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1863 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 0x00760018); 1863 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1864 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port), 0x00400888); 1864 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1865 1865
1866 mutex_unlock(&dev_priv->dpio_lock); 1866 mutex_unlock(&dev_priv->dpio_lock);
1867 1867
@@ -1872,7 +1872,7 @@ static void vlv_pre_enable_dp(struct intel_encoder *encoder)
1872 1872
1873 intel_enable_dp(encoder); 1873 intel_enable_dp(encoder);
1874 1874
1875 vlv_wait_port_ready(dev_priv, port); 1875 vlv_wait_port_ready(dev_priv, dport);
1876} 1876}
1877 1877
1878static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder) 1878static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
@@ -1882,24 +1882,24 @@ static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
1882 struct drm_i915_private *dev_priv = dev->dev_private; 1882 struct drm_i915_private *dev_priv = dev->dev_private;
1883 struct intel_crtc *intel_crtc = 1883 struct intel_crtc *intel_crtc =
1884 to_intel_crtc(encoder->base.crtc); 1884 to_intel_crtc(encoder->base.crtc);
1885 int port = vlv_dport_to_channel(dport); 1885 enum dpio_channel port = vlv_dport_to_channel(dport);
1886 int pipe = intel_crtc->pipe; 1886 int pipe = intel_crtc->pipe;
1887 1887
1888 /* Program Tx lane resets to default */ 1888 /* Program Tx lane resets to default */
1889 mutex_lock(&dev_priv->dpio_lock); 1889 mutex_lock(&dev_priv->dpio_lock);
1890 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 1890 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1891 DPIO_PCS_TX_LANE2_RESET | 1891 DPIO_PCS_TX_LANE2_RESET |
1892 DPIO_PCS_TX_LANE1_RESET); 1892 DPIO_PCS_TX_LANE1_RESET);
1893 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 1893 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1894 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1894 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1895 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1895 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1896 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1896 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1897 DPIO_PCS_CLK_SOFT_RESET); 1897 DPIO_PCS_CLK_SOFT_RESET);
1898 1898
1899 /* Fix up inter-pair skew failure */ 1899 /* Fix up inter-pair skew failure */
1900 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); 1900 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1901 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); 1901 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1902 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); 1902 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1903 mutex_unlock(&dev_priv->dpio_lock); 1903 mutex_unlock(&dev_priv->dpio_lock);
1904} 1904}
1905 1905
@@ -2050,7 +2050,7 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2050 unsigned long demph_reg_value, preemph_reg_value, 2050 unsigned long demph_reg_value, preemph_reg_value,
2051 uniqtranscale_reg_value; 2051 uniqtranscale_reg_value;
2052 uint8_t train_set = intel_dp->train_set[0]; 2052 uint8_t train_set = intel_dp->train_set[0];
2053 int port = vlv_dport_to_channel(dport); 2053 enum dpio_channel port = vlv_dport_to_channel(dport);
2054 int pipe = intel_crtc->pipe; 2054 int pipe = intel_crtc->pipe;
2055 2055
2056 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 2056 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
@@ -2127,14 +2127,14 @@ static uint32_t intel_vlv_signal_levels(struct intel_dp *intel_dp)
2127 } 2127 }
2128 2128
2129 mutex_lock(&dev_priv->dpio_lock); 2129 mutex_lock(&dev_priv->dpio_lock);
2130 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x00000000); 2130 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
2131 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), demph_reg_value); 2131 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
2132 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), 2132 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
2133 uniqtranscale_reg_value); 2133 uniqtranscale_reg_value);
2134 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 0x0C782040); 2134 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
2135 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000); 2135 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
2136 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), preemph_reg_value); 2136 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
2137 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0x80000000); 2137 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
2138 mutex_unlock(&dev_priv->dpio_lock); 2138 mutex_unlock(&dev_priv->dpio_lock);
2139 2139
2140 return 0; 2140 return 0;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a18e88b3e425..2b5bcb617908 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -156,6 +156,17 @@ struct intel_encoder {
156struct intel_panel { 156struct intel_panel {
157 struct drm_display_mode *fixed_mode; 157 struct drm_display_mode *fixed_mode;
158 int fitting_mode; 158 int fitting_mode;
159
160 /* backlight */
161 struct {
162 bool present;
163 u32 level;
164 u32 max;
165 bool enabled;
166 bool combination_mode; /* gen 2/4 only */
167 bool active_low_pwm;
168 struct backlight_device *device;
169 } backlight;
159}; 170};
160 171
161struct intel_connector { 172struct intel_connector {
@@ -490,9 +501,9 @@ vlv_dport_to_channel(struct intel_digital_port *dport)
490{ 501{
491 switch (dport->port) { 502 switch (dport->port) {
492 case PORT_B: 503 case PORT_B:
493 return 0; 504 return DPIO_CH0;
494 case PORT_C: 505 case PORT_C:
495 return 1; 506 return DPIO_CH1;
496 default: 507 default:
497 BUG(); 508 BUG();
498 } 509 }
@@ -638,7 +649,8 @@ enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
638void intel_wait_for_vblank(struct drm_device *dev, int pipe); 649void intel_wait_for_vblank(struct drm_device *dev, int pipe);
639void intel_wait_for_pipe_off(struct drm_device *dev, int pipe); 650void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
640int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp); 651int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp);
641void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port); 652void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
653 struct intel_digital_port *dport);
642bool intel_get_load_detect_pipe(struct drm_connector *connector, 654bool intel_get_load_detect_pipe(struct drm_connector *connector,
643 struct drm_display_mode *mode, 655 struct drm_display_mode *mode,
644 struct intel_load_detect_pipe *old); 656 struct intel_load_detect_pipe *old);
@@ -694,7 +706,7 @@ void i915_disable_vga_mem(struct drm_device *dev);
694void hsw_enable_ips(struct intel_crtc *crtc); 706void hsw_enable_ips(struct intel_crtc *crtc);
695void hsw_disable_ips(struct intel_crtc *crtc); 707void hsw_disable_ips(struct intel_crtc *crtc);
696void intel_display_set_init_power(struct drm_device *dev, bool enable); 708void intel_display_set_init_power(struct drm_device *dev, bool enable);
697 709int valleyview_get_vco(struct drm_i915_private *dev_priv);
698 710
699/* intel_dp.c */ 711/* intel_dp.c */
700void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); 712void intel_dp_init(struct drm_device *dev, int output_reg, enum port port);
@@ -808,7 +820,8 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
808int intel_panel_setup_backlight(struct drm_connector *connector); 820int intel_panel_setup_backlight(struct drm_connector *connector);
809void intel_panel_enable_backlight(struct intel_connector *connector); 821void intel_panel_enable_backlight(struct intel_connector *connector);
810void intel_panel_disable_backlight(struct intel_connector *connector); 822void intel_panel_disable_backlight(struct intel_connector *connector);
811void intel_panel_destroy_backlight(struct drm_device *dev); 823void intel_panel_destroy_backlight(struct drm_connector *connector);
824void intel_panel_init_backlight_funcs(struct drm_device *dev);
812enum drm_connector_status intel_panel_detect(struct drm_device *dev); 825enum drm_connector_status intel_panel_detect(struct drm_device *dev);
813 826
814 827
@@ -829,6 +842,8 @@ int intel_power_domains_init(struct drm_device *dev);
829void intel_power_domains_remove(struct drm_device *dev); 842void intel_power_domains_remove(struct drm_device *dev);
830bool intel_display_power_enabled(struct drm_device *dev, 843bool intel_display_power_enabled(struct drm_device *dev,
831 enum intel_display_power_domain domain); 844 enum intel_display_power_domain domain);
845bool intel_display_power_enabled_sw(struct drm_device *dev,
846 enum intel_display_power_domain domain);
832void intel_display_power_get(struct drm_device *dev, 847void intel_display_power_get(struct drm_device *dev,
833 enum intel_display_power_domain domain); 848 enum intel_display_power_domain domain);
834void intel_display_power_put(struct drm_device *dev, 849void intel_display_power_put(struct drm_device *dev,
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index d257b093ca68..7b9b350d29ae 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -251,8 +251,9 @@ static void intel_dsi_get_config(struct intel_encoder *encoder,
251 /* XXX: read flags, set to adjusted_mode */ 251 /* XXX: read flags, set to adjusted_mode */
252} 252}
253 253
254static int intel_dsi_mode_valid(struct drm_connector *connector, 254static enum drm_mode_status
255 struct drm_display_mode *mode) 255intel_dsi_mode_valid(struct drm_connector *connector,
256 struct drm_display_mode *mode)
256{ 257{
257 struct intel_connector *intel_connector = to_intel_connector(connector); 258 struct intel_connector *intel_connector = to_intel_connector(connector);
258 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 259 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
diff --git a/drivers/gpu/drm/i915/intel_dvo.c b/drivers/gpu/drm/i915/intel_dvo.c
index 3c7736546856..eeff998e52ef 100644
--- a/drivers/gpu/drm/i915/intel_dvo.c
+++ b/drivers/gpu/drm/i915/intel_dvo.c
@@ -234,8 +234,9 @@ static void intel_dvo_dpms(struct drm_connector *connector, int mode)
234 intel_modeset_check_state(connector->dev); 234 intel_modeset_check_state(connector->dev);
235} 235}
236 236
237static int intel_dvo_mode_valid(struct drm_connector *connector, 237static enum drm_mode_status
238 struct drm_display_mode *mode) 238intel_dvo_mode_valid(struct drm_connector *connector,
239 struct drm_display_mode *mode)
239{ 240{
240 struct intel_dvo *intel_dvo = intel_attached_dvo(connector); 241 struct intel_dvo *intel_dvo = intel_attached_dvo(connector);
241 242
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index 895fcb4fbd94..284c3eb066f6 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -57,18 +57,14 @@ static struct fb_ops intelfb_ops = {
57 .fb_debug_leave = drm_fb_helper_debug_leave, 57 .fb_debug_leave = drm_fb_helper_debug_leave,
58}; 58};
59 59
60static int intelfb_create(struct drm_fb_helper *helper, 60static int intelfb_alloc(struct drm_fb_helper *helper,
61 struct drm_fb_helper_surface_size *sizes) 61 struct drm_fb_helper_surface_size *sizes)
62{ 62{
63 struct intel_fbdev *ifbdev = 63 struct intel_fbdev *ifbdev =
64 container_of(helper, struct intel_fbdev, helper); 64 container_of(helper, struct intel_fbdev, helper);
65 struct drm_device *dev = helper->dev; 65 struct drm_device *dev = helper->dev;
66 struct drm_i915_private *dev_priv = dev->dev_private;
67 struct fb_info *info;
68 struct drm_framebuffer *fb;
69 struct drm_mode_fb_cmd2 mode_cmd = {}; 66 struct drm_mode_fb_cmd2 mode_cmd = {};
70 struct drm_i915_gem_object *obj; 67 struct drm_i915_gem_object *obj;
71 struct device *device = &dev->pdev->dev;
72 int size, ret; 68 int size, ret;
73 69
74 /* we don't do packed 24bpp */ 70 /* we don't do packed 24bpp */
@@ -94,8 +90,6 @@ static int intelfb_create(struct drm_fb_helper *helper,
94 goto out; 90 goto out;
95 } 91 }
96 92
97 mutex_lock(&dev->struct_mutex);
98
99 /* Flush everything out, we'll be doing GTT only from now on */ 93 /* Flush everything out, we'll be doing GTT only from now on */
100 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); 94 ret = intel_pin_and_fence_fb_obj(dev, obj, NULL);
101 if (ret) { 95 if (ret) {
@@ -103,7 +97,50 @@ static int intelfb_create(struct drm_fb_helper *helper,
103 goto out_unref; 97 goto out_unref;
104 } 98 }
105 99
106 info = framebuffer_alloc(0, device); 100 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
101 if (ret)
102 goto out_unpin;
103
104 return 0;
105
106out_unpin:
107 i915_gem_object_unpin(obj);
108out_unref:
109 drm_gem_object_unreference(&obj->base);
110out:
111 return ret;
112}
113
114static int intelfb_create(struct drm_fb_helper *helper,
115 struct drm_fb_helper_surface_size *sizes)
116{
117 struct intel_fbdev *ifbdev =
118 container_of(helper, struct intel_fbdev, helper);
119 struct intel_framebuffer *intel_fb = &ifbdev->ifb;
120 struct drm_device *dev = helper->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct fb_info *info;
123 struct drm_framebuffer *fb;
124 struct drm_i915_gem_object *obj;
125 int size, ret;
126
127 mutex_lock(&dev->struct_mutex);
128
129 if (!intel_fb->obj) {
130 DRM_DEBUG_KMS("no BIOS fb, allocating a new one\n");
131 ret = intelfb_alloc(helper, sizes);
132 if (ret)
133 goto out_unlock;
134 } else {
135 DRM_DEBUG_KMS("re-using BIOS fb\n");
136 sizes->fb_width = intel_fb->base.width;
137 sizes->fb_height = intel_fb->base.height;
138 }
139
140 obj = intel_fb->obj;
141 size = obj->base.size;
142
143 info = framebuffer_alloc(0, &dev->pdev->dev);
107 if (!info) { 144 if (!info) {
108 ret = -ENOMEM; 145 ret = -ENOMEM;
109 goto out_unpin; 146 goto out_unpin;
@@ -111,10 +148,6 @@ static int intelfb_create(struct drm_fb_helper *helper,
111 148
112 info->par = helper; 149 info->par = helper;
113 150
114 ret = intel_framebuffer_init(dev, &ifbdev->ifb, &mode_cmd, obj);
115 if (ret)
116 goto out_unpin;
117
118 fb = &ifbdev->ifb.base; 151 fb = &ifbdev->ifb.base;
119 152
120 ifbdev->helper.fb = fb; 153 ifbdev->helper.fb = fb;
@@ -170,17 +203,15 @@ static int intelfb_create(struct drm_fb_helper *helper,
170 fb->width, fb->height, 203 fb->width, fb->height,
171 i915_gem_obj_ggtt_offset(obj), obj); 204 i915_gem_obj_ggtt_offset(obj), obj);
172 205
173
174 mutex_unlock(&dev->struct_mutex); 206 mutex_unlock(&dev->struct_mutex);
175 vga_switcheroo_client_fb_set(dev->pdev, info); 207 vga_switcheroo_client_fb_set(dev->pdev, info);
176 return 0; 208 return 0;
177 209
178out_unpin: 210out_unpin:
179 i915_gem_object_unpin(obj); 211 i915_gem_object_unpin(obj);
180out_unref:
181 drm_gem_object_unreference(&obj->base); 212 drm_gem_object_unreference(&obj->base);
213out_unlock:
182 mutex_unlock(&dev->struct_mutex); 214 mutex_unlock(&dev->struct_mutex);
183out:
184 return ret; 215 return ret;
185} 216}
186 217
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 03f9ca70530c..6a6ad0c78dc7 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -853,8 +853,9 @@ static int hdmi_portclock_limit(struct intel_hdmi *hdmi)
853 return 225000; 853 return 225000;
854} 854}
855 855
856static int intel_hdmi_mode_valid(struct drm_connector *connector, 856static enum drm_mode_status
857 struct drm_display_mode *mode) 857intel_hdmi_mode_valid(struct drm_connector *connector,
858 struct drm_display_mode *mode)
858{ 859{
859 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector))) 860 if (mode->clock > hdmi_portclock_limit(intel_attached_hdmi(connector)))
860 return MODE_CLOCK_HIGH; 861 return MODE_CLOCK_HIGH;
@@ -1081,7 +1082,7 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1081 struct drm_i915_private *dev_priv = dev->dev_private; 1082 struct drm_i915_private *dev_priv = dev->dev_private;
1082 struct intel_crtc *intel_crtc = 1083 struct intel_crtc *intel_crtc =
1083 to_intel_crtc(encoder->base.crtc); 1084 to_intel_crtc(encoder->base.crtc);
1084 int port = vlv_dport_to_channel(dport); 1085 enum dpio_channel port = vlv_dport_to_channel(dport);
1085 int pipe = intel_crtc->pipe; 1086 int pipe = intel_crtc->pipe;
1086 u32 val; 1087 u32 val;
1087 1088
@@ -1090,41 +1091,33 @@ static void vlv_hdmi_pre_enable(struct intel_encoder *encoder)
1090 1091
1091 /* Enable clock channels for this port */ 1092 /* Enable clock channels for this port */
1092 mutex_lock(&dev_priv->dpio_lock); 1093 mutex_lock(&dev_priv->dpio_lock);
1093 val = vlv_dpio_read(dev_priv, pipe, DPIO_DATA_LANE_A(port)); 1094 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1094 val = 0; 1095 val = 0;
1095 if (pipe) 1096 if (pipe)
1096 val |= (1<<21); 1097 val |= (1<<21);
1097 else 1098 else
1098 val &= ~(1<<21); 1099 val &= ~(1<<21);
1099 val |= 0x001000c4; 1100 val |= 0x001000c4;
1100 vlv_dpio_write(dev_priv, pipe, DPIO_DATA_CHANNEL(port), val); 1101 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1101 1102
1102 /* HDMI 1.0V-2dB */ 1103 /* HDMI 1.0V-2dB */
1103 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port), 0); 1104 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0);
1104 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL4(port), 1105 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), 0x2b245f5f);
1105 0x2b245f5f); 1106 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 0x5578b83a);
1106 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL2(port), 1107 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0c782040);
1107 0x5578b83a); 1108 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), 0x2b247878);
1108 vlv_dpio_write(dev_priv, pipe, DPIO_TX_SWING_CTL3(port), 1109 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1109 0x0c782040); 1110 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1110 vlv_dpio_write(dev_priv, pipe, DPIO_TX3_SWING_CTL4(port), 1111 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1111 0x2b247878);
1112 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER0(port), 0x00030000);
1113 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port),
1114 0x00002000);
1115 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
1116 DPIO_TX_OCALINIT_EN);
1117 1112
1118 /* Program lane clock */ 1113 /* Program lane clock */
1119 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF0(port), 1114 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1120 0x00760018); 1115 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1121 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLOCKBUF8(port),
1122 0x00400888);
1123 mutex_unlock(&dev_priv->dpio_lock); 1116 mutex_unlock(&dev_priv->dpio_lock);
1124 1117
1125 intel_enable_hdmi(encoder); 1118 intel_enable_hdmi(encoder);
1126 1119
1127 vlv_wait_port_ready(dev_priv, port); 1120 vlv_wait_port_ready(dev_priv, dport);
1128} 1121}
1129 1122
1130static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder) 1123static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
@@ -1134,7 +1127,7 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1134 struct drm_i915_private *dev_priv = dev->dev_private; 1127 struct drm_i915_private *dev_priv = dev->dev_private;
1135 struct intel_crtc *intel_crtc = 1128 struct intel_crtc *intel_crtc =
1136 to_intel_crtc(encoder->base.crtc); 1129 to_intel_crtc(encoder->base.crtc);
1137 int port = vlv_dport_to_channel(dport); 1130 enum dpio_channel port = vlv_dport_to_channel(dport);
1138 int pipe = intel_crtc->pipe; 1131 int pipe = intel_crtc->pipe;
1139 1132
1140 if (!IS_VALLEYVIEW(dev)) 1133 if (!IS_VALLEYVIEW(dev))
@@ -1142,24 +1135,22 @@ static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder)
1142 1135
1143 /* Program Tx lane resets to default */ 1136 /* Program Tx lane resets to default */
1144 mutex_lock(&dev_priv->dpio_lock); 1137 mutex_lock(&dev_priv->dpio_lock);
1145 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 1138 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1146 DPIO_PCS_TX_LANE2_RESET | 1139 DPIO_PCS_TX_LANE2_RESET |
1147 DPIO_PCS_TX_LANE1_RESET); 1140 DPIO_PCS_TX_LANE1_RESET);
1148 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 1141 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1149 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1142 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1150 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1143 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1151 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1144 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1152 DPIO_PCS_CLK_SOFT_RESET); 1145 DPIO_PCS_CLK_SOFT_RESET);
1153 1146
1154 /* Fix up inter-pair skew failure */ 1147 /* Fix up inter-pair skew failure */
1155 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_STAGGER1(port), 0x00750f00); 1148 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1156 vlv_dpio_write(dev_priv, pipe, DPIO_TX_CTL(port), 0x00001500); 1149 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1157 vlv_dpio_write(dev_priv, pipe, DPIO_TX_LANE(port), 0x40400000); 1150 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1158 1151
1159 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CTL_OVER1(port), 1152 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), 0x00002000);
1160 0x00002000); 1153 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1161 vlv_dpio_write(dev_priv, pipe, DPIO_TX_OCALINIT(port),
1162 DPIO_TX_OCALINIT_EN);
1163 mutex_unlock(&dev_priv->dpio_lock); 1154 mutex_unlock(&dev_priv->dpio_lock);
1164} 1155}
1165 1156
@@ -1169,13 +1160,13 @@ static void vlv_hdmi_post_disable(struct intel_encoder *encoder)
1169 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; 1160 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
1170 struct intel_crtc *intel_crtc = 1161 struct intel_crtc *intel_crtc =
1171 to_intel_crtc(encoder->base.crtc); 1162 to_intel_crtc(encoder->base.crtc);
1172 int port = vlv_dport_to_channel(dport); 1163 enum dpio_channel port = vlv_dport_to_channel(dport);
1173 int pipe = intel_crtc->pipe; 1164 int pipe = intel_crtc->pipe;
1174 1165
1175 /* Reset lanes to avoid HDMI flicker (VLV w/a) */ 1166 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1176 mutex_lock(&dev_priv->dpio_lock); 1167 mutex_lock(&dev_priv->dpio_lock);
1177 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_TX(port), 0x00000000); 1168 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1178 vlv_dpio_write(dev_priv, pipe, DPIO_PCS_CLK(port), 0x00e00060); 1169 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1179 mutex_unlock(&dev_priv->dpio_lock); 1170 mutex_unlock(&dev_priv->dpio_lock);
1180} 1171}
1181 1172
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 2ca17b14b6c1..b1dc33f47899 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -82,20 +82,11 @@ static int get_disp_clk_div(struct drm_i915_private *dev_priv,
82 82
83static void gmbus_set_freq(struct drm_i915_private *dev_priv) 83static void gmbus_set_freq(struct drm_i915_private *dev_priv)
84{ 84{
85 int vco_freq[] = { 800, 1600, 2000, 2400 }; 85 int vco, gmbus_freq = 0, cdclk_div;
86 int gmbus_freq = 0, cdclk_div, hpll_freq;
87 86
88 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); 87 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
89 88
90 /* Skip setting the gmbus freq if BIOS has already programmed it */ 89 vco = valleyview_get_vco(dev_priv);
91 if (I915_READ(GMBUSFREQ_VLV) != 0xA0)
92 return;
93
94 /* Obtain SKU information */
95 mutex_lock(&dev_priv->dpio_lock);
96 hpll_freq =
97 vlv_cck_read(dev_priv, CCK_FUSE_REG) & CCK_FUSE_HPLL_FREQ_MASK;
98 mutex_unlock(&dev_priv->dpio_lock);
99 90
100 /* Get the CDCLK divide ratio */ 91 /* Get the CDCLK divide ratio */
101 cdclk_div = get_disp_clk_div(dev_priv, CDCLK); 92 cdclk_div = get_disp_clk_div(dev_priv, CDCLK);
@@ -106,7 +97,7 @@ static void gmbus_set_freq(struct drm_i915_private *dev_priv)
106 * in fact 1MHz is the correct frequency. 97 * in fact 1MHz is the correct frequency.
107 */ 98 */
108 if (cdclk_div) 99 if (cdclk_div)
109 gmbus_freq = (vco_freq[hpll_freq] << 1) / cdclk_div; 100 gmbus_freq = (vco << 1) / cdclk_div;
110 101
111 if (WARN_ON(gmbus_freq == 0)) 102 if (WARN_ON(gmbus_freq == 0))
112 return; 103 return;
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index c3b4da7895ed..3deb58e2f394 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -256,8 +256,9 @@ static void intel_disable_lvds(struct intel_encoder *encoder)
256 POSTING_READ(lvds_encoder->reg); 256 POSTING_READ(lvds_encoder->reg);
257} 257}
258 258
259static int intel_lvds_mode_valid(struct drm_connector *connector, 259static enum drm_mode_status
260 struct drm_display_mode *mode) 260intel_lvds_mode_valid(struct drm_connector *connector,
261 struct drm_display_mode *mode)
261{ 262{
262 struct intel_connector *intel_connector = to_intel_connector(connector); 263 struct intel_connector *intel_connector = to_intel_connector(connector);
263 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 264 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
diff --git a/drivers/gpu/drm/i915/intel_opregion.c b/drivers/gpu/drm/i915/intel_opregion.c
index 6d69a9bad865..a8febbd3017b 100644
--- a/drivers/gpu/drm/i915/intel_opregion.c
+++ b/drivers/gpu/drm/i915/intel_opregion.c
@@ -396,13 +396,10 @@ int intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
396static u32 asle_set_backlight(struct drm_device *dev, u32 bclp) 396static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
397{ 397{
398 struct drm_i915_private *dev_priv = dev->dev_private; 398 struct drm_i915_private *dev_priv = dev->dev_private;
399 struct drm_encoder *encoder;
400 struct drm_connector *connector; 399 struct drm_connector *connector;
401 struct intel_connector *intel_connector = NULL; 400 struct intel_connector *intel_connector;
402 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0]; 401 struct intel_panel *panel;
403 struct opregion_asle __iomem *asle = dev_priv->opregion.asle; 402 struct opregion_asle __iomem *asle = dev_priv->opregion.asle;
404 u32 ret = 0;
405 bool found = false;
406 403
407 DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp); 404 DRM_DEBUG_DRIVER("bclp = 0x%08x\n", bclp);
408 405
@@ -414,38 +411,24 @@ static u32 asle_set_backlight(struct drm_device *dev, u32 bclp)
414 return ASLC_BACKLIGHT_FAILED; 411 return ASLC_BACKLIGHT_FAILED;
415 412
416 mutex_lock(&dev->mode_config.mutex); 413 mutex_lock(&dev->mode_config.mutex);
414
417 /* 415 /*
418 * Could match the OpRegion connector here instead, but we'd also need 416 * Update backlight on all connectors that support backlight (usually
419 * to verify the connector could handle a backlight call. 417 * only one).
420 */ 418 */
421 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
422 if (encoder->crtc == crtc) {
423 found = true;
424 break;
425 }
426
427 if (!found) {
428 ret = ASLC_BACKLIGHT_FAILED;
429 goto out;
430 }
431
432 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
433 if (connector->encoder == encoder)
434 intel_connector = to_intel_connector(connector);
435
436 if (!intel_connector) {
437 ret = ASLC_BACKLIGHT_FAILED;
438 goto out;
439 }
440
441 DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp); 419 DRM_DEBUG_KMS("updating opregion backlight %d/255\n", bclp);
442 intel_panel_set_backlight(intel_connector, bclp, 255); 420 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
421 intel_connector = to_intel_connector(connector);
422 panel = &intel_connector->panel;
423 if (panel->backlight.present)
424 intel_panel_set_backlight(intel_connector, bclp, 255);
425 }
443 iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, &asle->cblv); 426 iowrite32(DIV_ROUND_UP(bclp * 100, 255) | ASLE_CBLV_VALID, &asle->cblv);
444 427
445out:
446 mutex_unlock(&dev->mode_config.mutex); 428 mutex_unlock(&dev->mode_config.mutex);
447 429
448 return ret; 430
431 return 0;
449} 432}
450 433
451static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi) 434static u32 asle_set_als_illum(struct drm_device *dev, u32 alsi)
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index f161ac02c4f6..e480cf41c536 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -325,203 +325,170 @@ out:
325 pipe_config->gmch_pfit.lvds_border_bits = border; 325 pipe_config->gmch_pfit.lvds_border_bits = border;
326} 326}
327 327
328static int is_backlight_combination_mode(struct drm_device *dev) 328static int i915_panel_invert_brightness;
329MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
330 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
331 "report PCI device ID, subsystem vendor and subsystem device ID "
332 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
333 "It will then be included in an upcoming module version.");
334module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
335static u32 intel_panel_compute_brightness(struct intel_connector *connector,
336 u32 val)
329{ 337{
338 struct drm_device *dev = connector->base.dev;
330 struct drm_i915_private *dev_priv = dev->dev_private; 339 struct drm_i915_private *dev_priv = dev->dev_private;
340 struct intel_panel *panel = &connector->panel;
331 341
332 if (IS_GEN4(dev)) 342 WARN_ON(panel->backlight.max == 0);
333 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
334 343
335 if (IS_GEN2(dev)) 344 if (i915_panel_invert_brightness < 0)
336 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; 345 return val;
337 346
338 return 0; 347 if (i915_panel_invert_brightness > 0 ||
348 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
349 return panel->backlight.max - val;
350 }
351
352 return val;
339} 353}
340 354
341/* XXX: query mode clock or hardware clock and program max PWM appropriately 355static u32 bdw_get_backlight(struct intel_connector *connector)
342 * when it's 0.
343 */
344static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
345{ 356{
357 struct drm_device *dev = connector->base.dev;
346 struct drm_i915_private *dev_priv = dev->dev_private; 358 struct drm_i915_private *dev_priv = dev->dev_private;
347 u32 val;
348
349 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
350
351 /* Restore the CTL value if it lost, e.g. GPU reset */
352 359
353 if (HAS_PCH_SPLIT(dev_priv->dev)) { 360 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
354 val = I915_READ(BLC_PWM_PCH_CTL2); 361}
355 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
356 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
357 } else if (val == 0) {
358 val = dev_priv->regfile.saveBLC_PWM_CTL2;
359 I915_WRITE(BLC_PWM_PCH_CTL2, val);
360 }
361 } else if (IS_VALLEYVIEW(dev)) {
362 val = I915_READ(VLV_BLC_PWM_CTL(pipe));
363 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
364 dev_priv->regfile.saveBLC_PWM_CTL = val;
365 dev_priv->regfile.saveBLC_PWM_CTL2 =
366 I915_READ(VLV_BLC_PWM_CTL2(pipe));
367 } else if (val == 0) {
368 val = dev_priv->regfile.saveBLC_PWM_CTL;
369 I915_WRITE(VLV_BLC_PWM_CTL(pipe), val);
370 I915_WRITE(VLV_BLC_PWM_CTL2(pipe),
371 dev_priv->regfile.saveBLC_PWM_CTL2);
372 }
373 362
374 if (!val) 363static u32 pch_get_backlight(struct intel_connector *connector)
375 val = 0x0f42ffff; 364{
376 } else { 365 struct drm_device *dev = connector->base.dev;
377 val = I915_READ(BLC_PWM_CTL); 366 struct drm_i915_private *dev_priv = dev->dev_private;
378 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
379 dev_priv->regfile.saveBLC_PWM_CTL = val;
380 if (INTEL_INFO(dev)->gen >= 4)
381 dev_priv->regfile.saveBLC_PWM_CTL2 =
382 I915_READ(BLC_PWM_CTL2);
383 } else if (val == 0) {
384 val = dev_priv->regfile.saveBLC_PWM_CTL;
385 I915_WRITE(BLC_PWM_CTL, val);
386 if (INTEL_INFO(dev)->gen >= 4)
387 I915_WRITE(BLC_PWM_CTL2,
388 dev_priv->regfile.saveBLC_PWM_CTL2);
389 }
390 }
391 367
392 return val; 368 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
393} 369}
394 370
395static u32 intel_panel_get_max_backlight(struct drm_device *dev, 371static u32 i9xx_get_backlight(struct intel_connector *connector)
396 enum pipe pipe)
397{ 372{
398 u32 max; 373 struct drm_device *dev = connector->base.dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375 struct intel_panel *panel = &connector->panel;
376 u32 val;
399 377
400 max = i915_read_blc_pwm_ctl(dev, pipe); 378 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
379 if (INTEL_INFO(dev)->gen < 4)
380 val >>= 1;
401 381
402 if (HAS_PCH_SPLIT(dev)) { 382 if (panel->backlight.combination_mode) {
403 max >>= 16; 383 u8 lbpc;
404 } else {
405 if (INTEL_INFO(dev)->gen < 4)
406 max >>= 17;
407 else
408 max >>= 16;
409 384
410 if (is_backlight_combination_mode(dev)) 385 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
411 max *= 0xff; 386 val *= lbpc;
412 } 387 }
413 388
414 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); 389 return val;
415
416 return max;
417} 390}
418 391
419static int i915_panel_invert_brightness; 392static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe)
420MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
421 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
422 "report PCI device ID, subsystem vendor and subsystem device ID "
423 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
424 "It will then be included in an upcoming module version.");
425module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
426static u32 intel_panel_compute_brightness(struct drm_device *dev,
427 enum pipe pipe, u32 val)
428{ 393{
429 struct drm_i915_private *dev_priv = dev->dev_private; 394 struct drm_i915_private *dev_priv = dev->dev_private;
430 395
431 if (i915_panel_invert_brightness < 0) 396 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
432 return val; 397}
433 398
434 if (i915_panel_invert_brightness > 0 || 399static u32 vlv_get_backlight(struct intel_connector *connector)
435 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { 400{
436 u32 max = intel_panel_get_max_backlight(dev, pipe); 401 struct drm_device *dev = connector->base.dev;
437 if (max) 402 enum pipe pipe = intel_get_pipe_from_connector(connector);
438 return max - val;
439 }
440 403
441 return val; 404 return _vlv_get_backlight(dev, pipe);
442} 405}
443 406
444static u32 intel_panel_get_backlight(struct drm_device *dev, 407static u32 intel_panel_get_backlight(struct intel_connector *connector)
445 enum pipe pipe)
446{ 408{
409 struct drm_device *dev = connector->base.dev;
447 struct drm_i915_private *dev_priv = dev->dev_private; 410 struct drm_i915_private *dev_priv = dev->dev_private;
448 u32 val; 411 u32 val;
449 unsigned long flags; 412 unsigned long flags;
450 int reg;
451 413
452 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 414 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
453 415
454 if (HAS_PCH_SPLIT(dev)) { 416 val = dev_priv->display.get_backlight(connector);
455 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; 417 val = intel_panel_compute_brightness(connector, val);
456 } else {
457 if (IS_VALLEYVIEW(dev))
458 reg = VLV_BLC_PWM_CTL(pipe);
459 else
460 reg = BLC_PWM_CTL;
461
462 val = I915_READ(reg) & BACKLIGHT_DUTY_CYCLE_MASK;
463 if (INTEL_INFO(dev)->gen < 4)
464 val >>= 1;
465 418
466 if (is_backlight_combination_mode(dev)) { 419 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
467 u8 lbpc;
468
469 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
470 val *= lbpc;
471 }
472 }
473
474 val = intel_panel_compute_brightness(dev, pipe, val);
475
476 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
477 420
478 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); 421 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
479 return val; 422 return val;
480} 423}
481 424
482static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) 425static void bdw_set_backlight(struct intel_connector *connector, u32 level)
483{ 426{
427 struct drm_device *dev = connector->base.dev;
484 struct drm_i915_private *dev_priv = dev->dev_private; 428 struct drm_i915_private *dev_priv = dev->dev_private;
485 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; 429 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
486 I915_WRITE(BLC_PWM_CPU_CTL, val | level); 430 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
487} 431}
488 432
489static void intel_panel_actually_set_backlight(struct drm_device *dev, 433static void pch_set_backlight(struct intel_connector *connector, u32 level)
490 enum pipe pipe, u32 level)
491{ 434{
435 struct drm_device *dev = connector->base.dev;
492 struct drm_i915_private *dev_priv = dev->dev_private; 436 struct drm_i915_private *dev_priv = dev->dev_private;
493 u32 tmp; 437 u32 tmp;
494 int reg;
495 438
496 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); 439 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
497 level = intel_panel_compute_brightness(dev, pipe, level); 440 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
441}
442
443static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
444{
445 struct drm_device *dev = connector->base.dev;
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 struct intel_panel *panel = &connector->panel;
448 u32 tmp, mask;
498 449
499 if (HAS_PCH_SPLIT(dev)) 450 WARN_ON(panel->backlight.max == 0);
500 return intel_pch_panel_set_backlight(dev, level);
501 451
502 if (is_backlight_combination_mode(dev)) { 452 if (panel->backlight.combination_mode) {
503 u32 max = intel_panel_get_max_backlight(dev, pipe);
504 u8 lbpc; 453 u8 lbpc;
505 454
506 /* we're screwed, but keep behaviour backwards compatible */ 455 lbpc = level * 0xfe / panel->backlight.max + 1;
507 if (!max)
508 max = 1;
509
510 lbpc = level * 0xfe / max + 1;
511 level /= lbpc; 456 level /= lbpc;
512 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); 457 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
513 } 458 }
514 459
515 if (IS_VALLEYVIEW(dev)) 460 if (IS_GEN4(dev)) {
516 reg = VLV_BLC_PWM_CTL(pipe); 461 mask = BACKLIGHT_DUTY_CYCLE_MASK;
517 else 462 } else {
518 reg = BLC_PWM_CTL;
519
520 tmp = I915_READ(reg);
521 if (INTEL_INFO(dev)->gen < 4)
522 level <<= 1; 463 level <<= 1;
523 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; 464 mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
524 I915_WRITE(reg, tmp | level); 465 }
466
467 tmp = I915_READ(BLC_PWM_CTL) & ~mask;
468 I915_WRITE(BLC_PWM_CTL, tmp | level);
469}
470
471static void vlv_set_backlight(struct intel_connector *connector, u32 level)
472{
473 struct drm_device *dev = connector->base.dev;
474 struct drm_i915_private *dev_priv = dev->dev_private;
475 enum pipe pipe = intel_get_pipe_from_connector(connector);
476 u32 tmp;
477
478 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
479 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
480}
481
482static void
483intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level)
484{
485 struct drm_device *dev = connector->base.dev;
486 struct drm_i915_private *dev_priv = dev->dev_private;
487
488 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
489
490 level = intel_panel_compute_brightness(connector, level);
491 dev_priv->display.set_backlight(connector, level);
525} 492}
526 493
527/* set backlight brightness to level in range [0..max] */ 494/* set backlight brightness to level in range [0..max] */
@@ -530,6 +497,7 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
530{ 497{
531 struct drm_device *dev = connector->base.dev; 498 struct drm_device *dev = connector->base.dev;
532 struct drm_i915_private *dev_priv = dev->dev_private; 499 struct drm_i915_private *dev_priv = dev->dev_private;
500 struct intel_panel *panel = &connector->panel;
533 enum pipe pipe = intel_get_pipe_from_connector(connector); 501 enum pipe pipe = intel_get_pipe_from_connector(connector);
534 u32 freq; 502 u32 freq;
535 unsigned long flags; 503 unsigned long flags;
@@ -537,34 +505,77 @@ void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
537 if (pipe == INVALID_PIPE) 505 if (pipe == INVALID_PIPE)
538 return; 506 return;
539 507
540 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 508 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
541 509
542 freq = intel_panel_get_max_backlight(dev, pipe); 510 WARN_ON(panel->backlight.max == 0);
543 if (!freq) {
544 /* we are screwed, bail out */
545 goto out;
546 }
547 511
548 /* scale to hardware, but be careful to not overflow */ 512 /* scale to hardware max, but be careful to not overflow */
513 freq = panel->backlight.max;
549 if (freq < max) 514 if (freq < max)
550 level = level * freq / max; 515 level = level * freq / max;
551 else 516 else
552 level = freq / max * level; 517 level = freq / max * level;
553 518
554 dev_priv->backlight.level = level; 519 panel->backlight.level = level;
555 if (dev_priv->backlight.device) 520 if (panel->backlight.device)
556 dev_priv->backlight.device->props.brightness = level; 521 panel->backlight.device->props.brightness = level;
557 522
558 if (dev_priv->backlight.enabled) 523 if (panel->backlight.enabled)
559 intel_panel_actually_set_backlight(dev, pipe, level); 524 intel_panel_actually_set_backlight(connector, level);
560out: 525
561 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); 526 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
527}
528
529static void pch_disable_backlight(struct intel_connector *connector)
530{
531 struct drm_device *dev = connector->base.dev;
532 struct drm_i915_private *dev_priv = dev->dev_private;
533 u32 tmp;
534
535 intel_panel_actually_set_backlight(connector, 0);
536
537 tmp = I915_READ(BLC_PWM_CPU_CTL2);
538 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
539
540 tmp = I915_READ(BLC_PWM_PCH_CTL1);
541 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
542}
543
544static void i9xx_disable_backlight(struct intel_connector *connector)
545{
546 intel_panel_actually_set_backlight(connector, 0);
547}
548
549static void i965_disable_backlight(struct intel_connector *connector)
550{
551 struct drm_device *dev = connector->base.dev;
552 struct drm_i915_private *dev_priv = dev->dev_private;
553 u32 tmp;
554
555 intel_panel_actually_set_backlight(connector, 0);
556
557 tmp = I915_READ(BLC_PWM_CTL2);
558 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
559}
560
561static void vlv_disable_backlight(struct intel_connector *connector)
562{
563 struct drm_device *dev = connector->base.dev;
564 struct drm_i915_private *dev_priv = dev->dev_private;
565 enum pipe pipe = intel_get_pipe_from_connector(connector);
566 u32 tmp;
567
568 intel_panel_actually_set_backlight(connector, 0);
569
570 tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
571 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);
562} 572}
563 573
564void intel_panel_disable_backlight(struct intel_connector *connector) 574void intel_panel_disable_backlight(struct intel_connector *connector)
565{ 575{
566 struct drm_device *dev = connector->base.dev; 576 struct drm_device *dev = connector->base.dev;
567 struct drm_i915_private *dev_priv = dev->dev_private; 577 struct drm_i915_private *dev_priv = dev->dev_private;
578 struct intel_panel *panel = &connector->panel;
568 enum pipe pipe = intel_get_pipe_from_connector(connector); 579 enum pipe pipe = intel_get_pipe_from_connector(connector);
569 unsigned long flags; 580 unsigned long flags;
570 581
@@ -582,141 +593,215 @@ void intel_panel_disable_backlight(struct intel_connector *connector)
582 return; 593 return;
583 } 594 }
584 595
585 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 596 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
586 597
587 dev_priv->backlight.enabled = false; 598 panel->backlight.enabled = false;
588 intel_panel_actually_set_backlight(dev, pipe, 0); 599 dev_priv->display.disable_backlight(connector);
589 600
590 if (INTEL_INFO(dev)->gen >= 4) { 601 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
591 uint32_t reg, tmp; 602}
592 603
593 if (HAS_PCH_SPLIT(dev)) 604static void bdw_enable_backlight(struct intel_connector *connector)
594 reg = BLC_PWM_CPU_CTL2; 605{
595 else if (IS_VALLEYVIEW(dev)) 606 struct drm_device *dev = connector->base.dev;
596 reg = VLV_BLC_PWM_CTL2(pipe); 607 struct drm_i915_private *dev_priv = dev->dev_private;
597 else 608 struct intel_panel *panel = &connector->panel;
598 reg = BLC_PWM_CTL2; 609 u32 pch_ctl1, pch_ctl2;
610
611 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
612 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
613 DRM_DEBUG_KMS("pch backlight already enabled\n");
614 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
615 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
616 }
599 617
600 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); 618 pch_ctl2 = panel->backlight.max << 16;
619 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
601 620
602 if (HAS_PCH_SPLIT(dev)) { 621 pch_ctl1 = 0;
603 tmp = I915_READ(BLC_PWM_PCH_CTL1); 622 if (panel->backlight.active_low_pwm)
604 tmp &= ~BLM_PCH_PWM_ENABLE; 623 pch_ctl1 |= BLM_PCH_POLARITY;
605 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
606 }
607 }
608 624
609 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); 625 /* BDW always uses the pch pwm controls. */
626 pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE;
627
628 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
629 POSTING_READ(BLC_PWM_PCH_CTL1);
630 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
631
632 /* This won't stick until the above enable. */
633 intel_panel_actually_set_backlight(connector, panel->backlight.level);
610} 634}
611 635
612void intel_panel_enable_backlight(struct intel_connector *connector) 636static void pch_enable_backlight(struct intel_connector *connector)
613{ 637{
614 struct drm_device *dev = connector->base.dev; 638 struct drm_device *dev = connector->base.dev;
615 struct drm_i915_private *dev_priv = dev->dev_private; 639 struct drm_i915_private *dev_priv = dev->dev_private;
640 struct intel_panel *panel = &connector->panel;
616 enum pipe pipe = intel_get_pipe_from_connector(connector); 641 enum pipe pipe = intel_get_pipe_from_connector(connector);
617 enum transcoder cpu_transcoder = 642 enum transcoder cpu_transcoder =
618 intel_pipe_to_cpu_transcoder(dev_priv, pipe); 643 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
619 unsigned long flags; 644 u32 cpu_ctl2, pch_ctl1, pch_ctl2;
620 645
621 if (pipe == INVALID_PIPE) 646 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
622 return; 647 if (cpu_ctl2 & BLM_PWM_ENABLE) {
648 WARN(1, "cpu backlight already enabled\n");
649 cpu_ctl2 &= ~BLM_PWM_ENABLE;
650 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
651 }
623 652
624 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); 653 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
654 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
655 DRM_DEBUG_KMS("pch backlight already enabled\n");
656 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
657 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
658 }
625 659
626 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 660 if (cpu_transcoder == TRANSCODER_EDP)
661 cpu_ctl2 = BLM_TRANSCODER_EDP;
662 else
663 cpu_ctl2 = BLM_PIPE(cpu_transcoder);
664 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
665 POSTING_READ(BLC_PWM_CPU_CTL2);
666 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);
667
668 /* This won't stick until the above enable. */
669 intel_panel_actually_set_backlight(connector, panel->backlight.level);
670
671 pch_ctl2 = panel->backlight.max << 16;
672 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
673
674 pch_ctl1 = 0;
675 if (panel->backlight.active_low_pwm)
676 pch_ctl1 |= BLM_PCH_POLARITY;
677
678 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
679 POSTING_READ(BLC_PWM_PCH_CTL1);
680 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
681}
682
683static void i9xx_enable_backlight(struct intel_connector *connector)
684{
685 struct drm_device *dev = connector->base.dev;
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 struct intel_panel *panel = &connector->panel;
688 u32 ctl, freq;
627 689
628 if (dev_priv->backlight.level == 0) { 690 ctl = I915_READ(BLC_PWM_CTL);
629 dev_priv->backlight.level = intel_panel_get_max_backlight(dev, 691 if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
630 pipe); 692 WARN(1, "backlight already enabled\n");
631 if (dev_priv->backlight.device) 693 I915_WRITE(BLC_PWM_CTL, 0);
632 dev_priv->backlight.device->props.brightness =
633 dev_priv->backlight.level;
634 } 694 }
635 695
636 if (INTEL_INFO(dev)->gen >= 4) { 696 freq = panel->backlight.max;
637 uint32_t reg, tmp; 697 if (panel->backlight.combination_mode)
698 freq /= 0xff;
638 699
639 if (HAS_PCH_SPLIT(dev)) 700 ctl = freq << 17;
640 reg = BLC_PWM_CPU_CTL2; 701 if (IS_GEN2(dev) && panel->backlight.combination_mode)
641 else if (IS_VALLEYVIEW(dev)) 702 ctl |= BLM_LEGACY_MODE;
642 reg = VLV_BLC_PWM_CTL2(pipe); 703 if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm)
643 else 704 ctl |= BLM_POLARITY_PNV;
644 reg = BLC_PWM_CTL2;
645 705
646 tmp = I915_READ(reg); 706 I915_WRITE(BLC_PWM_CTL, ctl);
707 POSTING_READ(BLC_PWM_CTL);
647 708
648 /* Note that this can also get called through dpms changes. And 709 /* XXX: combine this into above write? */
649 * we don't track the backlight dpms state, hence check whether 710 intel_panel_actually_set_backlight(connector, panel->backlight.level);
650 * we have to do anything first. */ 711}
651 if (tmp & BLM_PWM_ENABLE)
652 goto set_level;
653 712
654 if (INTEL_INFO(dev)->num_pipes == 3) 713static void i965_enable_backlight(struct intel_connector *connector)
655 tmp &= ~BLM_PIPE_SELECT_IVB; 714{
656 else 715 struct drm_device *dev = connector->base.dev;
657 tmp &= ~BLM_PIPE_SELECT; 716 struct drm_i915_private *dev_priv = dev->dev_private;
717 struct intel_panel *panel = &connector->panel;
718 enum pipe pipe = intel_get_pipe_from_connector(connector);
719 u32 ctl, ctl2, freq;
658 720
659 if (cpu_transcoder == TRANSCODER_EDP) 721 ctl2 = I915_READ(BLC_PWM_CTL2);
660 tmp |= BLM_TRANSCODER_EDP; 722 if (ctl2 & BLM_PWM_ENABLE) {
661 else 723 WARN(1, "backlight already enabled\n");
662 tmp |= BLM_PIPE(cpu_transcoder); 724 ctl2 &= ~BLM_PWM_ENABLE;
663 tmp &= ~BLM_PWM_ENABLE; 725 I915_WRITE(BLC_PWM_CTL2, ctl2);
664
665 I915_WRITE(reg, tmp);
666 POSTING_READ(reg);
667 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
668
669 if (HAS_PCH_SPLIT(dev) &&
670 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
671 tmp = I915_READ(BLC_PWM_PCH_CTL1);
672 tmp |= BLM_PCH_PWM_ENABLE;
673 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
674 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
675 }
676 } 726 }
677 727
678set_level: 728 freq = panel->backlight.max;
679 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. 729 if (panel->backlight.combination_mode)
680 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these 730 freq /= 0xff;
681 * registers are set. 731
682 */ 732 ctl = freq << 16;
683 dev_priv->backlight.enabled = true; 733 I915_WRITE(BLC_PWM_CTL, ctl);
684 intel_panel_actually_set_backlight(dev, pipe, 734
685 dev_priv->backlight.level); 735 /* XXX: combine this into above write? */
736 intel_panel_actually_set_backlight(connector, panel->backlight.level);
686 737
687 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); 738 ctl2 = BLM_PIPE(pipe);
739 if (panel->backlight.combination_mode)
740 ctl2 |= BLM_COMBINATION_MODE;
741 if (panel->backlight.active_low_pwm)
742 ctl2 |= BLM_POLARITY_I965;
743 I915_WRITE(BLC_PWM_CTL2, ctl2);
744 POSTING_READ(BLC_PWM_CTL2);
745 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
688} 746}
689 747
690/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */ 748static void vlv_enable_backlight(struct intel_connector *connector)
691static void intel_panel_init_backlight_regs(struct drm_device *dev)
692{ 749{
750 struct drm_device *dev = connector->base.dev;
693 struct drm_i915_private *dev_priv = dev->dev_private; 751 struct drm_i915_private *dev_priv = dev->dev_private;
752 struct intel_panel *panel = &connector->panel;
753 enum pipe pipe = intel_get_pipe_from_connector(connector);
754 u32 ctl, ctl2;
694 755
695 if (IS_VALLEYVIEW(dev)) { 756 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
696 enum pipe pipe; 757 if (ctl2 & BLM_PWM_ENABLE) {
758 WARN(1, "backlight already enabled\n");
759 ctl2 &= ~BLM_PWM_ENABLE;
760 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
761 }
697 762
698 for_each_pipe(pipe) { 763 ctl = panel->backlight.max << 16;
699 u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe)); 764 I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl);
700 765
701 /* Skip if the modulation freq is already set */ 766 /* XXX: combine this into above write? */
702 if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK) 767 intel_panel_actually_set_backlight(connector, panel->backlight.level);
703 continue;
704 768
705 cur_val &= BACKLIGHT_DUTY_CYCLE_MASK; 769 ctl2 = 0;
706 I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) | 770 if (panel->backlight.active_low_pwm)
707 cur_val); 771 ctl2 |= BLM_POLARITY_I965;
708 } 772 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
709 } 773 POSTING_READ(VLV_BLC_PWM_CTL2(pipe));
774 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
710} 775}
711 776
712static void intel_panel_init_backlight(struct drm_device *dev) 777void intel_panel_enable_backlight(struct intel_connector *connector)
713{ 778{
779 struct drm_device *dev = connector->base.dev;
714 struct drm_i915_private *dev_priv = dev->dev_private; 780 struct drm_i915_private *dev_priv = dev->dev_private;
781 struct intel_panel *panel = &connector->panel;
782 enum pipe pipe = intel_get_pipe_from_connector(connector);
783 unsigned long flags;
784
785 if (pipe == INVALID_PIPE)
786 return;
787
788 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
789
790 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
791
792 WARN_ON(panel->backlight.max == 0);
715 793
716 intel_panel_init_backlight_regs(dev); 794 if (panel->backlight.level == 0) {
795 panel->backlight.level = panel->backlight.max;
796 if (panel->backlight.device)
797 panel->backlight.device->props.brightness =
798 panel->backlight.level;
799 }
800
801 dev_priv->display.enable_backlight(connector);
802 panel->backlight.enabled = true;
717 803
718 dev_priv->backlight.level = intel_panel_get_backlight(dev, 0); 804 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
719 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
720} 805}
721 806
722enum drm_connector_status 807enum drm_connector_status
@@ -742,7 +827,7 @@ intel_panel_detect(struct drm_device *dev)
742} 827}
743 828
744#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) 829#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
745static int intel_panel_update_status(struct backlight_device *bd) 830static int intel_backlight_device_update_status(struct backlight_device *bd)
746{ 831{
747 struct intel_connector *connector = bl_get_data(bd); 832 struct intel_connector *connector = bl_get_data(bd);
748 struct drm_device *dev = connector->base.dev; 833 struct drm_device *dev = connector->base.dev;
@@ -756,85 +841,306 @@ static int intel_panel_update_status(struct backlight_device *bd)
756 return 0; 841 return 0;
757} 842}
758 843
759static int intel_panel_get_brightness(struct backlight_device *bd) 844static int intel_backlight_device_get_brightness(struct backlight_device *bd)
760{ 845{
761 struct intel_connector *connector = bl_get_data(bd); 846 struct intel_connector *connector = bl_get_data(bd);
762 struct drm_device *dev = connector->base.dev; 847 struct drm_device *dev = connector->base.dev;
763 enum pipe pipe; 848 int ret;
764 849
765 mutex_lock(&dev->mode_config.mutex); 850 mutex_lock(&dev->mode_config.mutex);
766 pipe = intel_get_pipe_from_connector(connector); 851 ret = intel_panel_get_backlight(connector);
767 mutex_unlock(&dev->mode_config.mutex); 852 mutex_unlock(&dev->mode_config.mutex);
768 if (pipe == INVALID_PIPE)
769 return 0;
770 853
771 return intel_panel_get_backlight(connector->base.dev, pipe); 854 return ret;
772} 855}
773 856
774static const struct backlight_ops intel_panel_bl_ops = { 857static const struct backlight_ops intel_backlight_device_ops = {
775 .update_status = intel_panel_update_status, 858 .update_status = intel_backlight_device_update_status,
776 .get_brightness = intel_panel_get_brightness, 859 .get_brightness = intel_backlight_device_get_brightness,
777}; 860};
778 861
779int intel_panel_setup_backlight(struct drm_connector *connector) 862static int intel_backlight_device_register(struct intel_connector *connector)
780{ 863{
781 struct drm_device *dev = connector->dev; 864 struct intel_panel *panel = &connector->panel;
782 struct drm_i915_private *dev_priv = dev->dev_private;
783 struct backlight_properties props; 865 struct backlight_properties props;
784 unsigned long flags;
785 866
786 intel_panel_init_backlight(dev); 867 if (WARN_ON(panel->backlight.device))
787
788 if (WARN_ON(dev_priv->backlight.device))
789 return -ENODEV; 868 return -ENODEV;
790 869
870 BUG_ON(panel->backlight.max == 0);
871
791 memset(&props, 0, sizeof(props)); 872 memset(&props, 0, sizeof(props));
792 props.type = BACKLIGHT_RAW; 873 props.type = BACKLIGHT_RAW;
793 props.brightness = dev_priv->backlight.level; 874 props.brightness = panel->backlight.level;
875 props.max_brightness = panel->backlight.max;
794 876
795 spin_lock_irqsave(&dev_priv->backlight.lock, flags); 877 /*
796 props.max_brightness = intel_panel_get_max_backlight(dev, 0); 878 * Note: using the same name independent of the connector prevents
797 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags); 879 * registration of multiple backlight devices in the driver.
798 880 */
799 if (props.max_brightness == 0) { 881 panel->backlight.device =
800 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
801 return -ENODEV;
802 }
803 dev_priv->backlight.device =
804 backlight_device_register("intel_backlight", 882 backlight_device_register("intel_backlight",
805 connector->kdev, 883 connector->base.kdev,
806 to_intel_connector(connector), 884 connector,
807 &intel_panel_bl_ops, &props); 885 &intel_backlight_device_ops, &props);
808 886
809 if (IS_ERR(dev_priv->backlight.device)) { 887 if (IS_ERR(panel->backlight.device)) {
810 DRM_ERROR("Failed to register backlight: %ld\n", 888 DRM_ERROR("Failed to register backlight: %ld\n",
811 PTR_ERR(dev_priv->backlight.device)); 889 PTR_ERR(panel->backlight.device));
812 dev_priv->backlight.device = NULL; 890 panel->backlight.device = NULL;
813 return -ENODEV; 891 return -ENODEV;
814 } 892 }
815 return 0; 893 return 0;
816} 894}
817 895
818void intel_panel_destroy_backlight(struct drm_device *dev) 896static void intel_backlight_device_unregister(struct intel_connector *connector)
897{
898 struct intel_panel *panel = &connector->panel;
899
900 if (panel->backlight.device) {
901 backlight_device_unregister(panel->backlight.device);
902 panel->backlight.device = NULL;
903 }
904}
905#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
906static int intel_backlight_device_register(struct intel_connector *connector)
907{
908 return 0;
909}
910static void intel_backlight_device_unregister(struct intel_connector *connector)
911{
912}
913#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
914
915/*
916 * Note: The setup hooks can't assume pipe is set!
917 *
918 * XXX: Query mode clock or hardware clock and program PWM modulation frequency
919 * appropriately when it's 0. Use VBT and/or sane defaults.
920 */
921static int bdw_setup_backlight(struct intel_connector *connector)
819{ 922{
923 struct drm_device *dev = connector->base.dev;
820 struct drm_i915_private *dev_priv = dev->dev_private; 924 struct drm_i915_private *dev_priv = dev->dev_private;
821 if (dev_priv->backlight.device) { 925 struct intel_panel *panel = &connector->panel;
822 backlight_device_unregister(dev_priv->backlight.device); 926 u32 pch_ctl1, pch_ctl2, val;
823 dev_priv->backlight.device = NULL; 927
928 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
929 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
930
931 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
932 panel->backlight.max = pch_ctl2 >> 16;
933 if (!panel->backlight.max)
934 return -ENODEV;
935
936 val = bdw_get_backlight(connector);
937 panel->backlight.level = intel_panel_compute_brightness(connector, val);
938
939 panel->backlight.enabled = (pch_ctl1 & BLM_PCH_PWM_ENABLE) &&
940 panel->backlight.level != 0;
941
942 return 0;
943}
944
945static int pch_setup_backlight(struct intel_connector *connector)
946{
947 struct drm_device *dev = connector->base.dev;
948 struct drm_i915_private *dev_priv = dev->dev_private;
949 struct intel_panel *panel = &connector->panel;
950 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
951
952 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
953 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
954
955 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
956 panel->backlight.max = pch_ctl2 >> 16;
957 if (!panel->backlight.max)
958 return -ENODEV;
959
960 val = pch_get_backlight(connector);
961 panel->backlight.level = intel_panel_compute_brightness(connector, val);
962
963 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
964 panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) &&
965 (pch_ctl1 & BLM_PCH_PWM_ENABLE) && panel->backlight.level != 0;
966
967 return 0;
968}
969
970static int i9xx_setup_backlight(struct intel_connector *connector)
971{
972 struct drm_device *dev = connector->base.dev;
973 struct drm_i915_private *dev_priv = dev->dev_private;
974 struct intel_panel *panel = &connector->panel;
975 u32 ctl, val;
976
977 ctl = I915_READ(BLC_PWM_CTL);
978
979 if (IS_GEN2(dev))
980 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
981
982 if (IS_PINEVIEW(dev))
983 panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV;
984
985 panel->backlight.max = ctl >> 17;
986 if (panel->backlight.combination_mode)
987 panel->backlight.max *= 0xff;
988
989 if (!panel->backlight.max)
990 return -ENODEV;
991
992 val = i9xx_get_backlight(connector);
993 panel->backlight.level = intel_panel_compute_brightness(connector, val);
994
995 panel->backlight.enabled = panel->backlight.level != 0;
996
997 return 0;
998}
999
1000static int i965_setup_backlight(struct intel_connector *connector)
1001{
1002 struct drm_device *dev = connector->base.dev;
1003 struct drm_i915_private *dev_priv = dev->dev_private;
1004 struct intel_panel *panel = &connector->panel;
1005 u32 ctl, ctl2, val;
1006
1007 ctl2 = I915_READ(BLC_PWM_CTL2);
1008 panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE;
1009 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1010
1011 ctl = I915_READ(BLC_PWM_CTL);
1012 panel->backlight.max = ctl >> 16;
1013 if (panel->backlight.combination_mode)
1014 panel->backlight.max *= 0xff;
1015
1016 if (!panel->backlight.max)
1017 return -ENODEV;
1018
1019 val = i9xx_get_backlight(connector);
1020 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1021
1022 panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) &&
1023 panel->backlight.level != 0;
1024
1025 return 0;
1026}
1027
1028static int vlv_setup_backlight(struct intel_connector *connector)
1029{
1030 struct drm_device *dev = connector->base.dev;
1031 struct drm_i915_private *dev_priv = dev->dev_private;
1032 struct intel_panel *panel = &connector->panel;
1033 enum pipe pipe;
1034 u32 ctl, ctl2, val;
1035
1036 for_each_pipe(pipe) {
1037 u32 cur_val = I915_READ(VLV_BLC_PWM_CTL(pipe));
1038
1039 /* Skip if the modulation freq is already set */
1040 if (cur_val & ~BACKLIGHT_DUTY_CYCLE_MASK)
1041 continue;
1042
1043 cur_val &= BACKLIGHT_DUTY_CYCLE_MASK;
1044 I915_WRITE(VLV_BLC_PWM_CTL(pipe), (0xf42 << 16) |
1045 cur_val);
824 } 1046 }
1047
1048 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(PIPE_A));
1049 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1050
1051 ctl = I915_READ(VLV_BLC_PWM_CTL(PIPE_A));
1052 panel->backlight.max = ctl >> 16;
1053 if (!panel->backlight.max)
1054 return -ENODEV;
1055
1056 val = _vlv_get_backlight(dev, PIPE_A);
1057 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1058
1059 panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) &&
1060 panel->backlight.level != 0;
1061
1062 return 0;
825} 1063}
826#else 1064
827int intel_panel_setup_backlight(struct drm_connector *connector) 1065int intel_panel_setup_backlight(struct drm_connector *connector)
828{ 1066{
829 intel_panel_init_backlight(connector->dev); 1067 struct drm_device *dev = connector->dev;
1068 struct drm_i915_private *dev_priv = dev->dev_private;
1069 struct intel_connector *intel_connector = to_intel_connector(connector);
1070 struct intel_panel *panel = &intel_connector->panel;
1071 unsigned long flags;
1072 int ret;
1073
1074 /* set level and max in panel struct */
1075 spin_lock_irqsave(&dev_priv->backlight_lock, flags);
1076 ret = dev_priv->display.setup_backlight(intel_connector);
1077 spin_unlock_irqrestore(&dev_priv->backlight_lock, flags);
1078
1079 if (ret) {
1080 DRM_DEBUG_KMS("failed to setup backlight for connector %s\n",
1081 drm_get_connector_name(connector));
1082 return ret;
1083 }
1084
1085 intel_backlight_device_register(intel_connector);
1086
1087 panel->backlight.present = true;
1088
1089 DRM_DEBUG_KMS("backlight initialized, %s, brightness %u/%u, "
1090 "sysfs interface %sregistered\n",
1091 panel->backlight.enabled ? "enabled" : "disabled",
1092 panel->backlight.level, panel->backlight.max,
1093 panel->backlight.device ? "" : "not ");
1094
830 return 0; 1095 return 0;
831} 1096}
832 1097
833void intel_panel_destroy_backlight(struct drm_device *dev) 1098void intel_panel_destroy_backlight(struct drm_connector *connector)
834{ 1099{
835 return; 1100 struct intel_connector *intel_connector = to_intel_connector(connector);
1101 struct intel_panel *panel = &intel_connector->panel;
1102
1103 panel->backlight.present = false;
1104 intel_backlight_device_unregister(intel_connector);
1105}
1106
1107/* Set up chip specific backlight functions */
1108void intel_panel_init_backlight_funcs(struct drm_device *dev)
1109{
1110 struct drm_i915_private *dev_priv = dev->dev_private;
1111
1112 if (IS_BROADWELL(dev)) {
1113 dev_priv->display.setup_backlight = bdw_setup_backlight;
1114 dev_priv->display.enable_backlight = bdw_enable_backlight;
1115 dev_priv->display.disable_backlight = pch_disable_backlight;
1116 dev_priv->display.set_backlight = bdw_set_backlight;
1117 dev_priv->display.get_backlight = bdw_get_backlight;
1118 } else if (HAS_PCH_SPLIT(dev)) {
1119 dev_priv->display.setup_backlight = pch_setup_backlight;
1120 dev_priv->display.enable_backlight = pch_enable_backlight;
1121 dev_priv->display.disable_backlight = pch_disable_backlight;
1122 dev_priv->display.set_backlight = pch_set_backlight;
1123 dev_priv->display.get_backlight = pch_get_backlight;
1124 } else if (IS_VALLEYVIEW(dev)) {
1125 dev_priv->display.setup_backlight = vlv_setup_backlight;
1126 dev_priv->display.enable_backlight = vlv_enable_backlight;
1127 dev_priv->display.disable_backlight = vlv_disable_backlight;
1128 dev_priv->display.set_backlight = vlv_set_backlight;
1129 dev_priv->display.get_backlight = vlv_get_backlight;
1130 } else if (IS_GEN4(dev)) {
1131 dev_priv->display.setup_backlight = i965_setup_backlight;
1132 dev_priv->display.enable_backlight = i965_enable_backlight;
1133 dev_priv->display.disable_backlight = i965_disable_backlight;
1134 dev_priv->display.set_backlight = i9xx_set_backlight;
1135 dev_priv->display.get_backlight = i9xx_get_backlight;
1136 } else {
1137 dev_priv->display.setup_backlight = i9xx_setup_backlight;
1138 dev_priv->display.enable_backlight = i9xx_enable_backlight;
1139 dev_priv->display.disable_backlight = i9xx_disable_backlight;
1140 dev_priv->display.set_backlight = i9xx_set_backlight;
1141 dev_priv->display.get_backlight = i9xx_get_backlight;
1142 }
836} 1143}
837#endif
838 1144
839int intel_panel_init(struct intel_panel *panel, 1145int intel_panel_init(struct intel_panel *panel,
840 struct drm_display_mode *fixed_mode) 1146 struct drm_display_mode *fixed_mode)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6e0d5e075b15..e6d98fe86b17 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -191,7 +191,11 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
191 u32 blt_ecoskpd; 191 u32 blt_ecoskpd;
192 192
193 /* Make sure blitter notifies FBC of writes */ 193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv); 194
195 /* Blitter is part of Media powerwell on VLV. No impact of
196 * his param in other platforms for now */
197 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA);
198
195 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); 199 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
196 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << 200 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
197 GEN6_BLITTER_LOCK_SHIFT; 201 GEN6_BLITTER_LOCK_SHIFT;
@@ -202,7 +206,8 @@ static void sandybridge_blit_fbc_update(struct drm_device *dev)
202 GEN6_BLITTER_LOCK_SHIFT); 206 GEN6_BLITTER_LOCK_SHIFT);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); 207 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD); 208 POSTING_READ(GEN6_BLITTER_ECOSKPD);
205 gen6_gt_force_wake_put(dev_priv); 209
210 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA);
206} 211}
207 212
208static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval) 213static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -222,7 +227,9 @@ static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
222 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X); 227 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
223 /* Set persistent mode for front-buffer rendering, ala X. */ 228 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE; 229 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
225 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg); 230 dpfc_ctl |= DPFC_CTL_FENCE_EN;
231 if (IS_GEN5(dev))
232 dpfc_ctl |= obj->fence_reg;
226 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY); 233 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
227 234
228 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN | 235 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
@@ -295,7 +302,7 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
295 302
296 sandybridge_blit_fbc_update(dev); 303 sandybridge_blit_fbc_update(dev);
297 304
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane); 305 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
299} 306}
300 307
301bool intel_fbc_enabled(struct drm_device *dev) 308bool intel_fbc_enabled(struct drm_device *dev)
@@ -3430,26 +3437,19 @@ static void ironlake_disable_drps(struct drm_device *dev)
3430 * ourselves, instead of doing a rmw cycle (which might result in us clearing 3437 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3431 * all limits and the gpu stuck at whatever frequency it is at atm). 3438 * all limits and the gpu stuck at whatever frequency it is at atm).
3432 */ 3439 */
3433static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val) 3440static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val)
3434{ 3441{
3435 u32 limits; 3442 u32 limits;
3436 3443
3437 limits = 0;
3438
3439 if (*val >= dev_priv->rps.max_delay)
3440 *val = dev_priv->rps.max_delay;
3441 limits |= dev_priv->rps.max_delay << 24;
3442
3443 /* Only set the down limit when we've reached the lowest level to avoid 3444 /* Only set the down limit when we've reached the lowest level to avoid
3444 * getting more interrupts, otherwise leave this clear. This prevents a 3445 * getting more interrupts, otherwise leave this clear. This prevents a
3445 * race in the hw when coming out of rc6: There's a tiny window where 3446 * race in the hw when coming out of rc6: There's a tiny window where
3446 * the hw runs at the minimal clock before selecting the desired 3447 * the hw runs at the minimal clock before selecting the desired
3447 * frequency, if the down threshold expires in that window we will not 3448 * frequency, if the down threshold expires in that window we will not
3448 * receive a down interrupt. */ 3449 * receive a down interrupt. */
3449 if (*val <= dev_priv->rps.min_delay) { 3450 limits = dev_priv->rps.max_delay << 24;
3450 *val = dev_priv->rps.min_delay; 3451 if (val <= dev_priv->rps.min_delay)
3451 limits |= dev_priv->rps.min_delay << 16; 3452 limits |= dev_priv->rps.min_delay << 16;
3452 }
3453 3453
3454 return limits; 3454 return limits;
3455} 3455}
@@ -3549,7 +3549,6 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3549void gen6_set_rps(struct drm_device *dev, u8 val) 3549void gen6_set_rps(struct drm_device *dev, u8 val)
3550{ 3550{
3551 struct drm_i915_private *dev_priv = dev->dev_private; 3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552 u32 limits = gen6_rps_limits(dev_priv, &val);
3553 3552
3554 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3553 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3555 WARN_ON(val > dev_priv->rps.max_delay); 3554 WARN_ON(val > dev_priv->rps.max_delay);
@@ -3572,7 +3571,8 @@ void gen6_set_rps(struct drm_device *dev, u8 val)
3572 /* Make sure we continue to get interrupts 3571 /* Make sure we continue to get interrupts
3573 * until we hit the minimum or maximum frequencies. 3572 * until we hit the minimum or maximum frequencies.
3574 */ 3573 */
3575 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); 3574 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
3575 gen6_rps_limits(dev_priv, val));
3576 3576
3577 POSTING_READ(GEN6_RPNSWREQ); 3577 POSTING_READ(GEN6_RPNSWREQ);
3578 3578
@@ -3607,48 +3607,18 @@ void gen6_rps_boost(struct drm_i915_private *dev_priv)
3607 mutex_unlock(&dev_priv->rps.hw_lock); 3607 mutex_unlock(&dev_priv->rps.hw_lock);
3608} 3608}
3609 3609
3610/*
3611 * Wait until the previous freq change has completed,
3612 * or the timeout elapsed, and then update our notion
3613 * of the current GPU frequency.
3614 */
3615static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3616{
3617 u32 pval;
3618
3619 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3620
3621 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3622 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
3623
3624 pval >>= 8;
3625
3626 if (pval != dev_priv->rps.cur_delay)
3627 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3628 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3629 dev_priv->rps.cur_delay,
3630 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3631
3632 dev_priv->rps.cur_delay = pval;
3633}
3634
3635void valleyview_set_rps(struct drm_device *dev, u8 val) 3610void valleyview_set_rps(struct drm_device *dev, u8 val)
3636{ 3611{
3637 struct drm_i915_private *dev_priv = dev->dev_private; 3612 struct drm_i915_private *dev_priv = dev->dev_private;
3638 3613
3639 gen6_rps_limits(dev_priv, &val);
3640
3641 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); 3614 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3642 WARN_ON(val > dev_priv->rps.max_delay); 3615 WARN_ON(val > dev_priv->rps.max_delay);
3643 WARN_ON(val < dev_priv->rps.min_delay); 3616 WARN_ON(val < dev_priv->rps.min_delay);
3644 3617
3645 vlv_update_rps_cur_delay(dev_priv);
3646
3647 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", 3618 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3648 vlv_gpu_freq(dev_priv->mem_freq, 3619 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
3649 dev_priv->rps.cur_delay),
3650 dev_priv->rps.cur_delay, 3620 dev_priv->rps.cur_delay,
3651 vlv_gpu_freq(dev_priv->mem_freq, val), val); 3621 vlv_gpu_freq(dev_priv, val), val);
3652 3622
3653 if (val == dev_priv->rps.cur_delay) 3623 if (val == dev_priv->rps.cur_delay)
3654 return; 3624 return;
@@ -3657,7 +3627,7 @@ void valleyview_set_rps(struct drm_device *dev, u8 val)
3657 3627
3658 dev_priv->rps.cur_delay = val; 3628 dev_priv->rps.cur_delay = val;
3659 3629
3660 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); 3630 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val));
3661} 3631}
3662 3632
3663static void gen6_disable_rps_interrupts(struct drm_device *dev) 3633static void gen6_disable_rps_interrupts(struct drm_device *dev)
@@ -3775,7 +3745,7 @@ static void gen8_enable_rps(struct drm_device *dev)
3775 3745
3776 /* 1c & 1d: Get forcewake during program sequence. Although the driver 3746 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3777 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ 3747 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3778 gen6_gt_force_wake_get(dev_priv); 3748 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3779 3749
3780 /* 2a: Disable RC states. */ 3750 /* 2a: Disable RC states. */
3781 I915_WRITE(GEN6_RC_CONTROL, 0); 3751 I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -3832,7 +3802,7 @@ static void gen8_enable_rps(struct drm_device *dev)
3832 3802
3833 gen6_enable_rps_interrupts(dev); 3803 gen6_enable_rps_interrupts(dev);
3834 3804
3835 gen6_gt_force_wake_put(dev_priv); 3805 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3836} 3806}
3837 3807
3838static void gen6_enable_rps(struct drm_device *dev) 3808static void gen6_enable_rps(struct drm_device *dev)
@@ -3862,7 +3832,7 @@ static void gen6_enable_rps(struct drm_device *dev)
3862 I915_WRITE(GTFIFODBG, gtfifodbg); 3832 I915_WRITE(GTFIFODBG, gtfifodbg);
3863 } 3833 }
3864 3834
3865 gen6_gt_force_wake_get(dev_priv); 3835 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
3866 3836
3867 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); 3837 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3868 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); 3838 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
@@ -3954,7 +3924,7 @@ static void gen6_enable_rps(struct drm_device *dev)
3954 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); 3924 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3955 } 3925 }
3956 3926
3957 gen6_gt_force_wake_put(dev_priv); 3927 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
3958} 3928}
3959 3929
3960void gen6_update_ring_freq(struct drm_device *dev) 3930void gen6_update_ring_freq(struct drm_device *dev)
@@ -4116,7 +4086,8 @@ static void valleyview_enable_rps(struct drm_device *dev)
4116 4086
4117 valleyview_setup_pctx(dev); 4087 valleyview_setup_pctx(dev);
4118 4088
4119 gen6_gt_force_wake_get(dev_priv); 4089 /* If VLV, Forcewake all wells, else re-direct to regular path */
4090 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
4120 4091
4121 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); 4092 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4122 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); 4093 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
@@ -4140,7 +4111,7 @@ static void valleyview_enable_rps(struct drm_device *dev)
4140 for_each_ring(ring, dev_priv, i) 4111 for_each_ring(ring, dev_priv, i)
4141 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); 4112 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4142 4113
4143 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350); 4114 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
4144 4115
4145 /* allows RC6 residency counter to work */ 4116 /* allows RC6 residency counter to work */
4146 I915_WRITE(VLV_COUNTER_CONTROL, 4117 I915_WRITE(VLV_COUNTER_CONTROL,
@@ -4148,65 +4119,47 @@ static void valleyview_enable_rps(struct drm_device *dev)
4148 VLV_MEDIA_RC6_COUNT_EN | 4119 VLV_MEDIA_RC6_COUNT_EN |
4149 VLV_RENDER_RC6_COUNT_EN)); 4120 VLV_RENDER_RC6_COUNT_EN));
4150 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) 4121 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4151 rc6_mode = GEN7_RC_CTL_TO_MODE; 4122 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
4152 4123
4153 intel_print_rc6_info(dev, rc6_mode); 4124 intel_print_rc6_info(dev, rc6_mode);
4154 4125
4155 I915_WRITE(GEN6_RC_CONTROL, rc6_mode); 4126 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
4156 4127
4157 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); 4128 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4158 switch ((val >> 6) & 3) {
4159 case 0:
4160 case 1:
4161 dev_priv->mem_freq = 800;
4162 break;
4163 case 2:
4164 dev_priv->mem_freq = 1066;
4165 break;
4166 case 3:
4167 dev_priv->mem_freq = 1333;
4168 break;
4169 }
4170 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
4171 4129
4172 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); 4130 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4173 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); 4131 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4174 4132
4175 dev_priv->rps.cur_delay = (val >> 8) & 0xff; 4133 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
4176 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", 4134 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4177 vlv_gpu_freq(dev_priv->mem_freq, 4135 vlv_gpu_freq(dev_priv, dev_priv->rps.cur_delay),
4178 dev_priv->rps.cur_delay),
4179 dev_priv->rps.cur_delay); 4136 dev_priv->rps.cur_delay);
4180 4137
4181 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv); 4138 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4182 dev_priv->rps.hw_max = dev_priv->rps.max_delay; 4139 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
4183 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", 4140 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4184 vlv_gpu_freq(dev_priv->mem_freq, 4141 vlv_gpu_freq(dev_priv, dev_priv->rps.max_delay),
4185 dev_priv->rps.max_delay),
4186 dev_priv->rps.max_delay); 4142 dev_priv->rps.max_delay);
4187 4143
4188 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv); 4144 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4189 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", 4145 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4190 vlv_gpu_freq(dev_priv->mem_freq, 4146 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4191 dev_priv->rps.rpe_delay),
4192 dev_priv->rps.rpe_delay); 4147 dev_priv->rps.rpe_delay);
4193 4148
4194 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv); 4149 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4195 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", 4150 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4196 vlv_gpu_freq(dev_priv->mem_freq, 4151 vlv_gpu_freq(dev_priv, dev_priv->rps.min_delay),
4197 dev_priv->rps.min_delay),
4198 dev_priv->rps.min_delay); 4152 dev_priv->rps.min_delay);
4199 4153
4200 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", 4154 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4201 vlv_gpu_freq(dev_priv->mem_freq, 4155 vlv_gpu_freq(dev_priv, dev_priv->rps.rpe_delay),
4202 dev_priv->rps.rpe_delay),
4203 dev_priv->rps.rpe_delay); 4156 dev_priv->rps.rpe_delay);
4204 4157
4205 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay); 4158 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
4206 4159
4207 gen6_enable_rps_interrupts(dev); 4160 gen6_enable_rps_interrupts(dev);
4208 4161
4209 gen6_gt_force_wake_put(dev_priv); 4162 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
4210} 4163}
4211 4164
4212void ironlake_teardown_rc6(struct drm_device *dev) 4165void ironlake_teardown_rc6(struct drm_device *dev)
@@ -5463,6 +5416,26 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
5463static void valleyview_init_clock_gating(struct drm_device *dev) 5416static void valleyview_init_clock_gating(struct drm_device *dev)
5464{ 5417{
5465 struct drm_i915_private *dev_priv = dev->dev_private; 5418 struct drm_i915_private *dev_priv = dev->dev_private;
5419 u32 val;
5420
5421 mutex_lock(&dev_priv->rps.hw_lock);
5422 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5423 mutex_unlock(&dev_priv->rps.hw_lock);
5424 switch ((val >> 6) & 3) {
5425 case 0:
5426 dev_priv->mem_freq = 800;
5427 break;
5428 case 1:
5429 dev_priv->mem_freq = 1066;
5430 break;
5431 case 2:
5432 dev_priv->mem_freq = 1333;
5433 break;
5434 case 3:
5435 dev_priv->mem_freq = 1333;
5436 break;
5437 }
5438 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
5466 5439
5467 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); 5440 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
5468 5441
@@ -5642,49 +5615,78 @@ void intel_suspend_hw(struct drm_device *dev)
5642 lpt_suspend_hw(dev); 5615 lpt_suspend_hw(dev);
5643} 5616}
5644 5617
5645static bool is_always_on_power_domain(struct drm_device *dev, 5618#define for_each_power_well(i, power_well, domain_mask, power_domains) \
5646 enum intel_display_power_domain domain) 5619 for (i = 0; \
5647{ 5620 i < (power_domains)->power_well_count && \
5648 unsigned long always_on_domains; 5621 ((power_well) = &(power_domains)->power_wells[i]); \
5649 5622 i++) \
5650 BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK); 5623 if ((power_well)->domains & (domain_mask))
5651 5624
5652 if (IS_BROADWELL(dev)) { 5625#define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5653 always_on_domains = BDW_ALWAYS_ON_POWER_DOMAINS; 5626 for (i = (power_domains)->power_well_count - 1; \
5654 } else if (IS_HASWELL(dev)) { 5627 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5655 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS; 5628 i--) \
5656 } else { 5629 if ((power_well)->domains & (domain_mask))
5657 WARN_ON(1);
5658 return true;
5659 }
5660
5661 return BIT(domain) & always_on_domains;
5662}
5663 5630
5664/** 5631/**
5665 * We should only use the power well if we explicitly asked the hardware to 5632 * We should only use the power well if we explicitly asked the hardware to
5666 * enable it, so check if it's enabled and also check if we've requested it to 5633 * enable it, so check if it's enabled and also check if we've requested it to
5667 * be enabled. 5634 * be enabled.
5668 */ 5635 */
5636static bool hsw_power_well_enabled(struct drm_device *dev,
5637 struct i915_power_well *power_well)
5638{
5639 struct drm_i915_private *dev_priv = dev->dev_private;
5640
5641 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5642 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
5643}
5644
5645bool intel_display_power_enabled_sw(struct drm_device *dev,
5646 enum intel_display_power_domain domain)
5647{
5648 struct drm_i915_private *dev_priv = dev->dev_private;
5649 struct i915_power_domains *power_domains;
5650
5651 power_domains = &dev_priv->power_domains;
5652
5653 return power_domains->domain_use_count[domain];
5654}
5655
5669bool intel_display_power_enabled(struct drm_device *dev, 5656bool intel_display_power_enabled(struct drm_device *dev,
5670 enum intel_display_power_domain domain) 5657 enum intel_display_power_domain domain)
5671{ 5658{
5672 struct drm_i915_private *dev_priv = dev->dev_private; 5659 struct drm_i915_private *dev_priv = dev->dev_private;
5660 struct i915_power_domains *power_domains;
5661 struct i915_power_well *power_well;
5662 bool is_enabled;
5663 int i;
5673 5664
5674 if (!HAS_POWER_WELL(dev)) 5665 power_domains = &dev_priv->power_domains;
5675 return true;
5676 5666
5677 if (is_always_on_power_domain(dev, domain)) 5667 is_enabled = true;
5678 return true;
5679 5668
5680 return I915_READ(HSW_PWR_WELL_DRIVER) == 5669 mutex_lock(&power_domains->lock);
5681 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); 5670 for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
5671 if (power_well->always_on)
5672 continue;
5673
5674 if (!power_well->is_enabled(dev, power_well)) {
5675 is_enabled = false;
5676 break;
5677 }
5678 }
5679 mutex_unlock(&power_domains->lock);
5680
5681 return is_enabled;
5682} 5682}
5683 5683
5684static void __intel_set_power_well(struct drm_device *dev, bool enable) 5684static void hsw_set_power_well(struct drm_device *dev,
5685 struct i915_power_well *power_well, bool enable)
5685{ 5686{
5686 struct drm_i915_private *dev_priv = dev->dev_private; 5687 struct drm_i915_private *dev_priv = dev->dev_private;
5687 bool is_enabled, enable_requested; 5688 bool is_enabled, enable_requested;
5689 unsigned long irqflags;
5688 uint32_t tmp; 5690 uint32_t tmp;
5689 5691
5690 tmp = I915_READ(HSW_PWR_WELL_DRIVER); 5692 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
@@ -5702,9 +5704,24 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
5702 HSW_PWR_WELL_STATE_ENABLED), 20)) 5704 HSW_PWR_WELL_STATE_ENABLED), 20))
5703 DRM_ERROR("Timeout enabling power well\n"); 5705 DRM_ERROR("Timeout enabling power well\n");
5704 } 5706 }
5707
5708 if (IS_BROADWELL(dev)) {
5709 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
5710 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B),
5711 dev_priv->de_irq_mask[PIPE_B]);
5712 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B),
5713 ~dev_priv->de_irq_mask[PIPE_B] |
5714 GEN8_PIPE_VBLANK);
5715 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C),
5716 dev_priv->de_irq_mask[PIPE_C]);
5717 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C),
5718 ~dev_priv->de_irq_mask[PIPE_C] |
5719 GEN8_PIPE_VBLANK);
5720 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C));
5721 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
5722 }
5705 } else { 5723 } else {
5706 if (enable_requested) { 5724 if (enable_requested) {
5707 unsigned long irqflags;
5708 enum pipe p; 5725 enum pipe p;
5709 5726
5710 I915_WRITE(HSW_PWR_WELL_DRIVER, 0); 5727 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
@@ -5731,16 +5748,17 @@ static void __intel_set_power_well(struct drm_device *dev, bool enable)
5731static void __intel_power_well_get(struct drm_device *dev, 5748static void __intel_power_well_get(struct drm_device *dev,
5732 struct i915_power_well *power_well) 5749 struct i915_power_well *power_well)
5733{ 5750{
5734 if (!power_well->count++) 5751 if (!power_well->count++ && power_well->set)
5735 __intel_set_power_well(dev, true); 5752 power_well->set(dev, power_well, true);
5736} 5753}
5737 5754
5738static void __intel_power_well_put(struct drm_device *dev, 5755static void __intel_power_well_put(struct drm_device *dev,
5739 struct i915_power_well *power_well) 5756 struct i915_power_well *power_well)
5740{ 5757{
5741 WARN_ON(!power_well->count); 5758 WARN_ON(!power_well->count);
5742 if (!--power_well->count && i915_disable_power_well) 5759
5743 __intel_set_power_well(dev, false); 5760 if (!--power_well->count && power_well->set && i915_disable_power_well)
5761 power_well->set(dev, power_well, false);
5744} 5762}
5745 5763
5746void intel_display_power_get(struct drm_device *dev, 5764void intel_display_power_get(struct drm_device *dev,
@@ -5748,17 +5766,18 @@ void intel_display_power_get(struct drm_device *dev,
5748{ 5766{
5749 struct drm_i915_private *dev_priv = dev->dev_private; 5767 struct drm_i915_private *dev_priv = dev->dev_private;
5750 struct i915_power_domains *power_domains; 5768 struct i915_power_domains *power_domains;
5751 5769 struct i915_power_well *power_well;
5752 if (!HAS_POWER_WELL(dev)) 5770 int i;
5753 return;
5754
5755 if (is_always_on_power_domain(dev, domain))
5756 return;
5757 5771
5758 power_domains = &dev_priv->power_domains; 5772 power_domains = &dev_priv->power_domains;
5759 5773
5760 mutex_lock(&power_domains->lock); 5774 mutex_lock(&power_domains->lock);
5761 __intel_power_well_get(dev, &power_domains->power_wells[0]); 5775
5776 for_each_power_well(i, power_well, BIT(domain), power_domains)
5777 __intel_power_well_get(dev, power_well);
5778
5779 power_domains->domain_use_count[domain]++;
5780
5762 mutex_unlock(&power_domains->lock); 5781 mutex_unlock(&power_domains->lock);
5763} 5782}
5764 5783
@@ -5767,17 +5786,19 @@ void intel_display_power_put(struct drm_device *dev,
5767{ 5786{
5768 struct drm_i915_private *dev_priv = dev->dev_private; 5787 struct drm_i915_private *dev_priv = dev->dev_private;
5769 struct i915_power_domains *power_domains; 5788 struct i915_power_domains *power_domains;
5770 5789 struct i915_power_well *power_well;
5771 if (!HAS_POWER_WELL(dev)) 5790 int i;
5772 return;
5773
5774 if (is_always_on_power_domain(dev, domain))
5775 return;
5776 5791
5777 power_domains = &dev_priv->power_domains; 5792 power_domains = &dev_priv->power_domains;
5778 5793
5779 mutex_lock(&power_domains->lock); 5794 mutex_lock(&power_domains->lock);
5780 __intel_power_well_put(dev, &power_domains->power_wells[0]); 5795
5796 WARN_ON(!power_domains->domain_use_count[domain]);
5797 power_domains->domain_use_count[domain]--;
5798
5799 for_each_power_well_rev(i, power_well, BIT(domain), power_domains)
5800 __intel_power_well_put(dev, power_well);
5801
5781 mutex_unlock(&power_domains->lock); 5802 mutex_unlock(&power_domains->lock);
5782} 5803}
5783 5804
@@ -5793,10 +5814,7 @@ void i915_request_power_well(void)
5793 5814
5794 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5815 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5795 power_domains); 5816 power_domains);
5796 5817 intel_display_power_get(dev_priv->dev, POWER_DOMAIN_AUDIO);
5797 mutex_lock(&hsw_pwr->lock);
5798 __intel_power_well_get(dev_priv->dev, &hsw_pwr->power_wells[0]);
5799 mutex_unlock(&hsw_pwr->lock);
5800} 5818}
5801EXPORT_SYMBOL_GPL(i915_request_power_well); 5819EXPORT_SYMBOL_GPL(i915_request_power_well);
5802 5820
@@ -5810,24 +5828,71 @@ void i915_release_power_well(void)
5810 5828
5811 dev_priv = container_of(hsw_pwr, struct drm_i915_private, 5829 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5812 power_domains); 5830 power_domains);
5813 5831 intel_display_power_put(dev_priv->dev, POWER_DOMAIN_AUDIO);
5814 mutex_lock(&hsw_pwr->lock);
5815 __intel_power_well_put(dev_priv->dev, &hsw_pwr->power_wells[0]);
5816 mutex_unlock(&hsw_pwr->lock);
5817} 5832}
5818EXPORT_SYMBOL_GPL(i915_release_power_well); 5833EXPORT_SYMBOL_GPL(i915_release_power_well);
5819 5834
5835static struct i915_power_well i9xx_always_on_power_well[] = {
5836 {
5837 .name = "always-on",
5838 .always_on = 1,
5839 .domains = POWER_DOMAIN_MASK,
5840 },
5841};
5842
5843static struct i915_power_well hsw_power_wells[] = {
5844 {
5845 .name = "always-on",
5846 .always_on = 1,
5847 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
5848 },
5849 {
5850 .name = "display",
5851 .domains = POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS,
5852 .is_enabled = hsw_power_well_enabled,
5853 .set = hsw_set_power_well,
5854 },
5855};
5856
5857static struct i915_power_well bdw_power_wells[] = {
5858 {
5859 .name = "always-on",
5860 .always_on = 1,
5861 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
5862 },
5863 {
5864 .name = "display",
5865 .domains = POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS,
5866 .is_enabled = hsw_power_well_enabled,
5867 .set = hsw_set_power_well,
5868 },
5869};
5870
5871#define set_power_wells(power_domains, __power_wells) ({ \
5872 (power_domains)->power_wells = (__power_wells); \
5873 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
5874})
5875
5820int intel_power_domains_init(struct drm_device *dev) 5876int intel_power_domains_init(struct drm_device *dev)
5821{ 5877{
5822 struct drm_i915_private *dev_priv = dev->dev_private; 5878 struct drm_i915_private *dev_priv = dev->dev_private;
5823 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5879 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5824 struct i915_power_well *power_well;
5825 5880
5826 mutex_init(&power_domains->lock); 5881 mutex_init(&power_domains->lock);
5827 hsw_pwr = power_domains;
5828 5882
5829 power_well = &power_domains->power_wells[0]; 5883 /*
5830 power_well->count = 0; 5884 * The enabling order will be from lower to higher indexed wells,
5885 * the disabling order is reversed.
5886 */
5887 if (IS_HASWELL(dev)) {
5888 set_power_wells(power_domains, hsw_power_wells);
5889 hsw_pwr = power_domains;
5890 } else if (IS_BROADWELL(dev)) {
5891 set_power_wells(power_domains, bdw_power_wells);
5892 hsw_pwr = power_domains;
5893 } else {
5894 set_power_wells(power_domains, i9xx_always_on_power_well);
5895 }
5831 5896
5832 return 0; 5897 return 0;
5833} 5898}
@@ -5842,15 +5907,13 @@ static void intel_power_domains_resume(struct drm_device *dev)
5842 struct drm_i915_private *dev_priv = dev->dev_private; 5907 struct drm_i915_private *dev_priv = dev->dev_private;
5843 struct i915_power_domains *power_domains = &dev_priv->power_domains; 5908 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5844 struct i915_power_well *power_well; 5909 struct i915_power_well *power_well;
5845 5910 int i;
5846 if (!HAS_POWER_WELL(dev))
5847 return;
5848 5911
5849 mutex_lock(&power_domains->lock); 5912 mutex_lock(&power_domains->lock);
5850 5913 for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
5851 power_well = &power_domains->power_wells[0]; 5914 if (power_well->set)
5852 __intel_set_power_well(dev, power_well->count > 0); 5915 power_well->set(dev, power_well, power_well->count > 0);
5853 5916 }
5854 mutex_unlock(&power_domains->lock); 5917 mutex_unlock(&power_domains->lock);
5855} 5918}
5856 5919
@@ -5864,13 +5927,13 @@ void intel_power_domains_init_hw(struct drm_device *dev)
5864{ 5927{
5865 struct drm_i915_private *dev_priv = dev->dev_private; 5928 struct drm_i915_private *dev_priv = dev->dev_private;
5866 5929
5867 if (!HAS_POWER_WELL(dev))
5868 return;
5869
5870 /* For now, we need the power well to be always enabled. */ 5930 /* For now, we need the power well to be always enabled. */
5871 intel_display_set_init_power(dev, true); 5931 intel_display_set_init_power(dev, true);
5872 intel_power_domains_resume(dev); 5932 intel_power_domains_resume(dev);
5873 5933
5934 if (!(IS_HASWELL(dev) || IS_BROADWELL(dev)))
5935 return;
5936
5874 /* We're taking over the BIOS, so clear any requests made by it since 5937 /* We're taking over the BIOS, so clear any requests made by it since
5875 * the driver is in charge now. */ 5938 * the driver is in charge now. */
5876 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) 5939 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
@@ -6075,59 +6138,48 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
6075 return 0; 6138 return 0;
6076} 6139}
6077 6140
6078int vlv_gpu_freq(int ddr_freq, int val) 6141int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val)
6079{ 6142{
6080 int mult, base; 6143 int div;
6081 6144
6082 switch (ddr_freq) { 6145 /* 4 x czclk */
6146 switch (dev_priv->mem_freq) {
6083 case 800: 6147 case 800:
6084 mult = 20; 6148 div = 10;
6085 base = 120;
6086 break; 6149 break;
6087 case 1066: 6150 case 1066:
6088 mult = 22; 6151 div = 12;
6089 base = 133;
6090 break; 6152 break;
6091 case 1333: 6153 case 1333:
6092 mult = 21; 6154 div = 16;
6093 base = 125;
6094 break; 6155 break;
6095 default: 6156 default:
6096 return -1; 6157 return -1;
6097 } 6158 }
6098 6159
6099 return ((val - 0xbd) * mult) + base; 6160 return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div);
6100} 6161}
6101 6162
6102int vlv_freq_opcode(int ddr_freq, int val) 6163int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val)
6103{ 6164{
6104 int mult, base; 6165 int mul;
6105 6166
6106 switch (ddr_freq) { 6167 /* 4 x czclk */
6168 switch (dev_priv->mem_freq) {
6107 case 800: 6169 case 800:
6108 mult = 20; 6170 mul = 10;
6109 base = 120;
6110 break; 6171 break;
6111 case 1066: 6172 case 1066:
6112 mult = 22; 6173 mul = 12;
6113 base = 133;
6114 break; 6174 break;
6115 case 1333: 6175 case 1333:
6116 mult = 21; 6176 mul = 16;
6117 base = 125;
6118 break; 6177 break;
6119 default: 6178 default:
6120 return -1; 6179 return -1;
6121 } 6180 }
6122 6181
6123 val /= mult; 6182 return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6;
6124 val -= base / mult;
6125 val += 0xbd;
6126
6127 if (val > 0xea)
6128 val = 0xea;
6129
6130 return val;
6131} 6183}
6132 6184
6133void intel_pm_init(struct drm_device *dev) 6185void intel_pm_init(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index b620337e6d67..e05a0216cd9b 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -285,14 +285,16 @@ static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
285 if (!ring->fbc_dirty) 285 if (!ring->fbc_dirty)
286 return 0; 286 return 0;
287 287
288 ret = intel_ring_begin(ring, 4); 288 ret = intel_ring_begin(ring, 6);
289 if (ret) 289 if (ret)
290 return ret; 290 return ret;
291 intel_ring_emit(ring, MI_NOOP);
292 /* WaFbcNukeOn3DBlt:ivb/hsw */ 291 /* WaFbcNukeOn3DBlt:ivb/hsw */
293 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); 292 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
294 intel_ring_emit(ring, MSG_FBC_REND_STATE); 293 intel_ring_emit(ring, MSG_FBC_REND_STATE);
295 intel_ring_emit(ring, value); 294 intel_ring_emit(ring, value);
295 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | MI_SRM_LRM_GLOBAL_GTT);
296 intel_ring_emit(ring, MSG_FBC_REND_STATE);
297 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
296 intel_ring_advance(ring); 298 intel_ring_advance(ring);
297 299
298 ring->fbc_dirty = false; 300 ring->fbc_dirty = false;
@@ -354,7 +356,7 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring,
354 intel_ring_emit(ring, 0); 356 intel_ring_emit(ring, 0);
355 intel_ring_advance(ring); 357 intel_ring_advance(ring);
356 358
357 if (flush_domains) 359 if (!invalidate_domains && flush_domains)
358 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); 360 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
359 361
360 return 0; 362 return 0;
@@ -436,7 +438,7 @@ static int init_ring_common(struct intel_ring_buffer *ring)
436 int ret = 0; 438 int ret = 0;
437 u32 head; 439 u32 head;
438 440
439 gen6_gt_force_wake_get(dev_priv); 441 gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL);
440 442
441 if (I915_NEED_GFX_HWS(dev)) 443 if (I915_NEED_GFX_HWS(dev))
442 intel_ring_setup_status_page(ring); 444 intel_ring_setup_status_page(ring);
@@ -509,7 +511,7 @@ static int init_ring_common(struct intel_ring_buffer *ring)
509 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); 511 memset(&ring->hangcheck, 0, sizeof(ring->hangcheck));
510 512
511out: 513out:
512 gen6_gt_force_wake_put(dev_priv); 514 gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL);
513 515
514 return ret; 516 return ret;
515} 517}
@@ -965,6 +967,7 @@ void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
965 } else if (IS_GEN6(ring->dev)) { 967 } else if (IS_GEN6(ring->dev)) {
966 mmio = RING_HWS_PGA_GEN6(ring->mmio_base); 968 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
967 } else { 969 } else {
970 /* XXX: gen8 returns to sanity */
968 mmio = RING_HWS_PGA(ring->mmio_base); 971 mmio = RING_HWS_PGA(ring->mmio_base);
969 } 972 }
970 973
@@ -1029,11 +1032,6 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring)
1029 if (!dev->irq_enabled) 1032 if (!dev->irq_enabled)
1030 return false; 1033 return false;
1031 1034
1032 /* It looks like we need to prevent the gt from suspending while waiting
1033 * for an notifiy irq, otherwise irqs seem to get lost on at least the
1034 * blt/bsd rings on ivb. */
1035 gen6_gt_force_wake_get(dev_priv);
1036
1037 spin_lock_irqsave(&dev_priv->irq_lock, flags); 1035 spin_lock_irqsave(&dev_priv->irq_lock, flags);
1038 if (ring->irq_refcount++ == 0) { 1036 if (ring->irq_refcount++ == 0) {
1039 if (HAS_L3_DPF(dev) && ring->id == RCS) 1037 if (HAS_L3_DPF(dev) && ring->id == RCS)
@@ -1065,8 +1063,6 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring)
1065 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask); 1063 ilk_disable_gt_irq(dev_priv, ring->irq_enable_mask);
1066 } 1064 }
1067 spin_unlock_irqrestore(&dev_priv->irq_lock, flags); 1065 spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1068
1069 gen6_gt_force_wake_put(dev_priv);
1070} 1066}
1071 1067
1072static bool 1068static bool
@@ -1837,7 +1833,7 @@ static int gen6_ring_flush(struct intel_ring_buffer *ring,
1837 } 1833 }
1838 intel_ring_advance(ring); 1834 intel_ring_advance(ring);
1839 1835
1840 if (IS_GEN7(dev) && flush) 1836 if (IS_GEN7(dev) && !invalidate && flush)
1841 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); 1837 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1842 1838
1843 return 0; 1839 return 0;
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index a583e8f718a7..2abeab09e883 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -413,23 +413,34 @@ static const struct _sdvo_cmd_name {
413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd, 413static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
414 const void *args, int args_len) 414 const void *args, int args_len)
415{ 415{
416 int i; 416 int i, pos = 0;
417#define BUF_LEN 256
418 char buffer[BUF_LEN];
419
420#define BUF_PRINT(args...) \
421 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
422
417 423
418 DRM_DEBUG_KMS("%s: W: %02X ", 424 for (i = 0; i < args_len; i++) {
419 SDVO_NAME(intel_sdvo), cmd); 425 BUF_PRINT("%02X ", ((u8 *)args)[i]);
420 for (i = 0; i < args_len; i++) 426 }
421 DRM_LOG_KMS("%02X ", ((u8 *)args)[i]); 427 for (; i < 8; i++) {
422 for (; i < 8; i++) 428 BUF_PRINT(" ");
423 DRM_LOG_KMS(" "); 429 }
424 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) { 430 for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
425 if (cmd == sdvo_cmd_names[i].cmd) { 431 if (cmd == sdvo_cmd_names[i].cmd) {
426 DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name); 432 BUF_PRINT("(%s)", sdvo_cmd_names[i].name);
427 break; 433 break;
428 } 434 }
429 } 435 }
430 if (i == ARRAY_SIZE(sdvo_cmd_names)) 436 if (i == ARRAY_SIZE(sdvo_cmd_names)) {
431 DRM_LOG_KMS("(%02X)", cmd); 437 BUF_PRINT("(%02X)", cmd);
432 DRM_LOG_KMS("\n"); 438 }
439 BUG_ON(pos >= BUF_LEN - 1);
440#undef BUF_PRINT
441#undef BUF_LEN
442
443 DRM_DEBUG_KMS("%s: W: %02X %s\n", SDVO_NAME(intel_sdvo), cmd, buffer);
433} 444}
434 445
435static const char *cmd_status_names[] = { 446static const char *cmd_status_names[] = {
@@ -512,9 +523,10 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
512{ 523{
513 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */ 524 u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
514 u8 status; 525 u8 status;
515 int i; 526 int i, pos = 0;
527#define BUF_LEN 256
528 char buffer[BUF_LEN];
516 529
517 DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
518 530
519 /* 531 /*
520 * The documentation states that all commands will be 532 * The documentation states that all commands will be
@@ -551,10 +563,13 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
551 goto log_fail; 563 goto log_fail;
552 } 564 }
553 565
566#define BUF_PRINT(args...) \
567 pos += snprintf(buffer + pos, max_t(int, BUF_LEN - pos, 0), args)
568
554 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP) 569 if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
555 DRM_LOG_KMS("(%s)", cmd_status_names[status]); 570 BUF_PRINT("(%s)", cmd_status_names[status]);
556 else 571 else
557 DRM_LOG_KMS("(??? %d)", status); 572 BUF_PRINT("(??? %d)", status);
558 573
559 if (status != SDVO_CMD_STATUS_SUCCESS) 574 if (status != SDVO_CMD_STATUS_SUCCESS)
560 goto log_fail; 575 goto log_fail;
@@ -565,13 +580,17 @@ static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
565 SDVO_I2C_RETURN_0 + i, 580 SDVO_I2C_RETURN_0 + i,
566 &((u8 *)response)[i])) 581 &((u8 *)response)[i]))
567 goto log_fail; 582 goto log_fail;
568 DRM_LOG_KMS(" %02X", ((u8 *)response)[i]); 583 BUF_PRINT(" %02X", ((u8 *)response)[i]);
569 } 584 }
570 DRM_LOG_KMS("\n"); 585 BUG_ON(pos >= BUF_LEN - 1);
586#undef BUF_PRINT
587#undef BUF_LEN
588
589 DRM_DEBUG_KMS("%s: R: %s\n", SDVO_NAME(intel_sdvo), buffer);
571 return true; 590 return true;
572 591
573log_fail: 592log_fail:
574 DRM_LOG_KMS("... failed\n"); 593 DRM_DEBUG_KMS("%s: R: ... failed\n", SDVO_NAME(intel_sdvo));
575 return false; 594 return false;
576} 595}
577 596
@@ -1517,8 +1536,9 @@ static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
1517 intel_modeset_check_state(connector->dev); 1536 intel_modeset_check_state(connector->dev);
1518} 1537}
1519 1538
1520static int intel_sdvo_mode_valid(struct drm_connector *connector, 1539static enum drm_mode_status
1521 struct drm_display_mode *mode) 1540intel_sdvo_mode_valid(struct drm_connector *connector,
1541 struct drm_display_mode *mode)
1522{ 1542{
1523 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector); 1543 struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
1524 1544
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 9944d8135e87..cc6fbcde7d3d 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -90,6 +90,22 @@ void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
90 mutex_unlock(&dev_priv->dpio_lock); 90 mutex_unlock(&dev_priv->dpio_lock);
91} 91}
92 92
93u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
94{
95 u32 val = 0;
96
97 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
98 PUNIT_OPCODE_REG_READ, reg, &val);
99
100 return val;
101}
102
103void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
104{
105 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
106 PUNIT_OPCODE_REG_WRITE, reg, &val);
107}
108
93u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr) 109u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
94{ 110{
95 u32 val = 0; 111 u32 val = 0;
@@ -160,27 +176,18 @@ void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
160 PUNIT_OPCODE_REG_WRITE, reg, &val); 176 PUNIT_OPCODE_REG_WRITE, reg, &val);
161} 177}
162 178
163static u32 vlv_get_phy_port(enum pipe pipe)
164{
165 u32 port = IOSF_PORT_DPIO;
166
167 WARN_ON ((pipe != PIPE_A) && (pipe != PIPE_B));
168
169 return port;
170}
171
172u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg) 179u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
173{ 180{
174 u32 val = 0; 181 u32 val = 0;
175 182
176 vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), 183 vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
177 DPIO_OPCODE_REG_READ, reg, &val); 184 DPIO_OPCODE_REG_READ, reg, &val);
178 return val; 185 return val;
179} 186}
180 187
181void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val) 188void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
182{ 189{
183 vlv_sideband_rw(dev_priv, DPIO_DEVFN, vlv_get_phy_port(pipe), 190 vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
184 DPIO_OPCODE_REG_WRITE, reg, &val); 191 DPIO_OPCODE_REG_WRITE, reg, &val);
185} 192}
186 193
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index b9fabf826f7d..90a3f6db8288 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -104,6 +104,12 @@ vlv_update_plane(struct drm_plane *dplane, struct drm_crtc *crtc,
104 break; 104 break;
105 } 105 }
106 106
107 /*
108 * Enable gamma to match primary/cursor plane behaviour.
109 * FIXME should be user controllable via propertiesa.
110 */
111 sprctl |= SP_GAMMA_ENABLE;
112
107 if (obj->tiling_mode != I915_TILING_NONE) 113 if (obj->tiling_mode != I915_TILING_NONE)
108 sprctl |= SP_TILED; 114 sprctl |= SP_TILED;
109 115
@@ -257,6 +263,12 @@ ivb_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
257 BUG(); 263 BUG();
258 } 264 }
259 265
266 /*
267 * Enable gamma to match primary/cursor plane behaviour.
268 * FIXME should be user controllable via propertiesa.
269 */
270 sprctl |= SPRITE_GAMMA_ENABLE;
271
260 if (obj->tiling_mode != I915_TILING_NONE) 272 if (obj->tiling_mode != I915_TILING_NONE)
261 sprctl |= SPRITE_TILED; 273 sprctl |= SPRITE_TILED;
262 274
@@ -453,6 +465,12 @@ ilk_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
453 BUG(); 465 BUG();
454 } 466 }
455 467
468 /*
469 * Enable gamma to match primary/cursor plane behaviour.
470 * FIXME should be user controllable via propertiesa.
471 */
472 dvscntr |= DVS_GAMMA_ENABLE;
473
456 if (obj->tiling_mode != I915_TILING_NONE) 474 if (obj->tiling_mode != I915_TILING_NONE)
457 dvscntr |= DVS_TILED; 475 dvscntr |= DVS_TILED;
458 476
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 0b02078a0b84..0db5472b4dcd 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -64,7 +64,8 @@ static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
64 __raw_posting_read(dev_priv, ECOBUS); 64 __raw_posting_read(dev_priv, ECOBUS);
65} 65}
66 66
67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 67static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv,
68 int fw_engine)
68{ 69{
69 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, 70 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0,
70 FORCEWAKE_ACK_TIMEOUT_MS)) 71 FORCEWAKE_ACK_TIMEOUT_MS))
@@ -89,7 +90,8 @@ static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
89 __raw_posting_read(dev_priv, ECOBUS); 90 __raw_posting_read(dev_priv, ECOBUS);
90} 91}
91 92
92static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) 93static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv,
94 int fw_engine)
93{ 95{
94 u32 forcewake_ack; 96 u32 forcewake_ack;
95 97
@@ -121,12 +123,12 @@ static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
121 u32 gtfifodbg; 123 u32 gtfifodbg;
122 124
123 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); 125 gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG);
124 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK, 126 if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg))
125 "MMIO read or write has been dropped %x\n", gtfifodbg)) 127 __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg);
126 __raw_i915_write32(dev_priv, GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
127} 128}
128 129
129static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 130static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv,
131 int fw_engine)
130{ 132{
131 __raw_i915_write32(dev_priv, FORCEWAKE, 0); 133 __raw_i915_write32(dev_priv, FORCEWAKE, 0);
132 /* something from same cacheline, but !FORCEWAKE */ 134 /* something from same cacheline, but !FORCEWAKE */
@@ -134,7 +136,8 @@ static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
134 gen6_gt_check_fifodbg(dev_priv); 136 gen6_gt_check_fifodbg(dev_priv);
135} 137}
136 138
137static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv) 139static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv,
140 int fw_engine)
138{ 141{
139 __raw_i915_write32(dev_priv, FORCEWAKE_MT, 142 __raw_i915_write32(dev_priv, FORCEWAKE_MT,
140 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 143 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
@@ -149,10 +152,10 @@ static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
149 152
150 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { 153 if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
151 int loop = 500; 154 int loop = 500;
152 u32 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); 155 u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
153 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { 156 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
154 udelay(10); 157 udelay(10);
155 fifo = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); 158 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
156 } 159 }
157 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) 160 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
158 ++ret; 161 ++ret;
@@ -171,38 +174,112 @@ static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
171 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); 174 __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV);
172} 175}
173 176
174static void vlv_force_wake_get(struct drm_i915_private *dev_priv) 177static void __vlv_force_wake_get(struct drm_i915_private *dev_priv,
178 int fw_engine)
175{ 179{
176 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0, 180 /* Check for Render Engine */
177 FORCEWAKE_ACK_TIMEOUT_MS)) 181 if (FORCEWAKE_RENDER & fw_engine) {
178 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); 182 if (wait_for_atomic((__raw_i915_read32(dev_priv,
183 FORCEWAKE_ACK_VLV) &
184 FORCEWAKE_KERNEL) == 0,
185 FORCEWAKE_ACK_TIMEOUT_MS))
186 DRM_ERROR("Timed out: Render forcewake old ack to clear.\n");
179 187
180 __raw_i915_write32(dev_priv, FORCEWAKE_VLV, 188 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
181 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); 189 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
182 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
183 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
184 190
185 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL), 191 if (wait_for_atomic((__raw_i915_read32(dev_priv,
186 FORCEWAKE_ACK_TIMEOUT_MS)) 192 FORCEWAKE_ACK_VLV) &
187 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n"); 193 FORCEWAKE_KERNEL),
194 FORCEWAKE_ACK_TIMEOUT_MS))
195 DRM_ERROR("Timed out: waiting for Render to ack.\n");
196 }
188 197
189 if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK_MEDIA_VLV) & 198 /* Check for Media Engine */
190 FORCEWAKE_KERNEL), 199 if (FORCEWAKE_MEDIA & fw_engine) {
191 FORCEWAKE_ACK_TIMEOUT_MS)) 200 if (wait_for_atomic((__raw_i915_read32(dev_priv,
192 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); 201 FORCEWAKE_ACK_MEDIA_VLV) &
202 FORCEWAKE_KERNEL) == 0,
203 FORCEWAKE_ACK_TIMEOUT_MS))
204 DRM_ERROR("Timed out: Media forcewake old ack to clear.\n");
205
206 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
207 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
208
209 if (wait_for_atomic((__raw_i915_read32(dev_priv,
210 FORCEWAKE_ACK_MEDIA_VLV) &
211 FORCEWAKE_KERNEL),
212 FORCEWAKE_ACK_TIMEOUT_MS))
213 DRM_ERROR("Timed out: waiting for media to ack.\n");
214 }
193 215
194 /* WaRsForcewakeWaitTC0:vlv */ 216 /* WaRsForcewakeWaitTC0:vlv */
195 __gen6_gt_wait_for_thread_c0(dev_priv); 217 __gen6_gt_wait_for_thread_c0(dev_priv);
218
196} 219}
197 220
198static void vlv_force_wake_put(struct drm_i915_private *dev_priv) 221static void __vlv_force_wake_put(struct drm_i915_private *dev_priv,
222 int fw_engine)
199{ 223{
200 __raw_i915_write32(dev_priv, FORCEWAKE_VLV, 224
201 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 225 /* Check for Render Engine */
202 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, 226 if (FORCEWAKE_RENDER & fw_engine)
203 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); 227 __raw_i915_write32(dev_priv, FORCEWAKE_VLV,
228 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
229
230
231 /* Check for Media Engine */
232 if (FORCEWAKE_MEDIA & fw_engine)
233 __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV,
234 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
235
204 /* The below doubles as a POSTING_READ */ 236 /* The below doubles as a POSTING_READ */
205 gen6_gt_check_fifodbg(dev_priv); 237 gen6_gt_check_fifodbg(dev_priv);
238
239}
240
241void vlv_force_wake_get(struct drm_i915_private *dev_priv,
242 int fw_engine)
243{
244 unsigned long irqflags;
245
246 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
247 if (FORCEWAKE_RENDER & fw_engine) {
248 if (dev_priv->uncore.fw_rendercount++ == 0)
249 dev_priv->uncore.funcs.force_wake_get(dev_priv,
250 FORCEWAKE_RENDER);
251 }
252 if (FORCEWAKE_MEDIA & fw_engine) {
253 if (dev_priv->uncore.fw_mediacount++ == 0)
254 dev_priv->uncore.funcs.force_wake_get(dev_priv,
255 FORCEWAKE_MEDIA);
256 }
257
258 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
259}
260
261void vlv_force_wake_put(struct drm_i915_private *dev_priv,
262 int fw_engine)
263{
264 unsigned long irqflags;
265
266 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
267
268 if (FORCEWAKE_RENDER & fw_engine) {
269 WARN_ON(dev_priv->uncore.fw_rendercount == 0);
270 if (--dev_priv->uncore.fw_rendercount == 0)
271 dev_priv->uncore.funcs.force_wake_put(dev_priv,
272 FORCEWAKE_RENDER);
273 }
274
275 if (FORCEWAKE_MEDIA & fw_engine) {
276 WARN_ON(dev_priv->uncore.fw_mediacount == 0);
277 if (--dev_priv->uncore.fw_mediacount == 0)
278 dev_priv->uncore.funcs.force_wake_put(dev_priv,
279 FORCEWAKE_MEDIA);
280 }
281
282 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
206} 283}
207 284
208static void gen6_force_wake_work(struct work_struct *work) 285static void gen6_force_wake_work(struct work_struct *work)
@@ -213,7 +290,7 @@ static void gen6_force_wake_work(struct work_struct *work)
213 290
214 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 291 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
215 if (--dev_priv->uncore.forcewake_count == 0) 292 if (--dev_priv->uncore.forcewake_count == 0)
216 dev_priv->uncore.funcs.force_wake_put(dev_priv); 293 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
217 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 294 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
218} 295}
219 296
@@ -281,29 +358,38 @@ void intel_uncore_sanitize(struct drm_device *dev)
281 * be called at the beginning of the sequence followed by a call to 358 * be called at the beginning of the sequence followed by a call to
282 * gen6_gt_force_wake_put() at the end of the sequence. 359 * gen6_gt_force_wake_put() at the end of the sequence.
283 */ 360 */
284void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) 361void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine)
285{ 362{
286 unsigned long irqflags; 363 unsigned long irqflags;
287 364
288 if (!dev_priv->uncore.funcs.force_wake_get) 365 if (!dev_priv->uncore.funcs.force_wake_get)
289 return; 366 return;
290 367
368 /* Redirect to VLV specific routine */
369 if (IS_VALLEYVIEW(dev_priv->dev))
370 return vlv_force_wake_get(dev_priv, fw_engine);
371
291 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 372 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
292 if (dev_priv->uncore.forcewake_count++ == 0) 373 if (dev_priv->uncore.forcewake_count++ == 0)
293 dev_priv->uncore.funcs.force_wake_get(dev_priv); 374 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
294 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 375 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
295} 376}
296 377
297/* 378/*
298 * see gen6_gt_force_wake_get() 379 * see gen6_gt_force_wake_get()
299 */ 380 */
300void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv) 381void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine)
301{ 382{
302 unsigned long irqflags; 383 unsigned long irqflags;
303 384
304 if (!dev_priv->uncore.funcs.force_wake_put) 385 if (!dev_priv->uncore.funcs.force_wake_put)
305 return; 386 return;
306 387
388 /* Redirect to VLV specific routine */
389 if (IS_VALLEYVIEW(dev_priv->dev))
390 return vlv_force_wake_put(dev_priv, fw_engine);
391
392
307 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); 393 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
308 if (--dev_priv->uncore.forcewake_count == 0) { 394 if (--dev_priv->uncore.forcewake_count == 0) {
309 dev_priv->uncore.forcewake_count++; 395 dev_priv->uncore.forcewake_count++;
@@ -379,16 +465,51 @@ gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
379 REG_READ_HEADER(x); \ 465 REG_READ_HEADER(x); \
380 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ 466 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
381 if (dev_priv->uncore.forcewake_count == 0) \ 467 if (dev_priv->uncore.forcewake_count == 0) \
382 dev_priv->uncore.funcs.force_wake_get(dev_priv); \ 468 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
469 FORCEWAKE_ALL); \
383 val = __raw_i915_read##x(dev_priv, reg); \ 470 val = __raw_i915_read##x(dev_priv, reg); \
384 if (dev_priv->uncore.forcewake_count == 0) \ 471 if (dev_priv->uncore.forcewake_count == 0) \
385 dev_priv->uncore.funcs.force_wake_put(dev_priv); \ 472 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
473 FORCEWAKE_ALL); \
474 } else { \
475 val = __raw_i915_read##x(dev_priv, reg); \
476 } \
477 REG_READ_FOOTER; \
478}
479
480#define __vlv_read(x) \
481static u##x \
482vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \
483 unsigned fwengine = 0; \
484 unsigned *fwcount; \
485 REG_READ_HEADER(x); \
486 if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \
487 fwengine = FORCEWAKE_RENDER; \
488 fwcount = &dev_priv->uncore.fw_rendercount; \
489 } \
490 else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \
491 fwengine = FORCEWAKE_MEDIA; \
492 fwcount = &dev_priv->uncore.fw_mediacount; \
493 } \
494 if (fwengine != 0) { \
495 if ((*fwcount)++ == 0) \
496 (dev_priv)->uncore.funcs.force_wake_get(dev_priv, \
497 fwengine); \
498 val = __raw_i915_read##x(dev_priv, reg); \
499 if (--(*fwcount) == 0) \
500 (dev_priv)->uncore.funcs.force_wake_put(dev_priv, \
501 fwengine); \
386 } else { \ 502 } else { \
387 val = __raw_i915_read##x(dev_priv, reg); \ 503 val = __raw_i915_read##x(dev_priv, reg); \
388 } \ 504 } \
389 REG_READ_FOOTER; \ 505 REG_READ_FOOTER; \
390} 506}
391 507
508
509__vlv_read(8)
510__vlv_read(16)
511__vlv_read(32)
512__vlv_read(64)
392__gen6_read(8) 513__gen6_read(8)
393__gen6_read(16) 514__gen6_read(16)
394__gen6_read(32) 515__gen6_read(32)
@@ -402,6 +523,7 @@ __gen4_read(16)
402__gen4_read(32) 523__gen4_read(32)
403__gen4_read(64) 524__gen4_read(64)
404 525
526#undef __vlv_read
405#undef __gen6_read 527#undef __gen6_read
406#undef __gen5_read 528#undef __gen5_read
407#undef __gen4_read 529#undef __gen4_read
@@ -489,11 +611,13 @@ gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace
489 bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \ 611 bool __needs_put = !is_gen8_shadowed(dev_priv, reg); \
490 REG_WRITE_HEADER; \ 612 REG_WRITE_HEADER; \
491 if (__needs_put) { \ 613 if (__needs_put) { \
492 dev_priv->uncore.funcs.force_wake_get(dev_priv); \ 614 dev_priv->uncore.funcs.force_wake_get(dev_priv, \
615 FORCEWAKE_ALL); \
493 } \ 616 } \
494 __raw_i915_write##x(dev_priv, reg, val); \ 617 __raw_i915_write##x(dev_priv, reg, val); \
495 if (__needs_put) { \ 618 if (__needs_put) { \
496 dev_priv->uncore.funcs.force_wake_put(dev_priv); \ 619 dev_priv->uncore.funcs.force_wake_put(dev_priv, \
620 FORCEWAKE_ALL); \
497 } \ 621 } \
498 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ 622 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \
499} 623}
@@ -534,8 +658,8 @@ void intel_uncore_init(struct drm_device *dev)
534 gen6_force_wake_work); 658 gen6_force_wake_work);
535 659
536 if (IS_VALLEYVIEW(dev)) { 660 if (IS_VALLEYVIEW(dev)) {
537 dev_priv->uncore.funcs.force_wake_get = vlv_force_wake_get; 661 dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get;
538 dev_priv->uncore.funcs.force_wake_put = vlv_force_wake_put; 662 dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put;
539 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { 663 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
540 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get; 664 dev_priv->uncore.funcs.force_wake_get = __gen6_gt_force_wake_mt_get;
541 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put; 665 dev_priv->uncore.funcs.force_wake_put = __gen6_gt_force_wake_mt_put;
@@ -552,9 +676,9 @@ void intel_uncore_init(struct drm_device *dev)
552 * forcewake being disabled. 676 * forcewake being disabled.
553 */ 677 */
554 mutex_lock(&dev->struct_mutex); 678 mutex_lock(&dev->struct_mutex);
555 __gen6_gt_force_wake_mt_get(dev_priv); 679 __gen6_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL);
556 ecobus = __raw_i915_read32(dev_priv, ECOBUS); 680 ecobus = __raw_i915_read32(dev_priv, ECOBUS);
557 __gen6_gt_force_wake_mt_put(dev_priv); 681 __gen6_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL);
558 mutex_unlock(&dev->struct_mutex); 682 mutex_unlock(&dev->struct_mutex);
559 683
560 if (ecobus & FORCEWAKE_MT_ENABLE) { 684 if (ecobus & FORCEWAKE_MT_ENABLE) {
@@ -601,10 +725,18 @@ void intel_uncore_init(struct drm_device *dev)
601 dev_priv->uncore.funcs.mmio_writel = gen6_write32; 725 dev_priv->uncore.funcs.mmio_writel = gen6_write32;
602 dev_priv->uncore.funcs.mmio_writeq = gen6_write64; 726 dev_priv->uncore.funcs.mmio_writeq = gen6_write64;
603 } 727 }
604 dev_priv->uncore.funcs.mmio_readb = gen6_read8; 728
605 dev_priv->uncore.funcs.mmio_readw = gen6_read16; 729 if (IS_VALLEYVIEW(dev)) {
606 dev_priv->uncore.funcs.mmio_readl = gen6_read32; 730 dev_priv->uncore.funcs.mmio_readb = vlv_read8;
607 dev_priv->uncore.funcs.mmio_readq = gen6_read64; 731 dev_priv->uncore.funcs.mmio_readw = vlv_read16;
732 dev_priv->uncore.funcs.mmio_readl = vlv_read32;
733 dev_priv->uncore.funcs.mmio_readq = vlv_read64;
734 } else {
735 dev_priv->uncore.funcs.mmio_readb = gen6_read8;
736 dev_priv->uncore.funcs.mmio_readw = gen6_read16;
737 dev_priv->uncore.funcs.mmio_readl = gen6_read32;
738 dev_priv->uncore.funcs.mmio_readq = gen6_read64;
739 }
608 break; 740 break;
609 case 5: 741 case 5:
610 dev_priv->uncore.funcs.mmio_writeb = gen5_write8; 742 dev_priv->uncore.funcs.mmio_writeb = gen5_write8;
@@ -687,6 +819,43 @@ int i915_reg_read_ioctl(struct drm_device *dev,
687 return 0; 819 return 0;
688} 820}
689 821
822int i915_get_reset_stats_ioctl(struct drm_device *dev,
823 void *data, struct drm_file *file)
824{
825 struct drm_i915_private *dev_priv = dev->dev_private;
826 struct drm_i915_reset_stats *args = data;
827 struct i915_ctx_hang_stats *hs;
828 int ret;
829
830 if (args->flags || args->pad)
831 return -EINVAL;
832
833 if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN))
834 return -EPERM;
835
836 ret = mutex_lock_interruptible(&dev->struct_mutex);
837 if (ret)
838 return ret;
839
840 hs = i915_gem_context_get_hang_stats(dev, file, args->ctx_id);
841 if (IS_ERR(hs)) {
842 mutex_unlock(&dev->struct_mutex);
843 return PTR_ERR(hs);
844 }
845
846 if (capable(CAP_SYS_ADMIN))
847 args->reset_count = i915_reset_count(&dev_priv->gpu_error);
848 else
849 args->reset_count = 0;
850
851 args->batch_active = hs->batch_active;
852 args->batch_pending = hs->batch_pending;
853
854 mutex_unlock(&dev->struct_mutex);
855
856 return 0;
857}
858
690static int i965_reset_complete(struct drm_device *dev) 859static int i965_reset_complete(struct drm_device *dev)
691{ 860{
692 u8 gdrst; 861 u8 gdrst;
@@ -770,12 +939,12 @@ static int gen6_do_reset(struct drm_device *dev)
770 939
771 /* If reset with a user forcewake, try to restore, otherwise turn it off */ 940 /* If reset with a user forcewake, try to restore, otherwise turn it off */
772 if (dev_priv->uncore.forcewake_count) 941 if (dev_priv->uncore.forcewake_count)
773 dev_priv->uncore.funcs.force_wake_get(dev_priv); 942 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
774 else 943 else
775 dev_priv->uncore.funcs.force_wake_put(dev_priv); 944 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
776 945
777 /* Restore fifo count */ 946 /* Restore fifo count */
778 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GT_FIFO_FREE_ENTRIES); 947 dev_priv->uncore.fifo_count = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK;
779 948
780 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); 949 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
781 return ret; 950 return ret;
@@ -784,6 +953,7 @@ static int gen6_do_reset(struct drm_device *dev)
784int intel_gpu_reset(struct drm_device *dev) 953int intel_gpu_reset(struct drm_device *dev)
785{ 954{
786 switch (INTEL_INFO(dev)->gen) { 955 switch (INTEL_INFO(dev)->gen) {
956 case 8:
787 case 7: 957 case 7:
788 case 6: return gen6_do_reset(dev); 958 case 6: return gen6_do_reset(dev);
789 case 5: return ironlake_do_reset(dev); 959 case 5: return ironlake_do_reset(dev);
@@ -792,15 +962,6 @@ int intel_gpu_reset(struct drm_device *dev)
792 } 962 }
793} 963}
794 964
795void intel_uncore_clear_errors(struct drm_device *dev)
796{
797 struct drm_i915_private *dev_priv = dev->dev_private;
798
799 /* XXX needs spinlock around caller's grouping */
800 if (HAS_FPGA_DBG_UNCLAIMED(dev))
801 __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
802}
803
804void intel_uncore_check_errors(struct drm_device *dev) 965void intel_uncore_check_errors(struct drm_device *dev)
805{ 966{
806 struct drm_i915_private *dev_priv = dev->dev_private; 967 struct drm_i915_private *dev_priv = dev->dev_private;
diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
index 3a4e97bd8607..52aed893710a 100644
--- a/include/uapi/drm/i915_drm.h
+++ b/include/uapi/drm/i915_drm.h
@@ -222,6 +222,7 @@ typedef struct _drm_i915_sarea {
222#define DRM_I915_GEM_SET_CACHING 0x2f 222#define DRM_I915_GEM_SET_CACHING 0x2f
223#define DRM_I915_GEM_GET_CACHING 0x30 223#define DRM_I915_GEM_GET_CACHING 0x30
224#define DRM_I915_REG_READ 0x31 224#define DRM_I915_REG_READ 0x31
225#define DRM_I915_GET_RESET_STATS 0x32
225 226
226#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) 227#define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
227#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) 228#define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -271,6 +272,7 @@ typedef struct _drm_i915_sarea {
271#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create) 272#define DRM_IOCTL_I915_GEM_CONTEXT_CREATE DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_CREATE, struct drm_i915_gem_context_create)
272#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy) 273#define DRM_IOCTL_I915_GEM_CONTEXT_DESTROY DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_DESTROY, struct drm_i915_gem_context_destroy)
273#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read) 274#define DRM_IOCTL_I915_REG_READ DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_REG_READ, struct drm_i915_reg_read)
275#define DRM_IOCTL_I915_GET_RESET_STATS DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GET_RESET_STATS, struct drm_i915_reset_stats)
274 276
275/* Allow drivers to submit batchbuffers directly to hardware, relying 277/* Allow drivers to submit batchbuffers directly to hardware, relying
276 * on the security mechanisms provided by hardware. 278 * on the security mechanisms provided by hardware.
@@ -1030,4 +1032,21 @@ struct drm_i915_reg_read {
1030 __u64 offset; 1032 __u64 offset;
1031 __u64 val; /* Return value */ 1033 __u64 val; /* Return value */
1032}; 1034};
1035
1036struct drm_i915_reset_stats {
1037 __u32 ctx_id;
1038 __u32 flags;
1039
1040 /* All resets since boot/module reload, for all contexts */
1041 __u32 reset_count;
1042
1043 /* Number of batches lost when active in GPU, for this context */
1044 __u32 batch_active;
1045
1046 /* Number of batches lost pending for execution, for this context */
1047 __u32 batch_pending;
1048
1049 __u32 pad;
1050};
1051
1033#endif /* _UAPI_I915_DRM_H_ */ 1052#endif /* _UAPI_I915_DRM_H_ */
generated by cgit v1.2.2 (git 2.25.0) at 2026-07-22 06:03:10 -0400