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authorBjorn Helgaas <bhelgaas@google.com>2014-01-06 16:43:13 -0500
committerBjorn Helgaas <bhelgaas@google.com>2014-01-07 13:37:18 -0500
commitd3572532993c7e8635ad8e5b50f8f613bf855ee2 (patch)
tree4e6b9b4650bbc60add44d824469b357b831b2264
parentb5e350f919acb8ef6961bc1b62e395f53cea123a (diff)
agp/intel: Use CPU physical address, not bus address, for ioremap()
In i810_setup(), i830_setup(), and i9xx_setup(), we use the result of pci_bus_address() as an argument to ioremap() and to compute gtt_phys_addr. These should use pci_resource_start() instead because we want the CPU physical address, not the bus address. If there were an AGP device behind a host bridge that translated addresses, e.g., a PNP0A08 device with _TRA != 0, this would fix a bug. I'm not aware of any of those, but they are possible. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/char/agp/intel-gtt.c14
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index dd8b66a617dc..ad5da1ffcbe9 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -172,7 +172,7 @@ static void i8xx_destroy_pages(struct page *page)
172#define I810_GTT_ORDER 4 172#define I810_GTT_ORDER 4
173static int i810_setup(void) 173static int i810_setup(void)
174{ 174{
175 u32 reg_addr; 175 phys_addr_t reg_addr;
176 char *gtt_table; 176 char *gtt_table;
177 177
178 /* i81x does not preallocate the gtt. It's always 64kb in size. */ 178 /* i81x does not preallocate the gtt. It's always 64kb in size. */
@@ -181,7 +181,7 @@ static int i810_setup(void)
181 return -ENOMEM; 181 return -ENOMEM;
182 intel_private.i81x_gtt_table = gtt_table; 182 intel_private.i81x_gtt_table = gtt_table;
183 183
184 reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR); 184 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
185 185
186 intel_private.registers = ioremap(reg_addr, KB(64)); 186 intel_private.registers = ioremap(reg_addr, KB(64));
187 if (!intel_private.registers) 187 if (!intel_private.registers)
@@ -782,9 +782,9 @@ EXPORT_SYMBOL(intel_enable_gtt);
782 782
783static int i830_setup(void) 783static int i830_setup(void)
784{ 784{
785 u32 reg_addr; 785 phys_addr_t reg_addr;
786 786
787 reg_addr = pci_bus_address(intel_private.pcidev, I810_MMADR_BAR); 787 reg_addr = pci_resource_start(intel_private.pcidev, I810_MMADR_BAR);
788 788
789 intel_private.registers = ioremap(reg_addr, KB(64)); 789 intel_private.registers = ioremap(reg_addr, KB(64));
790 if (!intel_private.registers) 790 if (!intel_private.registers)
@@ -1102,10 +1102,10 @@ static void i965_write_entry(dma_addr_t addr,
1102 1102
1103static int i9xx_setup(void) 1103static int i9xx_setup(void)
1104{ 1104{
1105 u32 reg_addr; 1105 phys_addr_t reg_addr;
1106 int size = KB(512); 1106 int size = KB(512);
1107 1107
1108 reg_addr = pci_bus_address(intel_private.pcidev, I915_MMADR_BAR); 1108 reg_addr = pci_resource_start(intel_private.pcidev, I915_MMADR_BAR);
1109 1109
1110 intel_private.registers = ioremap(reg_addr, size); 1110 intel_private.registers = ioremap(reg_addr, size);
1111 if (!intel_private.registers) 1111 if (!intel_private.registers)
@@ -1114,7 +1114,7 @@ static int i9xx_setup(void)
1114 switch (INTEL_GTT_GEN) { 1114 switch (INTEL_GTT_GEN) {
1115 case 3: 1115 case 3:
1116 intel_private.gtt_phys_addr = 1116 intel_private.gtt_phys_addr =
1117 pci_bus_address(intel_private.pcidev, I915_PTE_BAR); 1117 pci_resource_start(intel_private.pcidev, I915_PTE_BAR);
1118 break; 1118 break;
1119 case 5: 1119 case 5:
1120 intel_private.gtt_phys_addr = reg_addr + MB(2); 1120 intel_private.gtt_phys_addr = reg_addr + MB(2);