diff options
author | Dave Airlie <airlied@redhat.com> | 2013-08-18 22:55:50 -0400 |
---|---|---|
committer | Dave Airlie <airlied@redhat.com> | 2013-08-18 22:55:50 -0400 |
commit | d2b2c08456d12a9914c87cef479b2ec2ab30337f (patch) | |
tree | dd64a4de083572ab300e149d58d3e0ec8f7da158 | |
parent | e42f5814212079aecd5826dba10588a896ac0862 (diff) | |
parent | d43a93c8d9bc4e0dc0293b6458c077c3c797594f (diff) |
Merge branch 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux
Just two small fixes for radeon. One fixes an array overrun
that can cause garbage to get written to registers on some r7xx boards,
the other is a small UVD fix.
Also one audio regresion
* 'drm-fixes-3.11' of git://people.freedesktop.org/~agd5f/linux:
drm/radeon: fix WREG32_OR macro setting bits in a register
drm/radeon/r7xx: fix copy paste typo in golden register setup
drm/radeon: fix UVD message buffer validation
-rw-r--r-- | drivers/gpu/drm/radeon/radeon.h | 2 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_uvd.c | 8 | ||||
-rw-r--r-- | drivers/gpu/drm/radeon/rv770.c | 12 |
3 files changed, 15 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 274b8e1b889f..9f19259667df 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h | |||
@@ -2163,7 +2163,7 @@ void cik_mm_wdoorbell(struct radeon_device *rdev, u32 offset, u32 v); | |||
2163 | WREG32(reg, tmp_); \ | 2163 | WREG32(reg, tmp_); \ |
2164 | } while (0) | 2164 | } while (0) |
2165 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) | 2165 | #define WREG32_AND(reg, and) WREG32_P(reg, 0, and) |
2166 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~or) | 2166 | #define WREG32_OR(reg, or) WREG32_P(reg, or, ~(or)) |
2167 | #define WREG32_PLL_P(reg, val, mask) \ | 2167 | #define WREG32_PLL_P(reg, val, mask) \ |
2168 | do { \ | 2168 | do { \ |
2169 | uint32_t tmp_ = RREG32_PLL(reg); \ | 2169 | uint32_t tmp_ = RREG32_PLL(reg); \ |
diff --git a/drivers/gpu/drm/radeon/radeon_uvd.c b/drivers/gpu/drm/radeon/radeon_uvd.c index f1c15754e73c..b79f4f5cdd62 100644 --- a/drivers/gpu/drm/radeon/radeon_uvd.c +++ b/drivers/gpu/drm/radeon/radeon_uvd.c | |||
@@ -356,6 +356,14 @@ static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, | |||
356 | return -EINVAL; | 356 | return -EINVAL; |
357 | } | 357 | } |
358 | 358 | ||
359 | if (bo->tbo.sync_obj) { | ||
360 | r = radeon_fence_wait(bo->tbo.sync_obj, false); | ||
361 | if (r) { | ||
362 | DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); | ||
363 | return r; | ||
364 | } | ||
365 | } | ||
366 | |||
359 | r = radeon_bo_kmap(bo, &ptr); | 367 | r = radeon_bo_kmap(bo, &ptr); |
360 | if (r) { | 368 | if (r) { |
361 | DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); | 369 | DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); |
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c index bcc68ec204ad..f5e92cfcc140 100644 --- a/drivers/gpu/drm/radeon/rv770.c +++ b/drivers/gpu/drm/radeon/rv770.c | |||
@@ -744,10 +744,10 @@ static void rv770_init_golden_registers(struct radeon_device *rdev) | |||
744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); | 744 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
745 | radeon_program_register_sequence(rdev, | 745 | radeon_program_register_sequence(rdev, |
746 | rv730_golden_registers, | 746 | rv730_golden_registers, |
747 | (const u32)ARRAY_SIZE(rv770_golden_registers)); | 747 | (const u32)ARRAY_SIZE(rv730_golden_registers)); |
748 | radeon_program_register_sequence(rdev, | 748 | radeon_program_register_sequence(rdev, |
749 | rv730_mgcg_init, | 749 | rv730_mgcg_init, |
750 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); | 750 | (const u32)ARRAY_SIZE(rv730_mgcg_init)); |
751 | break; | 751 | break; |
752 | case CHIP_RV710: | 752 | case CHIP_RV710: |
753 | radeon_program_register_sequence(rdev, | 753 | radeon_program_register_sequence(rdev, |
@@ -758,18 +758,18 @@ static void rv770_init_golden_registers(struct radeon_device *rdev) | |||
758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); | 758 | (const u32)ARRAY_SIZE(r7xx_golden_dyn_gpr_registers)); |
759 | radeon_program_register_sequence(rdev, | 759 | radeon_program_register_sequence(rdev, |
760 | rv710_golden_registers, | 760 | rv710_golden_registers, |
761 | (const u32)ARRAY_SIZE(rv770_golden_registers)); | 761 | (const u32)ARRAY_SIZE(rv710_golden_registers)); |
762 | radeon_program_register_sequence(rdev, | 762 | radeon_program_register_sequence(rdev, |
763 | rv710_mgcg_init, | 763 | rv710_mgcg_init, |
764 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); | 764 | (const u32)ARRAY_SIZE(rv710_mgcg_init)); |
765 | break; | 765 | break; |
766 | case CHIP_RV740: | 766 | case CHIP_RV740: |
767 | radeon_program_register_sequence(rdev, | 767 | radeon_program_register_sequence(rdev, |
768 | rv740_golden_registers, | 768 | rv740_golden_registers, |
769 | (const u32)ARRAY_SIZE(rv770_golden_registers)); | 769 | (const u32)ARRAY_SIZE(rv740_golden_registers)); |
770 | radeon_program_register_sequence(rdev, | 770 | radeon_program_register_sequence(rdev, |
771 | rv740_mgcg_init, | 771 | rv740_mgcg_init, |
772 | (const u32)ARRAY_SIZE(rv770_mgcg_init)); | 772 | (const u32)ARRAY_SIZE(rv740_mgcg_init)); |
773 | break; | 773 | break; |
774 | default: | 774 | default: |
775 | break; | 775 | break; |