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authorThierry Reding <thierry.reding@avionic-design.de>2013-08-09 10:49:19 -0400
committerStephen Warren <swarren@nvidia.com>2013-08-13 14:07:45 -0400
commitd1523b52bff35ea709141abac87dd701559ef290 (patch)
treebc60d26ee1b80ef445e6b3d8ae5546ff4d774ab7
parent734a0f6bb93d6f2c27a2b2976e9da1e31905facd (diff)
PCI: tegra: Move PCIe driver to drivers/pci/host
Move the PCIe driver from arch/arm/mach-tegra into the drivers/pci/host directory. The motivation is to collect various host controller drivers in the same location in order to facilitate refactoring. The Tegra PCIe driver has been largely rewritten, both in order to turn it into a proper platform driver and to add MSI (based on code by Krishna Kishore <kthota@nvidia.com>) as well as device tree support. Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> [swarren, split DT changes into a separate patch in another branch] Signed-off-by: Stephen Warren <swarren@nvidia.com>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt161
-rw-r--r--arch/arm/mach-tegra/Kconfig7
-rw-r--r--arch/arm/mach-tegra/Makefile3
-rw-r--r--arch/arm/mach-tegra/board-harmony-pcie.c89
-rw-r--r--arch/arm/mach-tegra/board.h8
-rw-r--r--arch/arm/mach-tegra/iomap.h3
-rw-r--r--arch/arm/mach-tegra/pcie.c886
-rw-r--r--arch/arm/mach-tegra/tegra.c24
-rw-r--r--drivers/pci/host/Kconfig4
-rw-r--r--drivers/pci/host/Makefile1
-rw-r--r--drivers/pci/host/pci-tegra.c1535
11 files changed, 1703 insertions, 1018 deletions
diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
new file mode 100644
index 000000000000..90c112f671da
--- /dev/null
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra20-pcie.txt
@@ -0,0 +1,161 @@
1NVIDIA Tegra PCIe controller
2
3Required properties:
4- compatible: "nvidia,tegra20-pcie"
5- device_type: Must be "pci"
6- reg: A list of physical base address and length for each set of controller
7 registers. Must contain an entry for each entry in the reg-names property.
8- reg-names: Must include the following entries:
9 "pads": PADS registers
10 "afi": AFI registers
11 "cs": configuration space region
12- interrupts: A list of interrupt outputs of the controller. Must contain an
13 entry for each entry in the interrupt-names property.
14- interrupt-names: Must include the following entries:
15 "intr": The Tegra interrupt that is asserted for controller interrupts
16 "msi": The Tegra interrupt that is asserted when an MSI is received
17- pex-clk-supply: Supply voltage for internal reference clock
18- vdd-supply: Power supply for controller (1.05V)
19- bus-range: Range of bus numbers associated with this controller
20- #address-cells: Address representation for root ports (must be 3)
21 - cell 0 specifies the bus and device numbers of the root port:
22 [23:16]: bus number
23 [15:11]: device number
24 - cell 1 denotes the upper 32 address bits and should be 0
25 - cell 2 contains the lower 32 address bits and is used to translate to the
26 CPU address space
27- #size-cells: Size representation for root ports (must be 2)
28- ranges: Describes the translation of addresses for root ports and standard
29 PCI regions. The entries must be 6 cells each, where the first three cells
30 correspond to the address as described for the #address-cells property
31 above, the fourth cell is the physical CPU address to translate to and the
32 fifth and six cells are as described for the #size-cells property above.
33 - The first two entries are expected to translate the addresses for the root
34 port registers, which are referenced by the assigned-addresses property of
35 the root port nodes (see below).
36 - The remaining entries setup the mapping for the standard I/O, memory and
37 prefetchable PCI regions. The first cell determines the type of region
38 that is setup:
39 - 0x81000000: I/O memory region
40 - 0x82000000: non-prefetchable memory region
41 - 0xc2000000: prefetchable memory region
42 Please refer to the standard PCI bus binding document for a more detailed
43 explanation.
44- clocks: List of clock inputs of the controller. Must contain an entry for
45 each entry in the clock-names property.
46- clock-names: Must include the following entries:
47 "pex": The Tegra clock of that name
48 "afi": The Tegra clock of that name
49 "pcie_xclk": The Tegra clock of that name
50 "pll_e": The Tegra clock of that name
51
52Root ports are defined as subnodes of the PCIe controller node.
53
54Required properties:
55- device_type: Must be "pci"
56- assigned-addresses: Address and size of the port configuration registers
57- reg: PCI bus address of the root port
58- #address-cells: Must be 3
59- #size-cells: Must be 2
60- ranges: Sub-ranges distributed from the PCIe controller node. An empty
61 property is sufficient.
62- nvidia,num-lanes: Number of lanes to use for this port. Valid combinations
63 are:
64 - Root port 0 uses 4 lanes, root port 1 is unused.
65 - Both root ports use 2 lanes.
66
67Example:
68
69SoC DTSI:
70
71 pcie-controller {
72 compatible = "nvidia,tegra20-pcie";
73 device_type = "pci";
74 reg = <0x80003000 0x00000800 /* PADS registers */
75 0x80003800 0x00000200 /* AFI registers */
76 0x90000000 0x10000000>; /* configuration space */
77 reg-names = "pads", "afi", "cs";
78 interrupts = <0 98 0x04 /* controller interrupt */
79 0 99 0x04>; /* MSI interrupt */
80 interrupt-names = "intr", "msi";
81
82 bus-range = <0x00 0xff>;
83 #address-cells = <3>;
84 #size-cells = <2>;
85
86 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
87 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
88 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
89 0x82000000 0 0xa0000000 0xa0000000 0 0x10000000 /* non-prefetchable memory */
90 0xc2000000 0 0xb0000000 0xb0000000 0 0x10000000>; /* prefetchable memory */
91
92 clocks = <&tegra_car 70>, <&tegra_car 72>, <&tegra_car 74>,
93 <&tegra_car 118>;
94 clock-names = "pex", "afi", "pcie_xclk", "pll_e";
95 status = "disabled";
96
97 pci@1,0 {
98 device_type = "pci";
99 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
100 reg = <0x000800 0 0 0 0>;
101 status = "disabled";
102
103 #address-cells = <3>;
104 #size-cells = <2>;
105
106 ranges;
107
108 nvidia,num-lanes = <2>;
109 };
110
111 pci@2,0 {
112 device_type = "pci";
113 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
114 reg = <0x001000 0 0 0 0>;
115 status = "disabled";
116
117 #address-cells = <3>;
118 #size-cells = <2>;
119
120 ranges;
121
122 nvidia,num-lanes = <2>;
123 };
124 };
125
126
127Board DTS:
128
129 pcie-controller {
130 status = "okay";
131
132 vdd-supply = <&pci_vdd_reg>;
133 pex-clk-supply = <&pci_clk_reg>;
134
135 /* root port 00:01.0 */
136 pci@1,0 {
137 status = "okay";
138
139 /* bridge 01:00.0 (optional) */
140 pci@0,0 {
141 reg = <0x010000 0 0 0 0>;
142
143 #address-cells = <3>;
144 #size-cells = <2>;
145
146 device_type = "pci";
147
148 /* endpoint 02:00.0 */
149 pci@0,0 {
150 reg = <0x020000 0 0 0 0>;
151 };
152 };
153 };
154 };
155
156Note that devices on the PCI bus are dynamically discovered using PCI's bus
157enumeration and therefore don't need corresponding device nodes in DT. However
158if a device on the PCI bus provides a non-probeable bus such as I2C or SPI,
159device nodes need to be added in order to allow the bus' children to be
160instantiated at the proper location in the operating system's device tree (as
161illustrated by the optional nodes in the example above).
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index e963db273339..def056493260 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -21,6 +21,8 @@ config ARCH_TEGRA
21 select USB_ULPI if USB_PHY 21 select USB_ULPI if USB_PHY
22 select USB_ULPI_VIEWPORT if USB_PHY 22 select USB_ULPI_VIEWPORT if USB_PHY
23 select USE_OF 23 select USE_OF
24 select MIGHT_HAVE_PCI
25 select ARCH_SUPPORTS_MSI
24 help 26 help
25 This enables support for NVIDIA Tegra based systems. 27 This enables support for NVIDIA Tegra based systems.
26 28
@@ -60,11 +62,6 @@ config ARCH_TEGRA_114_SOC
60 Support for NVIDIA Tegra T114 processor family, based on the 62 Support for NVIDIA Tegra T114 processor family, based on the
61 ARM CortexA15MP CPU 63 ARM CortexA15MP CPU
62 64
63config TEGRA_PCI
64 bool "PCI Express support"
65 depends on ARCH_TEGRA_2x_SOC
66 select PCI
67
68config TEGRA_AHB 65config TEGRA_AHB
69 bool "Enable AHB driver for NVIDIA Tegra SoCs" 66 bool "Enable AHB driver for NVIDIA Tegra SoCs"
70 default y 67 default y
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index f4e70631626f..e7e5f45c6558 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -29,7 +29,6 @@ obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += cpuidle-tegra30.o
29endif 29endif
30obj-$(CONFIG_SMP) += platsmp.o headsmp.o 30obj-$(CONFIG_SMP) += platsmp.o headsmp.o
31obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o 31obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
32obj-$(CONFIG_TEGRA_PCI) += pcie.o
33 32
34obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o 33obj-$(CONFIG_ARCH_TEGRA_114_SOC) += tegra114_speedo.o
35obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o 34obj-$(CONFIG_ARCH_TEGRA_114_SOC) += sleep-tegra30.o
@@ -38,6 +37,4 @@ ifeq ($(CONFIG_CPU_IDLE),y)
38obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o 37obj-$(CONFIG_ARCH_TEGRA_114_SOC) += cpuidle-tegra114.o
39endif 38endif
40 39
41obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-harmony-pcie.o
42
43obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o 40obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += board-paz00.o
diff --git a/arch/arm/mach-tegra/board-harmony-pcie.c b/arch/arm/mach-tegra/board-harmony-pcie.c
deleted file mode 100644
index 035b240b9e15..000000000000
--- a/arch/arm/mach-tegra/board-harmony-pcie.c
+++ /dev/null
@@ -1,89 +0,0 @@
1/*
2 * arch/arm/mach-tegra/board-harmony-pcie.c
3 *
4 * Copyright (C) 2010 CompuLab, Ltd.
5 * Mike Rapoport <mike@compulab.co.il>
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include <linux/kernel.h>
19#include <linux/gpio.h>
20#include <linux/err.h>
21#include <linux/of_gpio.h>
22#include <linux/regulator/consumer.h>
23
24#include <asm/mach-types.h>
25
26#include "board.h"
27
28#ifdef CONFIG_TEGRA_PCI
29
30int __init harmony_pcie_init(void)
31{
32 struct device_node *np;
33 int en_vdd_1v05;
34 struct regulator *regulator = NULL;
35 int err;
36
37 np = of_find_node_by_path("/regulators/regulator@3");
38 if (!np) {
39 pr_err("%s: of_find_node_by_path failed\n", __func__);
40 return -ENODEV;
41 }
42
43 en_vdd_1v05 = of_get_named_gpio(np, "gpio", 0);
44 if (en_vdd_1v05 < 0) {
45 pr_err("%s: of_get_named_gpio failed: %d\n", __func__,
46 en_vdd_1v05);
47 return en_vdd_1v05;
48 }
49
50 err = gpio_request(en_vdd_1v05, "EN_VDD_1V05");
51 if (err) {
52 pr_err("%s: gpio_request failed: %d\n", __func__, err);
53 return err;
54 }
55
56 gpio_direction_output(en_vdd_1v05, 1);
57
58 regulator = regulator_get(NULL, "vdd_ldo0,vddio_pex_clk");
59 if (IS_ERR(regulator)) {
60 err = PTR_ERR(regulator);
61 pr_err("%s: regulator_get failed: %d\n", __func__, err);
62 goto err_reg;
63 }
64
65 err = regulator_enable(regulator);
66 if (err) {
67 pr_err("%s: regulator_enable failed: %d\n", __func__, err);
68 goto err_en;
69 }
70
71 err = tegra_pcie_init(true, true);
72 if (err) {
73 pr_err("%s: tegra_pcie_init failed: %d\n", __func__, err);
74 goto err_pcie;
75 }
76
77 return 0;
78
79err_pcie:
80 regulator_disable(regulator);
81err_en:
82 regulator_put(regulator);
83err_reg:
84 gpio_free(en_vdd_1v05);
85
86 return err;
87}
88
89#endif
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 9a6659fe2dc2..db6810dc0b3d 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -31,7 +31,6 @@ void __init tegra_init_early(void);
31void __init tegra_map_common_io(void); 31void __init tegra_map_common_io(void);
32void __init tegra_init_irq(void); 32void __init tegra_init_irq(void);
33void __init tegra_dt_init_irq(void); 33void __init tegra_dt_init_irq(void);
34int __init tegra_pcie_init(bool init_port0, bool init_port1);
35 34
36void tegra_init_late(void); 35void tegra_init_late(void);
37 36
@@ -48,13 +47,6 @@ int __init tegra_powergate_debugfs_init(void);
48static inline int tegra_powergate_debugfs_init(void) { return 0; } 47static inline int tegra_powergate_debugfs_init(void) { return 0; }
49#endif 48#endif
50 49
51int __init harmony_regulator_init(void);
52#ifdef CONFIG_TEGRA_PCI
53int __init harmony_pcie_init(void);
54#else
55static inline int harmony_pcie_init(void) { return 0; }
56#endif
57
58void __init tegra_paz00_wifikill_init(void); 50void __init tegra_paz00_wifikill_init(void);
59 51
60#endif 52#endif
diff --git a/arch/arm/mach-tegra/iomap.h b/arch/arm/mach-tegra/iomap.h
index aba36291d98c..3f5fa0749bde 100644
--- a/arch/arm/mach-tegra/iomap.h
+++ b/arch/arm/mach-tegra/iomap.h
@@ -286,9 +286,6 @@
286#define IO_APB_VIRT IOMEM(0xFE300000) 286#define IO_APB_VIRT IOMEM(0xFE300000)
287#define IO_APB_SIZE SZ_1M 287#define IO_APB_SIZE SZ_1M
288 288
289#define TEGRA_PCIE_BASE 0x80000000
290#define TEGRA_PCIE_IO_BASE (TEGRA_PCIE_BASE + SZ_4M)
291
292#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz))) 289#define IO_TO_VIRT_BETWEEN(p, st, sz) ((p) >= (st) && (p) < ((st) + (sz)))
293#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst))) 290#define IO_TO_VIRT_XLATE(p, pst, vst) (((p) - (pst) + (vst)))
294 291
diff --git a/arch/arm/mach-tegra/pcie.c b/arch/arm/mach-tegra/pcie.c
deleted file mode 100644
index 46144a19a7e7..000000000000
--- a/arch/arm/mach-tegra/pcie.c
+++ /dev/null
@@ -1,886 +0,0 @@
1/*
2 * arch/arm/mach-tegra/pci.c
3 *
4 * PCIe host controller driver for TEGRA(2) SOCs
5 *
6 * Copyright (c) 2010, CompuLab, Ltd.
7 * Author: Mike Rapoport <mike@compulab.co.il>
8 *
9 * Based on NVIDIA PCIe driver
10 * Copyright (c) 2008-2009, NVIDIA Corporation.
11 *
12 * Bits taken from arch/arm/mach-dove/pcie.c
13 *
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
18 *
19 * This program is distributed in the hope that it will be useful, but WITHOUT
20 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 * more details.
23 *
24 * You should have received a copy of the GNU General Public License along
25 * with this program; if not, write to the Free Software Foundation, Inc.,
26 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
27 */
28
29#include <linux/kernel.h>
30#include <linux/pci.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/clk.h>
34#include <linux/delay.h>
35#include <linux/export.h>
36#include <linux/clk/tegra.h>
37#include <linux/tegra-powergate.h>
38
39#include <asm/sizes.h>
40#include <asm/mach/pci.h>
41
42#include "board.h"
43#include "iomap.h"
44
45/* Hack - need to parse this from DT */
46#define INT_PCIE_INTR 130
47
48/* register definitions */
49#define AFI_OFFSET 0x3800
50#define PADS_OFFSET 0x3000
51#define RP0_OFFSET 0x0000
52#define RP1_OFFSET 0x1000
53
54#define AFI_AXI_BAR0_SZ 0x00
55#define AFI_AXI_BAR1_SZ 0x04
56#define AFI_AXI_BAR2_SZ 0x08
57#define AFI_AXI_BAR3_SZ 0x0c
58#define AFI_AXI_BAR4_SZ 0x10
59#define AFI_AXI_BAR5_SZ 0x14
60
61#define AFI_AXI_BAR0_START 0x18
62#define AFI_AXI_BAR1_START 0x1c
63#define AFI_AXI_BAR2_START 0x20
64#define AFI_AXI_BAR3_START 0x24
65#define AFI_AXI_BAR4_START 0x28
66#define AFI_AXI_BAR5_START 0x2c
67
68#define AFI_FPCI_BAR0 0x30
69#define AFI_FPCI_BAR1 0x34
70#define AFI_FPCI_BAR2 0x38
71#define AFI_FPCI_BAR3 0x3c
72#define AFI_FPCI_BAR4 0x40
73#define AFI_FPCI_BAR5 0x44
74
75#define AFI_CACHE_BAR0_SZ 0x48
76#define AFI_CACHE_BAR0_ST 0x4c
77#define AFI_CACHE_BAR1_SZ 0x50
78#define AFI_CACHE_BAR1_ST 0x54
79
80#define AFI_MSI_BAR_SZ 0x60
81#define AFI_MSI_FPCI_BAR_ST 0x64
82#define AFI_MSI_AXI_BAR_ST 0x68
83
84#define AFI_CONFIGURATION 0xac
85#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
86
87#define AFI_FPCI_ERROR_MASKS 0xb0
88
89#define AFI_INTR_MASK 0xb4
90#define AFI_INTR_MASK_INT_MASK (1 << 0)
91#define AFI_INTR_MASK_MSI_MASK (1 << 8)
92
93#define AFI_INTR_CODE 0xb8
94#define AFI_INTR_CODE_MASK 0xf
95#define AFI_INTR_MASTER_ABORT 4
96#define AFI_INTR_LEGACY 6
97
98#define AFI_INTR_SIGNATURE 0xbc
99#define AFI_SM_INTR_ENABLE 0xc4
100
101#define AFI_AFI_INTR_ENABLE 0xc8
102#define AFI_INTR_EN_INI_SLVERR (1 << 0)
103#define AFI_INTR_EN_INI_DECERR (1 << 1)
104#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
105#define AFI_INTR_EN_TGT_DECERR (1 << 3)
106#define AFI_INTR_EN_TGT_WRERR (1 << 4)
107#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
108#define AFI_INTR_EN_AXI_DECERR (1 << 6)
109#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
110
111#define AFI_PCIE_CONFIG 0x0f8
112#define AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE (1 << 1)
113#define AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE (1 << 2)
114#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
115#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
116#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
117
118#define AFI_FUSE 0x104
119#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
120
121#define AFI_PEX0_CTRL 0x110
122#define AFI_PEX1_CTRL 0x118
123#define AFI_PEX_CTRL_RST (1 << 0)
124#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
125
126#define RP_VEND_XP 0x00000F00
127#define RP_VEND_XP_DL_UP (1 << 30)
128
129#define RP_LINK_CONTROL_STATUS 0x00000090
130#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
131
132#define PADS_CTL_SEL 0x0000009C
133
134#define PADS_CTL 0x000000A0
135#define PADS_CTL_IDDQ_1L (1 << 0)
136#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
137#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
138
139#define PADS_PLL_CTL 0x000000B8
140#define PADS_PLL_CTL_RST_B4SM (1 << 1)
141#define PADS_PLL_CTL_LOCKDET (1 << 8)
142#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
143#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
144#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
145#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
146#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
147#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
148#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
149
150/* PMC access is required for PCIE xclk (un)clamping */
151#define PMC_SCRATCH42 0x144
152#define PMC_SCRATCH42_PCX_CLAMP (1 << 0)
153
154static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
155
156#define pmc_writel(value, reg) \
157 __raw_writel(value, reg_pmc_base + (reg))
158#define pmc_readl(reg) \
159 __raw_readl(reg_pmc_base + (reg))
160
161/*
162 * Tegra2 defines 1GB in the AXI address map for PCIe.
163 *
164 * That address space is split into different regions, with sizes and
165 * offsets as follows:
166 *
167 * 0x80000000 - 0x80003fff - PCI controller registers
168 * 0x80004000 - 0x80103fff - PCI configuration space
169 * 0x80104000 - 0x80203fff - PCI extended configuration space
170 * 0x80203fff - 0x803fffff - unused
171 * 0x80400000 - 0x8040ffff - downstream IO
172 * 0x80410000 - 0x8fffffff - unused
173 * 0x90000000 - 0x9fffffff - non-prefetchable memory
174 * 0xa0000000 - 0xbfffffff - prefetchable memory
175 */
176#define PCIE_REGS_SZ SZ_16K
177#define PCIE_CFG_OFF PCIE_REGS_SZ
178#define PCIE_CFG_SZ SZ_1M
179#define PCIE_EXT_CFG_OFF (PCIE_CFG_SZ + PCIE_CFG_OFF)
180#define PCIE_EXT_CFG_SZ SZ_1M
181#define PCIE_IOMAP_SZ (PCIE_REGS_SZ + PCIE_CFG_SZ + PCIE_EXT_CFG_SZ)
182
183#define MEM_BASE_0 (TEGRA_PCIE_BASE + SZ_256M)
184#define MEM_SIZE_0 SZ_128M
185#define MEM_BASE_1 (MEM_BASE_0 + MEM_SIZE_0)
186#define MEM_SIZE_1 SZ_128M
187#define PREFETCH_MEM_BASE_0 (MEM_BASE_1 + MEM_SIZE_1)
188#define PREFETCH_MEM_SIZE_0 SZ_128M
189#define PREFETCH_MEM_BASE_1 (PREFETCH_MEM_BASE_0 + PREFETCH_MEM_SIZE_0)
190#define PREFETCH_MEM_SIZE_1 SZ_128M
191
192#define PCIE_CONF_BUS(b) ((b) << 16)
193#define PCIE_CONF_DEV(d) ((d) << 11)
194#define PCIE_CONF_FUNC(f) ((f) << 8)
195#define PCIE_CONF_REG(r) \
196 (((r) & ~0x3) | (((r) < 256) ? PCIE_CFG_OFF : PCIE_EXT_CFG_OFF))
197
198struct tegra_pcie_port {
199 int index;
200 u8 root_bus_nr;
201 void __iomem *base;
202
203 bool link_up;
204
205 char mem_space_name[16];
206 char prefetch_space_name[20];
207 struct resource res[2];
208};
209
210struct tegra_pcie_info {
211 struct tegra_pcie_port port[2];
212 int num_ports;
213
214 void __iomem *regs;
215 struct resource res_mmio;
216
217 struct clk *pex_clk;
218 struct clk *afi_clk;
219 struct clk *pcie_xclk;
220 struct clk *pll_e;
221};
222
223static struct tegra_pcie_info tegra_pcie;
224
225static inline void afi_writel(u32 value, unsigned long offset)
226{
227 writel(value, offset + AFI_OFFSET + tegra_pcie.regs);
228}
229
230static inline u32 afi_readl(unsigned long offset)
231{
232 return readl(offset + AFI_OFFSET + tegra_pcie.regs);
233}
234
235static inline void pads_writel(u32 value, unsigned long offset)
236{
237 writel(value, offset + PADS_OFFSET + tegra_pcie.regs);
238}
239
240static inline u32 pads_readl(unsigned long offset)
241{
242 return readl(offset + PADS_OFFSET + tegra_pcie.regs);
243}
244
245static struct tegra_pcie_port *bus_to_port(int bus)
246{
247 int i;
248
249 for (i = tegra_pcie.num_ports - 1; i >= 0; i--) {
250 int rbus = tegra_pcie.port[i].root_bus_nr;
251 if (rbus != -1 && rbus == bus)
252 break;
253 }
254
255 return i >= 0 ? tegra_pcie.port + i : NULL;
256}
257
258static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260{
261 struct tegra_pcie_port *pp = bus_to_port(bus->number);
262 void __iomem *addr;
263
264 if (pp) {
265 if (devfn != 0) {
266 *val = 0xffffffff;
267 return PCIBIOS_DEVICE_NOT_FOUND;
268 }
269
270 addr = pp->base + (where & ~0x3);
271 } else {
272 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
273 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
274 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
275 PCIE_CONF_REG(where));
276 }
277
278 *val = readl(addr);
279
280 if (size == 1)
281 *val = (*val >> (8 * (where & 3))) & 0xff;
282 else if (size == 2)
283 *val = (*val >> (8 * (where & 3))) & 0xffff;
284
285 return PCIBIOS_SUCCESSFUL;
286}
287
288static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
289 int where, int size, u32 val)
290{
291 struct tegra_pcie_port *pp = bus_to_port(bus->number);
292 void __iomem *addr;
293
294 u32 mask;
295 u32 tmp;
296
297 if (pp) {
298 if (devfn != 0)
299 return PCIBIOS_DEVICE_NOT_FOUND;
300
301 addr = pp->base + (where & ~0x3);
302 } else {
303 addr = tegra_pcie.regs + (PCIE_CONF_BUS(bus->number) +
304 PCIE_CONF_DEV(PCI_SLOT(devfn)) +
305 PCIE_CONF_FUNC(PCI_FUNC(devfn)) +
306 PCIE_CONF_REG(where));
307 }
308
309 if (size == 4) {
310 writel(val, addr);
311 return PCIBIOS_SUCCESSFUL;
312 }
313
314 if (size == 2)
315 mask = ~(0xffff << ((where & 0x3) * 8));
316 else if (size == 1)
317 mask = ~(0xff << ((where & 0x3) * 8));
318 else
319 return PCIBIOS_BAD_REGISTER_NUMBER;
320
321 tmp = readl(addr) & mask;
322 tmp |= val << ((where & 0x3) * 8);
323 writel(tmp, addr);
324
325 return PCIBIOS_SUCCESSFUL;
326}
327
328static struct pci_ops tegra_pcie_ops = {
329 .read = tegra_pcie_read_conf,
330 .write = tegra_pcie_write_conf,
331};
332
333static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
334{
335 u16 reg;
336
337 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
338 pci_read_config_word(dev, PCI_COMMAND, &reg);
339 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
340 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
341 pci_write_config_word(dev, PCI_COMMAND, reg);
342 }
343}
344DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
345
346/* Tegra PCIE root complex wrongly reports device class */
347static void tegra_pcie_fixup_class(struct pci_dev *dev)
348{
349 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
350}
351DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
352DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
353
354/* Tegra PCIE requires relaxed ordering */
355static void tegra_pcie_relax_enable(struct pci_dev *dev)
356{
357 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
358}
359DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
360
361static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
362{
363 struct tegra_pcie_port *pp;
364
365 if (nr >= tegra_pcie.num_ports)
366 return 0;
367
368 pp = tegra_pcie.port + nr;
369 pp->root_bus_nr = sys->busnr;
370
371 pci_ioremap_io(nr * SZ_64K, TEGRA_PCIE_IO_BASE);
372
373 /*
374 * IORESOURCE_MEM
375 */
376 snprintf(pp->mem_space_name, sizeof(pp->mem_space_name),
377 "PCIe %d MEM", pp->index);
378 pp->mem_space_name[sizeof(pp->mem_space_name) - 1] = 0;
379 pp->res[0].name = pp->mem_space_name;
380 if (pp->index == 0) {
381 pp->res[0].start = MEM_BASE_0;
382 pp->res[0].end = pp->res[0].start + MEM_SIZE_0 - 1;
383 } else {
384 pp->res[0].start = MEM_BASE_1;
385 pp->res[0].end = pp->res[0].start + MEM_SIZE_1 - 1;
386 }
387 pp->res[0].flags = IORESOURCE_MEM;
388 if (request_resource(&iomem_resource, &pp->res[0]))
389 panic("Request PCIe Memory resource failed\n");
390 pci_add_resource_offset(&sys->resources, &pp->res[0], sys->mem_offset);
391
392 /*
393 * IORESOURCE_MEM | IORESOURCE_PREFETCH
394 */
395 snprintf(pp->prefetch_space_name, sizeof(pp->prefetch_space_name),
396 "PCIe %d PREFETCH MEM", pp->index);
397 pp->prefetch_space_name[sizeof(pp->prefetch_space_name) - 1] = 0;
398 pp->res[1].name = pp->prefetch_space_name;
399 if (pp->index == 0) {
400 pp->res[1].start = PREFETCH_MEM_BASE_0;
401 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_0 - 1;
402 } else {
403 pp->res[1].start = PREFETCH_MEM_BASE_1;
404 pp->res[1].end = pp->res[1].start + PREFETCH_MEM_SIZE_1 - 1;
405 }
406 pp->res[1].flags = IORESOURCE_MEM | IORESOURCE_PREFETCH;
407 if (request_resource(&iomem_resource, &pp->res[1]))
408 panic("Request PCIe Prefetch Memory resource failed\n");
409 pci_add_resource_offset(&sys->resources, &pp->res[1], sys->mem_offset);
410
411 return 1;
412}
413
414static int tegra_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
415{
416 return INT_PCIE_INTR;
417}
418
419static struct pci_bus __init *tegra_pcie_scan_bus(int nr,
420 struct pci_sys_data *sys)
421{
422 struct tegra_pcie_port *pp;
423
424 if (nr >= tegra_pcie.num_ports)
425 return NULL;
426
427 pp = tegra_pcie.port + nr;
428 pp->root_bus_nr = sys->busnr;
429
430 return pci_scan_root_bus(NULL, sys->busnr, &tegra_pcie_ops, sys,
431 &sys->resources);
432}
433
434static struct hw_pci tegra_pcie_hw __initdata = {
435 .nr_controllers = 2,
436 .setup = tegra_pcie_setup,
437 .scan = tegra_pcie_scan_bus,
438 .map_irq = tegra_pcie_map_irq,
439};
440
441
442static irqreturn_t tegra_pcie_isr(int irq, void *arg)
443{
444 const char *err_msg[] = {
445 "Unknown",
446 "AXI slave error",
447 "AXI decode error",
448 "Target abort",
449 "Master abort",
450 "Invalid write",
451 "Response decoding error",
452 "AXI response decoding error",
453 "Transcation timeout",
454 };
455
456 u32 code, signature;
457
458 code = afi_readl(AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
459 signature = afi_readl(AFI_INTR_SIGNATURE);
460 afi_writel(0, AFI_INTR_CODE);
461
462 if (code == AFI_INTR_LEGACY)
463 return IRQ_NONE;
464
465 if (code >= ARRAY_SIZE(err_msg))
466 code = 0;
467
468 /*
469 * do not pollute kernel log with master abort reports since they
470 * happen a lot during enumeration
471 */
472 if (code == AFI_INTR_MASTER_ABORT)
473 pr_debug("PCIE: %s, signature: %08x\n", err_msg[code], signature);
474 else
475 pr_err("PCIE: %s, signature: %08x\n", err_msg[code], signature);
476
477 return IRQ_HANDLED;
478}
479
480static void tegra_pcie_setup_translations(void)
481{
482 u32 fpci_bar;
483 u32 size;
484 u32 axi_address;
485
486 /* Bar 0: config Bar */
487 fpci_bar = ((u32)0xfdff << 16);
488 size = PCIE_CFG_SZ;
489 axi_address = TEGRA_PCIE_BASE + PCIE_CFG_OFF;
490 afi_writel(axi_address, AFI_AXI_BAR0_START);
491 afi_writel(size >> 12, AFI_AXI_BAR0_SZ);
492 afi_writel(fpci_bar, AFI_FPCI_BAR0);
493
494 /* Bar 1: extended config Bar */
495 fpci_bar = ((u32)0xfe1 << 20);
496 size = PCIE_EXT_CFG_SZ;
497 axi_address = TEGRA_PCIE_BASE + PCIE_EXT_CFG_OFF;
498 afi_writel(axi_address, AFI_AXI_BAR1_START);
499 afi_writel(size >> 12, AFI_AXI_BAR1_SZ);
500 afi_writel(fpci_bar, AFI_FPCI_BAR1);
501
502 /* Bar 2: downstream IO bar */
503 fpci_bar = ((__u32)0xfdfc << 16);
504 size = SZ_128K;
505 axi_address = TEGRA_PCIE_IO_BASE;
506 afi_writel(axi_address, AFI_AXI_BAR2_START);
507 afi_writel(size >> 12, AFI_AXI_BAR2_SZ);
508 afi_writel(fpci_bar, AFI_FPCI_BAR2);
509
510 /* Bar 3: prefetchable memory BAR */
511 fpci_bar = (((PREFETCH_MEM_BASE_0 >> 12) & 0x0fffffff) << 4) | 0x1;
512 size = PREFETCH_MEM_SIZE_0 + PREFETCH_MEM_SIZE_1;
513 axi_address = PREFETCH_MEM_BASE_0;
514 afi_writel(axi_address, AFI_AXI_BAR3_START);
515 afi_writel(size >> 12, AFI_AXI_BAR3_SZ);
516 afi_writel(fpci_bar, AFI_FPCI_BAR3);
517
518 /* Bar 4: non prefetchable memory BAR */
519 fpci_bar = (((MEM_BASE_0 >> 12) & 0x0FFFFFFF) << 4) | 0x1;
520 size = MEM_SIZE_0 + MEM_SIZE_1;
521 axi_address = MEM_BASE_0;
522 afi_writel(axi_address, AFI_AXI_BAR4_START);
523 afi_writel(size >> 12, AFI_AXI_BAR4_SZ);
524 afi_writel(fpci_bar, AFI_FPCI_BAR4);
525
526 /* Bar 5: NULL out the remaining BAR as it is not used */
527 fpci_bar = 0;
528 size = 0;
529 axi_address = 0;
530 afi_writel(axi_address, AFI_AXI_BAR5_START);
531 afi_writel(size >> 12, AFI_AXI_BAR5_SZ);
532 afi_writel(fpci_bar, AFI_FPCI_BAR5);
533
534 /* map all upstream transactions as uncached */
535 afi_writel(PHYS_OFFSET, AFI_CACHE_BAR0_ST);
536 afi_writel(0, AFI_CACHE_BAR0_SZ);
537 afi_writel(0, AFI_CACHE_BAR1_ST);
538 afi_writel(0, AFI_CACHE_BAR1_SZ);
539
540 /* No MSI */
541 afi_writel(0, AFI_MSI_FPCI_BAR_ST);
542 afi_writel(0, AFI_MSI_BAR_SZ);
543 afi_writel(0, AFI_MSI_AXI_BAR_ST);
544 afi_writel(0, AFI_MSI_BAR_SZ);
545}
546
547static int tegra_pcie_enable_controller(void)
548{
549 u32 val, reg;
550 int i, timeout;
551
552 /* Enable slot clock and pulse the reset signals */
553 for (i = 0, reg = AFI_PEX0_CTRL; i < 2; i++, reg += 0x8) {
554 val = afi_readl(reg) | AFI_PEX_CTRL_REFCLK_EN;
555 afi_writel(val, reg);
556 val &= ~AFI_PEX_CTRL_RST;
557 afi_writel(val, reg);
558
559 val = afi_readl(reg) | AFI_PEX_CTRL_RST;
560 afi_writel(val, reg);
561 }
562
563 /* Enable dual controller and both ports */
564 val = afi_readl(AFI_PCIE_CONFIG);
565 val &= ~(AFI_PCIE_CONFIG_PCIEC0_DISABLE_DEVICE |
566 AFI_PCIE_CONFIG_PCIEC1_DISABLE_DEVICE |
567 AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK);
568 val |= AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
569 afi_writel(val, AFI_PCIE_CONFIG);
570
571 val = afi_readl(AFI_FUSE) & ~AFI_FUSE_PCIE_T0_GEN2_DIS;
572 afi_writel(val, AFI_FUSE);
573
574 /* Initialze internal PHY, enable up to 16 PCIE lanes */
575 pads_writel(0x0, PADS_CTL_SEL);
576
577 /* override IDDQ to 1 on all 4 lanes */
578 val = pads_readl(PADS_CTL) | PADS_CTL_IDDQ_1L;
579 pads_writel(val, PADS_CTL);
580
581 /*
582 * set up PHY PLL inputs select PLLE output as refclock,
583 * set TX ref sel to div10 (not div5)
584 */
585 val = pads_readl(PADS_PLL_CTL);
586 val &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
587 val |= (PADS_PLL_CTL_REFCLK_INTERNAL_CML | PADS_PLL_CTL_TXCLKREF_DIV10);
588 pads_writel(val, PADS_PLL_CTL);
589
590 /* take PLL out of reset */
591 val = pads_readl(PADS_PLL_CTL) | PADS_PLL_CTL_RST_B4SM;
592 pads_writel(val, PADS_PLL_CTL);
593
594 /*
595 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
596 * This doesn't exist in the documentation
597 */
598 pads_writel(0xfa5cfa5c, 0xc8);
599
600 /* Wait for the PLL to lock */
601 timeout = 300;
602 do {
603 val = pads_readl(PADS_PLL_CTL);
604 usleep_range(1000, 1000);
605 if (--timeout == 0) {
606 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
607 return -EBUSY;
608 }
609 } while (!(val & PADS_PLL_CTL_LOCKDET));
610
611 /* turn off IDDQ override */
612 val = pads_readl(PADS_CTL) & ~PADS_CTL_IDDQ_1L;
613 pads_writel(val, PADS_CTL);
614
615 /* enable TX/RX data */
616 val = pads_readl(PADS_CTL);
617 val |= (PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
618 pads_writel(val, PADS_CTL);
619
620 /* Take the PCIe interface module out of reset */
621 tegra_periph_reset_deassert(tegra_pcie.pcie_xclk);
622
623 /* Finally enable PCIe */
624 val = afi_readl(AFI_CONFIGURATION) | AFI_CONFIGURATION_EN_FPCI;
625 afi_writel(val, AFI_CONFIGURATION);
626
627 val = (AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
628 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
629 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR);
630 afi_writel(val, AFI_AFI_INTR_ENABLE);
631 afi_writel(0xffffffff, AFI_SM_INTR_ENABLE);
632
633 /* FIXME: No MSI for now, only INT */
634 afi_writel(AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
635
636 /* Disable all execptions */
637 afi_writel(0, AFI_FPCI_ERROR_MASKS);
638
639 return 0;
640}
641
642static void tegra_pcie_xclk_clamp(bool clamp)
643{
644 u32 reg;
645
646 reg = pmc_readl(PMC_SCRATCH42) & ~PMC_SCRATCH42_PCX_CLAMP;
647
648 if (clamp)
649 reg |= PMC_SCRATCH42_PCX_CLAMP;
650
651 pmc_writel(reg, PMC_SCRATCH42);
652}
653
654static void tegra_pcie_power_off(void)
655{
656 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
657 tegra_periph_reset_assert(tegra_pcie.afi_clk);
658 tegra_periph_reset_assert(tegra_pcie.pex_clk);
659
660 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
661 tegra_pcie_xclk_clamp(true);
662}
663
664static int tegra_pcie_power_regate(void)
665{
666 int err;
667
668 tegra_pcie_power_off();
669
670 tegra_pcie_xclk_clamp(true);
671
672 tegra_periph_reset_assert(tegra_pcie.pcie_xclk);
673 tegra_periph_reset_assert(tegra_pcie.afi_clk);
674
675 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
676 tegra_pcie.pex_clk);
677 if (err) {
678 pr_err("PCIE: powerup sequence failed: %d\n", err);
679 return err;
680 }
681
682 tegra_periph_reset_deassert(tegra_pcie.afi_clk);
683
684 tegra_pcie_xclk_clamp(false);
685
686 clk_prepare_enable(tegra_pcie.afi_clk);
687 clk_prepare_enable(tegra_pcie.pex_clk);
688 return clk_prepare_enable(tegra_pcie.pll_e);
689}
690
691static int tegra_pcie_clocks_get(void)
692{
693 int err;
694
695 tegra_pcie.pex_clk = clk_get(NULL, "pex");
696 if (IS_ERR(tegra_pcie.pex_clk))
697 return PTR_ERR(tegra_pcie.pex_clk);
698
699 tegra_pcie.afi_clk = clk_get(NULL, "afi");
700 if (IS_ERR(tegra_pcie.afi_clk)) {
701 err = PTR_ERR(tegra_pcie.afi_clk);
702 goto err_afi_clk;
703 }
704
705 tegra_pcie.pcie_xclk = clk_get(NULL, "pcie_xclk");
706 if (IS_ERR(tegra_pcie.pcie_xclk)) {
707 err = PTR_ERR(tegra_pcie.pcie_xclk);
708 goto err_pcie_xclk;
709 }
710
711 tegra_pcie.pll_e = clk_get_sys(NULL, "pll_e");
712 if (IS_ERR(tegra_pcie.pll_e)) {
713 err = PTR_ERR(tegra_pcie.pll_e);
714 goto err_pll_e;
715 }
716
717 return 0;
718
719err_pll_e:
720 clk_put(tegra_pcie.pcie_xclk);
721err_pcie_xclk:
722 clk_put(tegra_pcie.afi_clk);
723err_afi_clk:
724 clk_put(tegra_pcie.pex_clk);
725
726 return err;
727}
728
729static void tegra_pcie_clocks_put(void)
730{
731 clk_put(tegra_pcie.pll_e);
732 clk_put(tegra_pcie.pcie_xclk);
733 clk_put(tegra_pcie.afi_clk);
734 clk_put(tegra_pcie.pex_clk);
735}
736
737static int __init tegra_pcie_get_resources(void)
738{
739 int err;
740
741 err = tegra_pcie_clocks_get();
742 if (err) {
743 pr_err("PCIE: failed to get clocks: %d\n", err);
744 return err;
745 }
746
747 err = tegra_pcie_power_regate();
748 if (err) {
749 pr_err("PCIE: failed to power up: %d\n", err);
750 goto err_pwr_on;
751 }
752
753 tegra_pcie.regs = ioremap_nocache(TEGRA_PCIE_BASE, PCIE_IOMAP_SZ);
754 if (tegra_pcie.regs == NULL) {
755 pr_err("PCIE: Failed to map PCI/AFI registers\n");
756 err = -ENOMEM;
757 goto err_map_reg;
758 }
759
760 err = request_irq(INT_PCIE_INTR, tegra_pcie_isr,
761 IRQF_SHARED, "PCIE", &tegra_pcie);
762 if (err) {
763 pr_err("PCIE: Failed to register IRQ: %d\n", err);
764 goto err_req_io;
765 }
766 set_irq_flags(INT_PCIE_INTR, IRQF_VALID);
767
768 return 0;
769
770err_req_io:
771 iounmap(tegra_pcie.regs);
772err_map_reg:
773 tegra_pcie_power_off();
774err_pwr_on:
775 tegra_pcie_clocks_put();
776
777 return err;
778}
779
780/*
781 * FIXME: If there are no PCIe cards attached, then calling this function
782 * can result in the increase of the bootup time as there are big timeout
783 * loops.
784 */
785#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
786static bool tegra_pcie_check_link(struct tegra_pcie_port *pp, int idx,
787 u32 reset_reg)
788{
789 u32 reg;
790 int retries = 3;
791 int timeout;
792
793 do {
794 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
795 while (timeout) {
796 reg = readl(pp->base + RP_VEND_XP);
797
798 if (reg & RP_VEND_XP_DL_UP)
799 break;
800
801 mdelay(1);
802 timeout--;
803 }
804
805 if (!timeout) {
806 pr_err("PCIE: port %d: link down, retrying\n", idx);
807 goto retry;
808 }
809
810 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
811 while (timeout) {
812 reg = readl(pp->base + RP_LINK_CONTROL_STATUS);
813
814 if (reg & 0x20000000)
815 return true;
816
817 mdelay(1);
818 timeout--;
819 }
820
821retry:
822 /* Pulse the PEX reset */
823 reg = afi_readl(reset_reg) | AFI_PEX_CTRL_RST;
824 afi_writel(reg, reset_reg);
825 mdelay(1);
826 reg = afi_readl(reset_reg) & ~AFI_PEX_CTRL_RST;
827 afi_writel(reg, reset_reg);
828
829 retries--;
830 } while (retries);
831
832 return false;
833}
834
835static void __init tegra_pcie_add_port(int index, u32 offset, u32 reset_reg)
836{
837 struct tegra_pcie_port *pp;
838
839 pp = tegra_pcie.port + tegra_pcie.num_ports;
840
841 pp->index = -1;
842 pp->base = tegra_pcie.regs + offset;
843 pp->link_up = tegra_pcie_check_link(pp, index, reset_reg);
844
845 if (!pp->link_up) {
846 pp->base = NULL;
847 printk(KERN_INFO "PCIE: port %d: link down, ignoring\n", index);
848 return;
849 }
850
851 tegra_pcie.num_ports++;
852 pp->index = index;
853 pp->root_bus_nr = -1;
854 memset(pp->res, 0, sizeof(pp->res));
855}
856
857int __init tegra_pcie_init(bool init_port0, bool init_port1)
858{
859 int err;
860
861 if (!(init_port0 || init_port1))
862 return -ENODEV;
863
864 pcibios_min_mem = 0;
865
866 err = tegra_pcie_get_resources();
867 if (err)
868 return err;
869
870 err = tegra_pcie_enable_controller();
871 if (err)
872 return err;
873
874 /* setup the AFI address translations */
875 tegra_pcie_setup_translations();
876
877 if (init_port0)
878 tegra_pcie_add_port(0, RP0_OFFSET, AFI_PEX0_CTRL);
879
880 if (init_port1)
881 tegra_pcie_add_port(1, RP1_OFFSET, AFI_PEX1_CTRL);
882
883 pci_common_init(&tegra_pcie_hw);
884
885 return 0;
886}
diff --git a/arch/arm/mach-tegra/tegra.c b/arch/arm/mach-tegra/tegra.c
index 0d1e4128d460..fe56fcafdf15 100644
--- a/arch/arm/mach-tegra/tegra.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -116,28 +116,6 @@ out:
116 tegra20_auxdata_lookup, parent); 116 tegra20_auxdata_lookup, parent);
117} 117}
118 118
119static void __init trimslice_init(void)
120{
121#ifdef CONFIG_TEGRA_PCI
122 int ret;
123
124 ret = tegra_pcie_init(true, true);
125 if (ret)
126 pr_err("tegra_pci_init() failed: %d\n", ret);
127#endif
128}
129
130static void __init harmony_init(void)
131{
132#ifdef CONFIG_TEGRA_PCI
133 int ret;
134
135 ret = harmony_pcie_init();
136 if (ret)
137 pr_err("harmony_pcie_init() failed: %d\n", ret);
138#endif
139}
140
141static void __init paz00_init(void) 119static void __init paz00_init(void)
142{ 120{
143 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC)) 121 if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
@@ -148,8 +126,6 @@ static struct {
148 char *machine; 126 char *machine;
149 void (*init)(void); 127 void (*init)(void);
150} board_init_funcs[] = { 128} board_init_funcs[] = {
151 { "compulab,trimslice", trimslice_init },
152 { "nvidia,harmony", harmony_init },
153 { "compal,paz00", paz00_init }, 129 { "compal,paz00", paz00_init },
154}; 130};
155 131
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
index 1184ff6fe864..5f33746c925b 100644
--- a/drivers/pci/host/Kconfig
+++ b/drivers/pci/host/Kconfig
@@ -14,4 +14,8 @@ config PCI_EXYNOS
14 select PCIEPORTBUS 14 select PCIEPORTBUS
15 select PCIE_DW 15 select PCIE_DW
16 16
17config PCI_TEGRA
18 bool "NVIDIA Tegra PCIe controller"
19 depends on ARCH_TEGRA
20
17endmenu 21endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
index 086d8500e849..a733fb0f7856 100644
--- a/drivers/pci/host/Makefile
+++ b/drivers/pci/host/Makefile
@@ -1,2 +1,3 @@
1obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o 1obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
2obj-$(CONFIG_PCIE_DW) += pcie-designware.o 2obj-$(CONFIG_PCIE_DW) += pcie-designware.o
3obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
diff --git a/drivers/pci/host/pci-tegra.c b/drivers/pci/host/pci-tegra.c
new file mode 100644
index 000000000000..a54a01138927
--- /dev/null
+++ b/drivers/pci/host/pci-tegra.c
@@ -0,0 +1,1535 @@
1/*
2 * PCIe host controller driver for TEGRA(2) SOCs
3 *
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 *
10 * Bits taken from arch/arm/mach-dove/pcie.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 */
26
27#include <linux/clk.h>
28#include <linux/clk/tegra.h>
29#include <linux/delay.h>
30#include <linux/export.h>
31#include <linux/interrupt.h>
32#include <linux/irq.h>
33#include <linux/irqdomain.h>
34#include <linux/kernel.h>
35#include <linux/module.h>
36#include <linux/msi.h>
37#include <linux/of_address.h>
38#include <linux/of_pci.h>
39#include <linux/of_platform.h>
40#include <linux/pci.h>
41#include <linux/platform_device.h>
42#include <linux/sizes.h>
43#include <linux/slab.h>
44#include <linux/tegra-powergate.h>
45#include <linux/vmalloc.h>
46#include <linux/regulator/consumer.h>
47
48#include <asm/mach/irq.h>
49#include <asm/mach/map.h>
50#include <asm/mach/pci.h>
51
52#define INT_PCI_MSI_NR (8 * 32)
53#define TEGRA_MAX_PORTS 2
54
55/* register definitions */
56
57#define AFI_AXI_BAR0_SZ 0x00
58#define AFI_AXI_BAR1_SZ 0x04
59#define AFI_AXI_BAR2_SZ 0x08
60#define AFI_AXI_BAR3_SZ 0x0c
61#define AFI_AXI_BAR4_SZ 0x10
62#define AFI_AXI_BAR5_SZ 0x14
63
64#define AFI_AXI_BAR0_START 0x18
65#define AFI_AXI_BAR1_START 0x1c
66#define AFI_AXI_BAR2_START 0x20
67#define AFI_AXI_BAR3_START 0x24
68#define AFI_AXI_BAR4_START 0x28
69#define AFI_AXI_BAR5_START 0x2c
70
71#define AFI_FPCI_BAR0 0x30
72#define AFI_FPCI_BAR1 0x34
73#define AFI_FPCI_BAR2 0x38
74#define AFI_FPCI_BAR3 0x3c
75#define AFI_FPCI_BAR4 0x40
76#define AFI_FPCI_BAR5 0x44
77
78#define AFI_CACHE_BAR0_SZ 0x48
79#define AFI_CACHE_BAR0_ST 0x4c
80#define AFI_CACHE_BAR1_SZ 0x50
81#define AFI_CACHE_BAR1_ST 0x54
82
83#define AFI_MSI_BAR_SZ 0x60
84#define AFI_MSI_FPCI_BAR_ST 0x64
85#define AFI_MSI_AXI_BAR_ST 0x68
86
87#define AFI_MSI_VEC0 0x6c
88#define AFI_MSI_VEC1 0x70
89#define AFI_MSI_VEC2 0x74
90#define AFI_MSI_VEC3 0x78
91#define AFI_MSI_VEC4 0x7c
92#define AFI_MSI_VEC5 0x80
93#define AFI_MSI_VEC6 0x84
94#define AFI_MSI_VEC7 0x88
95
96#define AFI_MSI_EN_VEC0 0x8c
97#define AFI_MSI_EN_VEC1 0x90
98#define AFI_MSI_EN_VEC2 0x94
99#define AFI_MSI_EN_VEC3 0x98
100#define AFI_MSI_EN_VEC4 0x9c
101#define AFI_MSI_EN_VEC5 0xa0
102#define AFI_MSI_EN_VEC6 0xa4
103#define AFI_MSI_EN_VEC7 0xa8
104
105#define AFI_CONFIGURATION 0xac
106#define AFI_CONFIGURATION_EN_FPCI (1 << 0)
107
108#define AFI_FPCI_ERROR_MASKS 0xb0
109
110#define AFI_INTR_MASK 0xb4
111#define AFI_INTR_MASK_INT_MASK (1 << 0)
112#define AFI_INTR_MASK_MSI_MASK (1 << 8)
113
114#define AFI_INTR_CODE 0xb8
115#define AFI_INTR_CODE_MASK 0xf
116#define AFI_INTR_AXI_SLAVE_ERROR 1
117#define AFI_INTR_AXI_DECODE_ERROR 2
118#define AFI_INTR_TARGET_ABORT 3
119#define AFI_INTR_MASTER_ABORT 4
120#define AFI_INTR_INVALID_WRITE 5
121#define AFI_INTR_LEGACY 6
122#define AFI_INTR_FPCI_DECODE_ERROR 7
123
124#define AFI_INTR_SIGNATURE 0xbc
125#define AFI_UPPER_FPCI_ADDRESS 0xc0
126#define AFI_SM_INTR_ENABLE 0xc4
127#define AFI_SM_INTR_INTA_ASSERT (1 << 0)
128#define AFI_SM_INTR_INTB_ASSERT (1 << 1)
129#define AFI_SM_INTR_INTC_ASSERT (1 << 2)
130#define AFI_SM_INTR_INTD_ASSERT (1 << 3)
131#define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
132#define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
133#define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
134#define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
135
136#define AFI_AFI_INTR_ENABLE 0xc8
137#define AFI_INTR_EN_INI_SLVERR (1 << 0)
138#define AFI_INTR_EN_INI_DECERR (1 << 1)
139#define AFI_INTR_EN_TGT_SLVERR (1 << 2)
140#define AFI_INTR_EN_TGT_DECERR (1 << 3)
141#define AFI_INTR_EN_TGT_WRERR (1 << 4)
142#define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
143#define AFI_INTR_EN_AXI_DECERR (1 << 6)
144#define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
145
146#define AFI_PCIE_CONFIG 0x0f8
147#define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
148#define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
149#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
150#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
151#define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
152
153#define AFI_FUSE 0x104
154#define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
155
156#define AFI_PEX0_CTRL 0x110
157#define AFI_PEX1_CTRL 0x118
158#define AFI_PEX_CTRL_RST (1 << 0)
159#define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
160
161#define RP_VEND_XP 0x00000F00
162#define RP_VEND_XP_DL_UP (1 << 30)
163
164#define RP_LINK_CONTROL_STATUS 0x00000090
165#define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
166#define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
167
168#define PADS_CTL_SEL 0x0000009C
169
170#define PADS_CTL 0x000000A0
171#define PADS_CTL_IDDQ_1L (1 << 0)
172#define PADS_CTL_TX_DATA_EN_1L (1 << 6)
173#define PADS_CTL_RX_DATA_EN_1L (1 << 10)
174
175#define PADS_PLL_CTL 0x000000B8
176#define PADS_PLL_CTL_RST_B4SM (1 << 1)
177#define PADS_PLL_CTL_LOCKDET (1 << 8)
178#define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
179#define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
180#define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
181#define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
182#define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
183#define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
184#define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
185
186struct tegra_msi {
187 struct msi_chip chip;
188 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
189 struct irq_domain *domain;
190 unsigned long pages;
191 struct mutex lock;
192 int irq;
193};
194
195static inline struct tegra_msi *to_tegra_msi(struct msi_chip *chip)
196{
197 return container_of(chip, struct tegra_msi, chip);
198}
199
200struct tegra_pcie {
201 struct device *dev;
202
203 void __iomem *pads;
204 void __iomem *afi;
205 int irq;
206
207 struct list_head busses;
208 struct resource *cs;
209
210 struct resource io;
211 struct resource mem;
212 struct resource prefetch;
213 struct resource busn;
214
215 struct clk *pex_clk;
216 struct clk *afi_clk;
217 struct clk *pcie_xclk;
218 struct clk *pll_e;
219
220 struct tegra_msi msi;
221
222 struct list_head ports;
223 unsigned int num_ports;
224 u32 xbar_config;
225
226 struct regulator *pex_clk_supply;
227 struct regulator *vdd_supply;
228};
229
230struct tegra_pcie_port {
231 struct tegra_pcie *pcie;
232 struct list_head list;
233 struct resource regs;
234 void __iomem *base;
235 unsigned int index;
236 unsigned int lanes;
237};
238
239struct tegra_pcie_bus {
240 struct vm_struct *area;
241 struct list_head list;
242 unsigned int nr;
243};
244
245static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
246{
247 return sys->private_data;
248}
249
250static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
251 unsigned long offset)
252{
253 writel(value, pcie->afi + offset);
254}
255
256static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
257{
258 return readl(pcie->afi + offset);
259}
260
261static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
262 unsigned long offset)
263{
264 writel(value, pcie->pads + offset);
265}
266
267static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
268{
269 return readl(pcie->pads + offset);
270}
271
272/*
273 * The configuration space mapping on Tegra is somewhat similar to the ECAM
274 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
275 * register accesses are mapped:
276 *
277 * [27:24] extended register number
278 * [23:16] bus number
279 * [15:11] device number
280 * [10: 8] function number
281 * [ 7: 0] register number
282 *
283 * Mapping the whole extended configuration space would require 256 MiB of
284 * virtual address space, only a small part of which will actually be used.
285 * To work around this, a 1 MiB of virtual addresses are allocated per bus
286 * when the bus is first accessed. When the physical range is mapped, the
287 * the bus number bits are hidden so that the extended register number bits
288 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
289 *
290 * [19:16] extended register number
291 * [15:11] device number
292 * [10: 8] function number
293 * [ 7: 0] register number
294 *
295 * This is achieved by stitching together 16 chunks of 64 KiB of physical
296 * address space via the MMU.
297 */
298static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
299{
300 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
301 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
302}
303
304static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
305 unsigned int busnr)
306{
307 pgprot_t prot = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | L_PTE_XN |
308 L_PTE_MT_DEV_SHARED | L_PTE_SHARED;
309 phys_addr_t cs = pcie->cs->start;
310 struct tegra_pcie_bus *bus;
311 unsigned int i;
312 int err;
313
314 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
315 if (!bus)
316 return ERR_PTR(-ENOMEM);
317
318 INIT_LIST_HEAD(&bus->list);
319 bus->nr = busnr;
320
321 /* allocate 1 MiB of virtual addresses */
322 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
323 if (!bus->area) {
324 err = -ENOMEM;
325 goto free;
326 }
327
328 /* map each of the 16 chunks of 64 KiB each */
329 for (i = 0; i < 16; i++) {
330 unsigned long virt = (unsigned long)bus->area->addr +
331 i * SZ_64K;
332 phys_addr_t phys = cs + i * SZ_1M + busnr * SZ_64K;
333
334 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
335 if (err < 0) {
336 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
337 err);
338 goto unmap;
339 }
340 }
341
342 return bus;
343
344unmap:
345 vunmap(bus->area->addr);
346free:
347 kfree(bus);
348 return ERR_PTR(err);
349}
350
351/*
352 * Look up a virtual address mapping for the specified bus number. If no such
353 * mapping existis, try to create one.
354 */
355static void __iomem *tegra_pcie_bus_map(struct tegra_pcie *pcie,
356 unsigned int busnr)
357{
358 struct tegra_pcie_bus *bus;
359
360 list_for_each_entry(bus, &pcie->busses, list)
361 if (bus->nr == busnr)
362 return bus->area->addr;
363
364 bus = tegra_pcie_bus_alloc(pcie, busnr);
365 if (IS_ERR(bus))
366 return NULL;
367
368 list_add_tail(&bus->list, &pcie->busses);
369
370 return bus->area->addr;
371}
372
373static void __iomem *tegra_pcie_conf_address(struct pci_bus *bus,
374 unsigned int devfn,
375 int where)
376{
377 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
378 void __iomem *addr = NULL;
379
380 if (bus->number == 0) {
381 unsigned int slot = PCI_SLOT(devfn);
382 struct tegra_pcie_port *port;
383
384 list_for_each_entry(port, &pcie->ports, list) {
385 if (port->index + 1 == slot) {
386 addr = port->base + (where & ~3);
387 break;
388 }
389 }
390 } else {
391 addr = tegra_pcie_bus_map(pcie, bus->number);
392 if (!addr) {
393 dev_err(pcie->dev,
394 "failed to map cfg. space for bus %u\n",
395 bus->number);
396 return NULL;
397 }
398
399 addr += tegra_pcie_conf_offset(devfn, where);
400 }
401
402 return addr;
403}
404
405static int tegra_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
406 int where, int size, u32 *value)
407{
408 void __iomem *addr;
409
410 addr = tegra_pcie_conf_address(bus, devfn, where);
411 if (!addr) {
412 *value = 0xffffffff;
413 return PCIBIOS_DEVICE_NOT_FOUND;
414 }
415
416 *value = readl(addr);
417
418 if (size == 1)
419 *value = (*value >> (8 * (where & 3))) & 0xff;
420 else if (size == 2)
421 *value = (*value >> (8 * (where & 3))) & 0xffff;
422
423 return PCIBIOS_SUCCESSFUL;
424}
425
426static int tegra_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
427 int where, int size, u32 value)
428{
429 void __iomem *addr;
430 u32 mask, tmp;
431
432 addr = tegra_pcie_conf_address(bus, devfn, where);
433 if (!addr)
434 return PCIBIOS_DEVICE_NOT_FOUND;
435
436 if (size == 4) {
437 writel(value, addr);
438 return PCIBIOS_SUCCESSFUL;
439 }
440
441 if (size == 2)
442 mask = ~(0xffff << ((where & 0x3) * 8));
443 else if (size == 1)
444 mask = ~(0xff << ((where & 0x3) * 8));
445 else
446 return PCIBIOS_BAD_REGISTER_NUMBER;
447
448 tmp = readl(addr) & mask;
449 tmp |= value << ((where & 0x3) * 8);
450 writel(tmp, addr);
451
452 return PCIBIOS_SUCCESSFUL;
453}
454
455static struct pci_ops tegra_pcie_ops = {
456 .read = tegra_pcie_read_conf,
457 .write = tegra_pcie_write_conf,
458};
459
460static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
461{
462 unsigned long ret = 0;
463
464 switch (port->index) {
465 case 0:
466 ret = AFI_PEX0_CTRL;
467 break;
468
469 case 1:
470 ret = AFI_PEX1_CTRL;
471 break;
472 }
473
474 return ret;
475}
476
477static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
478{
479 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
480 unsigned long value;
481
482 /* pulse reset signal */
483 value = afi_readl(port->pcie, ctrl);
484 value &= ~AFI_PEX_CTRL_RST;
485 afi_writel(port->pcie, value, ctrl);
486
487 usleep_range(1000, 2000);
488
489 value = afi_readl(port->pcie, ctrl);
490 value |= AFI_PEX_CTRL_RST;
491 afi_writel(port->pcie, value, ctrl);
492}
493
494static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
495{
496 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
497 unsigned long value;
498
499 /* enable reference clock */
500 value = afi_readl(port->pcie, ctrl);
501 value |= AFI_PEX_CTRL_REFCLK_EN;
502 afi_writel(port->pcie, value, ctrl);
503
504 tegra_pcie_port_reset(port);
505}
506
507static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
508{
509 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
510 unsigned long value;
511
512 /* assert port reset */
513 value = afi_readl(port->pcie, ctrl);
514 value &= ~AFI_PEX_CTRL_RST;
515 afi_writel(port->pcie, value, ctrl);
516
517 /* disable reference clock */
518 value = afi_readl(port->pcie, ctrl);
519 value &= ~AFI_PEX_CTRL_REFCLK_EN;
520 afi_writel(port->pcie, value, ctrl);
521}
522
523static void tegra_pcie_port_free(struct tegra_pcie_port *port)
524{
525 struct tegra_pcie *pcie = port->pcie;
526
527 devm_iounmap(pcie->dev, port->base);
528 devm_release_mem_region(pcie->dev, port->regs.start,
529 resource_size(&port->regs));
530 list_del(&port->list);
531 devm_kfree(pcie->dev, port);
532}
533
534static void tegra_pcie_fixup_bridge(struct pci_dev *dev)
535{
536 u16 reg;
537
538 if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE) {
539 pci_read_config_word(dev, PCI_COMMAND, &reg);
540 reg |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
541 PCI_COMMAND_MASTER | PCI_COMMAND_SERR);
542 pci_write_config_word(dev, PCI_COMMAND, reg);
543 }
544}
545DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_fixup_bridge);
546
547/* Tegra PCIE root complex wrongly reports device class */
548static void tegra_pcie_fixup_class(struct pci_dev *dev)
549{
550 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
551}
552DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
553DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
554
555/* Tegra PCIE requires relaxed ordering */
556static void tegra_pcie_relax_enable(struct pci_dev *dev)
557{
558 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
559}
560DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
561
562static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
563{
564 struct tegra_pcie *pcie = sys_to_pcie(sys);
565
566 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
567 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
568 sys->mem_offset);
569 pci_add_resource(&sys->resources, &pcie->busn);
570
571 pci_ioremap_io(nr * SZ_64K, pcie->io.start);
572
573 return 1;
574}
575
576static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
577{
578 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
579
580 return pcie->irq;
581}
582
583static void tegra_pcie_add_bus(struct pci_bus *bus)
584{
585 if (IS_ENABLED(CONFIG_PCI_MSI)) {
586 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
587
588 bus->msi = &pcie->msi.chip;
589 }
590}
591
592static struct pci_bus *tegra_pcie_scan_bus(int nr, struct pci_sys_data *sys)
593{
594 struct tegra_pcie *pcie = sys_to_pcie(sys);
595 struct pci_bus *bus;
596
597 bus = pci_create_root_bus(pcie->dev, sys->busnr, &tegra_pcie_ops, sys,
598 &sys->resources);
599 if (!bus)
600 return NULL;
601
602 pci_scan_child_bus(bus);
603
604 return bus;
605}
606
607static irqreturn_t tegra_pcie_isr(int irq, void *arg)
608{
609 const char *err_msg[] = {
610 "Unknown",
611 "AXI slave error",
612 "AXI decode error",
613 "Target abort",
614 "Master abort",
615 "Invalid write",
616 "Response decoding error",
617 "AXI response decoding error",
618 "Transaction timeout",
619 };
620 struct tegra_pcie *pcie = arg;
621 u32 code, signature;
622
623 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
624 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
625 afi_writel(pcie, 0, AFI_INTR_CODE);
626
627 if (code == AFI_INTR_LEGACY)
628 return IRQ_NONE;
629
630 if (code >= ARRAY_SIZE(err_msg))
631 code = 0;
632
633 /*
634 * do not pollute kernel log with master abort reports since they
635 * happen a lot during enumeration
636 */
637 if (code == AFI_INTR_MASTER_ABORT)
638 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
639 signature);
640 else
641 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
642 signature);
643
644 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
645 code == AFI_INTR_FPCI_DECODE_ERROR) {
646 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
647 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
648
649 if (code == AFI_INTR_MASTER_ABORT)
650 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
651 else
652 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
653 }
654
655 return IRQ_HANDLED;
656}
657
658/*
659 * FPCI map is as follows:
660 * - 0xfdfc000000: I/O space
661 * - 0xfdfe000000: type 0 configuration space
662 * - 0xfdff000000: type 1 configuration space
663 * - 0xfe00000000: type 0 extended configuration space
664 * - 0xfe10000000: type 1 extended configuration space
665 */
666static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
667{
668 u32 fpci_bar, size, axi_address;
669
670 /* Bar 0: type 1 extended configuration space */
671 fpci_bar = 0xfe100000;
672 size = resource_size(pcie->cs);
673 axi_address = pcie->cs->start;
674 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
675 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
676 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
677
678 /* Bar 1: downstream IO bar */
679 fpci_bar = 0xfdfc0000;
680 size = resource_size(&pcie->io);
681 axi_address = pcie->io.start;
682 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
683 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
684 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
685
686 /* Bar 2: prefetchable memory BAR */
687 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
688 size = resource_size(&pcie->prefetch);
689 axi_address = pcie->prefetch.start;
690 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
691 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
692 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
693
694 /* Bar 3: non prefetchable memory BAR */
695 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
696 size = resource_size(&pcie->mem);
697 axi_address = pcie->mem.start;
698 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
699 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
700 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
701
702 /* NULL out the remaining BARs as they are not used */
703 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
704 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
705 afi_writel(pcie, 0, AFI_FPCI_BAR4);
706
707 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
708 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
709 afi_writel(pcie, 0, AFI_FPCI_BAR5);
710
711 /* map all upstream transactions as uncached */
712 afi_writel(pcie, PHYS_OFFSET, AFI_CACHE_BAR0_ST);
713 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
714 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
715 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
716
717 /* MSI translations are setup only when needed */
718 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
719 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
720 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
721 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
722}
723
724static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
725{
726 struct tegra_pcie_port *port;
727 unsigned int timeout;
728 unsigned long value;
729
730 /* configure mode and disable all ports */
731 value = afi_readl(pcie, AFI_PCIE_CONFIG);
732 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
733 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
734
735 list_for_each_entry(port, &pcie->ports, list)
736 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
737
738 afi_writel(pcie, value, AFI_PCIE_CONFIG);
739
740 value = afi_readl(pcie, AFI_FUSE);
741 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
742 afi_writel(pcie, value, AFI_FUSE);
743
744 /* initialze internal PHY, enable up to 16 PCIE lanes */
745 pads_writel(pcie, 0x0, PADS_CTL_SEL);
746
747 /* override IDDQ to 1 on all 4 lanes */
748 value = pads_readl(pcie, PADS_CTL);
749 value |= PADS_CTL_IDDQ_1L;
750 pads_writel(pcie, value, PADS_CTL);
751
752 /*
753 * Set up PHY PLL inputs select PLLE output as refclock,
754 * set TX ref sel to div10 (not div5).
755 */
756 value = pads_readl(pcie, PADS_PLL_CTL);
757 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
758 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML |
759 PADS_PLL_CTL_TXCLKREF_DIV10;
760 pads_writel(pcie, value, PADS_PLL_CTL);
761
762 /* take PLL out of reset */
763 value = pads_readl(pcie, PADS_PLL_CTL);
764 value |= PADS_PLL_CTL_RST_B4SM;
765 pads_writel(pcie, value, PADS_PLL_CTL);
766
767 /*
768 * Hack, set the clock voltage to the DEFAULT provided by hw folks.
769 * This doesn't exist in the documentation.
770 */
771 pads_writel(pcie, 0xfa5cfa5c, 0xc8);
772
773 /* wait for the PLL to lock */
774 timeout = 300;
775 do {
776 value = pads_readl(pcie, PADS_PLL_CTL);
777 usleep_range(1000, 2000);
778 if (--timeout == 0) {
779 pr_err("Tegra PCIe error: timeout waiting for PLL\n");
780 return -EBUSY;
781 }
782 } while (!(value & PADS_PLL_CTL_LOCKDET));
783
784 /* turn off IDDQ override */
785 value = pads_readl(pcie, PADS_CTL);
786 value &= ~PADS_CTL_IDDQ_1L;
787 pads_writel(pcie, value, PADS_CTL);
788
789 /* enable TX/RX data */
790 value = pads_readl(pcie, PADS_CTL);
791 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
792 pads_writel(pcie, value, PADS_CTL);
793
794 /* take the PCIe interface module out of reset */
795 tegra_periph_reset_deassert(pcie->pcie_xclk);
796
797 /* finally enable PCIe */
798 value = afi_readl(pcie, AFI_CONFIGURATION);
799 value |= AFI_CONFIGURATION_EN_FPCI;
800 afi_writel(pcie, value, AFI_CONFIGURATION);
801
802 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
803 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
804 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
805 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
806 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
807
808 /* don't enable MSI for now, only when needed */
809 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
810
811 /* disable all exceptions */
812 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
813
814 return 0;
815}
816
817static void tegra_pcie_power_off(struct tegra_pcie *pcie)
818{
819 int err;
820
821 /* TODO: disable and unprepare clocks? */
822
823 tegra_periph_reset_assert(pcie->pcie_xclk);
824 tegra_periph_reset_assert(pcie->afi_clk);
825 tegra_periph_reset_assert(pcie->pex_clk);
826
827 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
828
829 err = regulator_disable(pcie->pex_clk_supply);
830 if (err < 0)
831 dev_err(pcie->dev, "failed to disable pex-clk regulator: %d\n",
832 err);
833
834 err = regulator_disable(pcie->vdd_supply);
835 if (err < 0)
836 dev_err(pcie->dev, "failed to disable VDD regulator: %d\n",
837 err);
838}
839
840static int tegra_pcie_power_on(struct tegra_pcie *pcie)
841{
842 int err;
843
844 tegra_periph_reset_assert(pcie->pcie_xclk);
845 tegra_periph_reset_assert(pcie->afi_clk);
846 tegra_periph_reset_assert(pcie->pex_clk);
847
848 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
849
850 /* enable regulators */
851 err = regulator_enable(pcie->vdd_supply);
852 if (err < 0) {
853 dev_err(pcie->dev, "failed to enable VDD regulator: %d\n", err);
854 return err;
855 }
856
857 err = regulator_enable(pcie->pex_clk_supply);
858 if (err < 0) {
859 dev_err(pcie->dev, "failed to enable pex-clk regulator: %d\n",
860 err);
861 return err;
862 }
863
864 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
865 pcie->pex_clk);
866 if (err) {
867 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
868 return err;
869 }
870
871 tegra_periph_reset_deassert(pcie->afi_clk);
872
873 err = clk_prepare_enable(pcie->afi_clk);
874 if (err < 0) {
875 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
876 return err;
877 }
878
879 err = clk_prepare_enable(pcie->pll_e);
880 if (err < 0) {
881 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
882 return err;
883 }
884
885 return 0;
886}
887
888static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
889{
890 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
891 if (IS_ERR(pcie->pex_clk))
892 return PTR_ERR(pcie->pex_clk);
893
894 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
895 if (IS_ERR(pcie->afi_clk))
896 return PTR_ERR(pcie->afi_clk);
897
898 pcie->pcie_xclk = devm_clk_get(pcie->dev, "pcie_xclk");
899 if (IS_ERR(pcie->pcie_xclk))
900 return PTR_ERR(pcie->pcie_xclk);
901
902 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
903 if (IS_ERR(pcie->pll_e))
904 return PTR_ERR(pcie->pll_e);
905
906 return 0;
907}
908
909static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
910{
911 struct platform_device *pdev = to_platform_device(pcie->dev);
912 struct resource *pads, *afi, *res;
913 int err;
914
915 err = tegra_pcie_clocks_get(pcie);
916 if (err) {
917 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
918 return err;
919 }
920
921 err = tegra_pcie_power_on(pcie);
922 if (err) {
923 dev_err(&pdev->dev, "failed to power up: %d\n", err);
924 return err;
925 }
926
927 /* request and remap controller registers */
928 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
929 if (!pads) {
930 err = -EADDRNOTAVAIL;
931 goto poweroff;
932 }
933
934 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
935 if (!afi) {
936 err = -EADDRNOTAVAIL;
937 goto poweroff;
938 }
939
940 pcie->pads = devm_request_and_ioremap(&pdev->dev, pads);
941 if (!pcie->pads) {
942 err = -EADDRNOTAVAIL;
943 goto poweroff;
944 }
945
946 pcie->afi = devm_request_and_ioremap(&pdev->dev, afi);
947 if (!pcie->afi) {
948 err = -EADDRNOTAVAIL;
949 goto poweroff;
950 }
951
952 /* request and remap configuration space */
953 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
954 if (!res) {
955 err = -EADDRNOTAVAIL;
956 goto poweroff;
957 }
958
959 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
960 resource_size(res), res->name);
961 if (!pcie->cs) {
962 err = -EADDRNOTAVAIL;
963 goto poweroff;
964 }
965
966 /* request interrupt */
967 err = platform_get_irq_byname(pdev, "intr");
968 if (err < 0) {
969 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
970 goto poweroff;
971 }
972
973 pcie->irq = err;
974
975 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
976 if (err) {
977 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
978 goto poweroff;
979 }
980
981 return 0;
982
983poweroff:
984 tegra_pcie_power_off(pcie);
985 return err;
986}
987
988static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
989{
990 if (pcie->irq > 0)
991 free_irq(pcie->irq, pcie);
992
993 tegra_pcie_power_off(pcie);
994 return 0;
995}
996
997static int tegra_msi_alloc(struct tegra_msi *chip)
998{
999 int msi;
1000
1001 mutex_lock(&chip->lock);
1002
1003 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1004 if (msi < INT_PCI_MSI_NR)
1005 set_bit(msi, chip->used);
1006 else
1007 msi = -ENOSPC;
1008
1009 mutex_unlock(&chip->lock);
1010
1011 return msi;
1012}
1013
1014static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1015{
1016 struct device *dev = chip->chip.dev;
1017
1018 mutex_lock(&chip->lock);
1019
1020 if (!test_bit(irq, chip->used))
1021 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1022 else
1023 clear_bit(irq, chip->used);
1024
1025 mutex_unlock(&chip->lock);
1026}
1027
1028static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1029{
1030 struct tegra_pcie *pcie = data;
1031 struct tegra_msi *msi = &pcie->msi;
1032 unsigned int i, processed = 0;
1033
1034 for (i = 0; i < 8; i++) {
1035 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1036
1037 while (reg) {
1038 unsigned int offset = find_first_bit(&reg, 32);
1039 unsigned int index = i * 32 + offset;
1040 unsigned int irq;
1041
1042 /* clear the interrupt */
1043 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1044
1045 irq = irq_find_mapping(msi->domain, index);
1046 if (irq) {
1047 if (test_bit(index, msi->used))
1048 generic_handle_irq(irq);
1049 else
1050 dev_info(pcie->dev, "unhandled MSI\n");
1051 } else {
1052 /*
1053 * that's weird who triggered this?
1054 * just clear it
1055 */
1056 dev_info(pcie->dev, "unexpected MSI\n");
1057 }
1058
1059 /* see if there's any more pending in this vector */
1060 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1061
1062 processed++;
1063 }
1064 }
1065
1066 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1067}
1068
1069static int tegra_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
1070 struct msi_desc *desc)
1071{
1072 struct tegra_msi *msi = to_tegra_msi(chip);
1073 struct msi_msg msg;
1074 unsigned int irq;
1075 int hwirq;
1076
1077 hwirq = tegra_msi_alloc(msi);
1078 if (hwirq < 0)
1079 return hwirq;
1080
1081 irq = irq_create_mapping(msi->domain, hwirq);
1082 if (!irq)
1083 return -EINVAL;
1084
1085 irq_set_msi_desc(irq, desc);
1086
1087 msg.address_lo = virt_to_phys((void *)msi->pages);
1088 /* 32 bit address only */
1089 msg.address_hi = 0;
1090 msg.data = hwirq;
1091
1092 write_msi_msg(irq, &msg);
1093
1094 return 0;
1095}
1096
1097static void tegra_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
1098{
1099 struct tegra_msi *msi = to_tegra_msi(chip);
1100 struct irq_data *d = irq_get_irq_data(irq);
1101
1102 tegra_msi_free(msi, d->hwirq);
1103}
1104
1105static struct irq_chip tegra_msi_irq_chip = {
1106 .name = "Tegra PCIe MSI",
1107 .irq_enable = unmask_msi_irq,
1108 .irq_disable = mask_msi_irq,
1109 .irq_mask = mask_msi_irq,
1110 .irq_unmask = unmask_msi_irq,
1111};
1112
1113static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1114 irq_hw_number_t hwirq)
1115{
1116 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1117 irq_set_chip_data(irq, domain->host_data);
1118 set_irq_flags(irq, IRQF_VALID);
1119
1120 return 0;
1121}
1122
1123static const struct irq_domain_ops msi_domain_ops = {
1124 .map = tegra_msi_map,
1125};
1126
1127static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1128{
1129 struct platform_device *pdev = to_platform_device(pcie->dev);
1130 struct tegra_msi *msi = &pcie->msi;
1131 unsigned long base;
1132 int err;
1133 u32 reg;
1134
1135 mutex_init(&msi->lock);
1136
1137 msi->chip.dev = pcie->dev;
1138 msi->chip.setup_irq = tegra_msi_setup_irq;
1139 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1140
1141 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1142 &msi_domain_ops, &msi->chip);
1143 if (!msi->domain) {
1144 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1145 return -ENOMEM;
1146 }
1147
1148 err = platform_get_irq_byname(pdev, "msi");
1149 if (err < 0) {
1150 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1151 goto err;
1152 }
1153
1154 msi->irq = err;
1155
1156 err = request_irq(msi->irq, tegra_pcie_msi_irq, 0,
1157 tegra_msi_irq_chip.name, pcie);
1158 if (err < 0) {
1159 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1160 goto err;
1161 }
1162
1163 /* setup AFI/FPCI range */
1164 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1165 base = virt_to_phys((void *)msi->pages);
1166
1167 afi_writel(pcie, base, AFI_MSI_FPCI_BAR_ST);
1168 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1169 /* this register is in 4K increments */
1170 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1171
1172 /* enable all MSI vectors */
1173 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1174 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1175 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1176 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1177 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1178 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1179 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1180 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1181
1182 /* and unmask the MSI interrupt */
1183 reg = afi_readl(pcie, AFI_INTR_MASK);
1184 reg |= AFI_INTR_MASK_MSI_MASK;
1185 afi_writel(pcie, reg, AFI_INTR_MASK);
1186
1187 return 0;
1188
1189err:
1190 irq_domain_remove(msi->domain);
1191 return err;
1192}
1193
1194static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1195{
1196 struct tegra_msi *msi = &pcie->msi;
1197 unsigned int i, irq;
1198 u32 value;
1199
1200 /* mask the MSI interrupt */
1201 value = afi_readl(pcie, AFI_INTR_MASK);
1202 value &= ~AFI_INTR_MASK_MSI_MASK;
1203 afi_writel(pcie, value, AFI_INTR_MASK);
1204
1205 /* disable all MSI vectors */
1206 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1207 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1208 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1209 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1210 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1211 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1212 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1213 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1214
1215 free_pages(msi->pages, 0);
1216
1217 if (msi->irq > 0)
1218 free_irq(msi->irq, pcie);
1219
1220 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1221 irq = irq_find_mapping(msi->domain, i);
1222 if (irq > 0)
1223 irq_dispose_mapping(irq);
1224 }
1225
1226 irq_domain_remove(msi->domain);
1227
1228 return 0;
1229}
1230
1231static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1232 u32 *xbar)
1233{
1234 struct device_node *np = pcie->dev->of_node;
1235
1236 switch (lanes) {
1237 case 0x00000004:
1238 dev_info(pcie->dev, "single-mode configuration\n");
1239 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1240 return 0;
1241
1242 case 0x00000202:
1243 dev_info(pcie->dev, "dual-mode configuration\n");
1244 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1245 return 0;
1246 }
1247
1248 return -EINVAL;
1249}
1250
1251static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1252{
1253 struct device_node *np = pcie->dev->of_node, *port;
1254 struct of_pci_range_parser parser;
1255 struct of_pci_range range;
1256 struct resource res;
1257 u32 lanes = 0;
1258 int err;
1259
1260 if (of_pci_range_parser_init(&parser, np)) {
1261 dev_err(pcie->dev, "missing \"ranges\" property\n");
1262 return -EINVAL;
1263 }
1264
1265 pcie->vdd_supply = devm_regulator_get(pcie->dev, "vdd");
1266 if (IS_ERR(pcie->vdd_supply))
1267 return PTR_ERR(pcie->vdd_supply);
1268
1269 pcie->pex_clk_supply = devm_regulator_get(pcie->dev, "pex-clk");
1270 if (IS_ERR(pcie->pex_clk_supply))
1271 return PTR_ERR(pcie->pex_clk_supply);
1272
1273 for_each_of_pci_range(&parser, &range) {
1274 of_pci_range_to_resource(&range, np, &res);
1275
1276 switch (res.flags & IORESOURCE_TYPE_BITS) {
1277 case IORESOURCE_IO:
1278 memcpy(&pcie->io, &res, sizeof(res));
1279 pcie->io.name = "I/O";
1280 break;
1281
1282 case IORESOURCE_MEM:
1283 if (res.flags & IORESOURCE_PREFETCH) {
1284 memcpy(&pcie->prefetch, &res, sizeof(res));
1285 pcie->prefetch.name = "PREFETCH";
1286 } else {
1287 memcpy(&pcie->mem, &res, sizeof(res));
1288 pcie->mem.name = "MEM";
1289 }
1290 break;
1291 }
1292 }
1293
1294 err = of_pci_parse_bus_range(np, &pcie->busn);
1295 if (err < 0) {
1296 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1297 err);
1298 pcie->busn.name = np->name;
1299 pcie->busn.start = 0;
1300 pcie->busn.end = 0xff;
1301 pcie->busn.flags = IORESOURCE_BUS;
1302 }
1303
1304 /* parse root ports */
1305 for_each_child_of_node(np, port) {
1306 struct tegra_pcie_port *rp;
1307 unsigned int index;
1308 u32 value;
1309
1310 err = of_pci_get_devfn(port);
1311 if (err < 0) {
1312 dev_err(pcie->dev, "failed to parse address: %d\n",
1313 err);
1314 return err;
1315 }
1316
1317 index = PCI_SLOT(err);
1318
1319 if (index < 1 || index > TEGRA_MAX_PORTS) {
1320 dev_err(pcie->dev, "invalid port number: %d\n", index);
1321 return -EINVAL;
1322 }
1323
1324 index--;
1325
1326 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1327 if (err < 0) {
1328 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1329 err);
1330 return err;
1331 }
1332
1333 if (value > 16) {
1334 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1335 return -EINVAL;
1336 }
1337
1338 lanes |= value << (index << 3);
1339
1340 if (!of_device_is_available(port))
1341 continue;
1342
1343 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1344 if (!rp)
1345 return -ENOMEM;
1346
1347 err = of_address_to_resource(port, 0, &rp->regs);
1348 if (err < 0) {
1349 dev_err(pcie->dev, "failed to parse address: %d\n",
1350 err);
1351 return err;
1352 }
1353
1354 INIT_LIST_HEAD(&rp->list);
1355 rp->index = index;
1356 rp->lanes = value;
1357 rp->pcie = pcie;
1358
1359 rp->base = devm_request_and_ioremap(pcie->dev, &rp->regs);
1360 if (!rp->base)
1361 return -EADDRNOTAVAIL;
1362
1363 list_add_tail(&rp->list, &pcie->ports);
1364 }
1365
1366 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1367 if (err < 0) {
1368 dev_err(pcie->dev, "invalid lane configuration\n");
1369 return err;
1370 }
1371
1372 return 0;
1373}
1374
1375/*
1376 * FIXME: If there are no PCIe cards attached, then calling this function
1377 * can result in the increase of the bootup time as there are big timeout
1378 * loops.
1379 */
1380#define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1381static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1382{
1383 unsigned int retries = 3;
1384 unsigned long value;
1385
1386 do {
1387 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1388
1389 do {
1390 value = readl(port->base + RP_VEND_XP);
1391
1392 if (value & RP_VEND_XP_DL_UP)
1393 break;
1394
1395 usleep_range(1000, 2000);
1396 } while (--timeout);
1397
1398 if (!timeout) {
1399 dev_err(port->pcie->dev, "link %u down, retrying\n",
1400 port->index);
1401 goto retry;
1402 }
1403
1404 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
1405
1406 do {
1407 value = readl(port->base + RP_LINK_CONTROL_STATUS);
1408
1409 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
1410 return true;
1411
1412 usleep_range(1000, 2000);
1413 } while (--timeout);
1414
1415retry:
1416 tegra_pcie_port_reset(port);
1417 } while (--retries);
1418
1419 return false;
1420}
1421
1422static int tegra_pcie_enable(struct tegra_pcie *pcie)
1423{
1424 struct tegra_pcie_port *port, *tmp;
1425 struct hw_pci hw;
1426
1427 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
1428 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
1429 port->index, port->lanes);
1430
1431 tegra_pcie_port_enable(port);
1432
1433 if (tegra_pcie_port_check_link(port))
1434 continue;
1435
1436 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
1437
1438 tegra_pcie_port_disable(port);
1439 tegra_pcie_port_free(port);
1440 }
1441
1442 memset(&hw, 0, sizeof(hw));
1443
1444 hw.nr_controllers = 1;
1445 hw.private_data = (void **)&pcie;
1446 hw.setup = tegra_pcie_setup;
1447 hw.map_irq = tegra_pcie_map_irq;
1448 hw.add_bus = tegra_pcie_add_bus;
1449 hw.scan = tegra_pcie_scan_bus;
1450 hw.ops = &tegra_pcie_ops;
1451
1452 pci_common_init_dev(pcie->dev, &hw);
1453
1454 return 0;
1455}
1456
1457static int tegra_pcie_probe(struct platform_device *pdev)
1458{
1459 struct tegra_pcie *pcie;
1460 int err;
1461
1462 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1463 if (!pcie)
1464 return -ENOMEM;
1465
1466 INIT_LIST_HEAD(&pcie->busses);
1467 INIT_LIST_HEAD(&pcie->ports);
1468 pcie->dev = &pdev->dev;
1469
1470 err = tegra_pcie_parse_dt(pcie);
1471 if (err < 0)
1472 return err;
1473
1474 pcibios_min_mem = 0;
1475
1476 err = tegra_pcie_get_resources(pcie);
1477 if (err < 0) {
1478 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
1479 return err;
1480 }
1481
1482 err = tegra_pcie_enable_controller(pcie);
1483 if (err)
1484 goto put_resources;
1485
1486 /* setup the AFI address translations */
1487 tegra_pcie_setup_translations(pcie);
1488
1489 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1490 err = tegra_pcie_enable_msi(pcie);
1491 if (err < 0) {
1492 dev_err(&pdev->dev,
1493 "failed to enable MSI support: %d\n",
1494 err);
1495 goto put_resources;
1496 }
1497 }
1498
1499 err = tegra_pcie_enable(pcie);
1500 if (err < 0) {
1501 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
1502 goto disable_msi;
1503 }
1504
1505 platform_set_drvdata(pdev, pcie);
1506 return 0;
1507
1508disable_msi:
1509 if (IS_ENABLED(CONFIG_PCI_MSI))
1510 tegra_pcie_disable_msi(pcie);
1511put_resources:
1512 tegra_pcie_put_resources(pcie);
1513 return err;
1514}
1515
1516static const struct of_device_id tegra_pcie_of_match[] = {
1517 { .compatible = "nvidia,tegra20-pcie", },
1518 { },
1519};
1520MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
1521
1522static struct platform_driver tegra_pcie_driver = {
1523 .driver = {
1524 .name = "tegra-pcie",
1525 .owner = THIS_MODULE,
1526 .of_match_table = tegra_pcie_of_match,
1527 .suppress_bind_attrs = true,
1528 },
1529 .probe = tegra_pcie_probe,
1530};
1531module_platform_driver(tegra_pcie_driver);
1532
1533MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
1534MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
1535MODULE_LICENSE("GPLv2");
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-16 05:28:37 -0400