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authorYijing Wang <wangyijing@huawei.com>2013-05-29 05:01:52 -0400
committerBjorn Helgaas <bhelgaas@google.com>2013-05-29 16:46:24 -0400
commitcb93b1864088eb833ea9cef2c20f07d1961241b0 (patch)
treeda800c7af24ebee15ab99dab319978e3f88b4bcc
parente7d4515209db5246245eb5667a94ad86ba9a12cc (diff)
PCI: Fix comment typo for PCI_EXP_LNKCAP_CLKPM
Fix trivial typo for PCI_EXP_LNKCAP_CLKPM comment. Signed-off-by: Yijing Wang <wangyijing@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
-rw-r--r--include/uapi/linux/pci_regs.h2
1 files changed, 1 insertions, 1 deletions
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 864e324da80d..c3cc01d474b0 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -468,7 +468,7 @@
468#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ 468#define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */
469#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */ 469#define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
470#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */ 470#define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
471#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */ 471#define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* Clock Power Management */
472#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */ 472#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
473#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */ 473#define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
474#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */ 474#define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */