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authorNick Hoath <nicholas.hoath@intel.com>2015-02-05 05:47:22 -0500
committerDaniel Vetter <daniel.vetter@ffwll.ch>2015-02-13 17:28:09 -0500
commitcac23df48af531168625f5510912d227c7ce6b8b (patch)
tree67c95bd666bcb3b95a5312fe3825bb930b54168a
parent3dcd020a8e3ef5b5f5289a4785b85499adc7626b (diff)
drm/i915/gen9: Implement WaEnableYV12BugFixInHalfSliceChicken7
Move WaEnableYV12BugFixInHalfSliceChicken7 to gen9_init_workarounds v2: Add stepping check. Signed-off-by: Nick Hoath <nicholas.hoath@intel.com> Reviewed-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
-rw-r--r--drivers/gpu/drm/i915/i915_reg.h3
-rw-r--r--drivers/gpu/drm/i915/intel_ringbuffer.c6
2 files changed, 9 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index dab4c1ebbc08..4ee1964d2c7b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6216,6 +6216,9 @@ enum skl_disp_power_wells {
6216#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5) 6216#define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1<<5)
6217#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1) 6217#define GEN8_SAMPLER_POWER_BYPASS_DIS (1<<1)
6218 6218
6219#define GEN9_HALF_SLICE_CHICKEN7 0xe194
6220#define GEN9_ENABLE_YV12_BUGFIX (1<<4)
6221
6219/* Audio */ 6222/* Audio */
6220#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020) 6223#define G4X_AUD_VID_DID (dev_priv->info.display_mmio_offset + 0x62020)
6221#define INTEL_AUDIO_DEVCL 0x808629FB 6224#define INTEL_AUDIO_DEVCL 0x808629FB
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 909430ffa7fe..2ab447c711bc 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -896,6 +896,12 @@ static int gen9_init_workarounds(struct intel_engine_cs *ring)
896 ~GEN9_DG_MIRROR_FIX_ENABLE); 896 ~GEN9_DG_MIRROR_FIX_ENABLE);
897 } 897 }
898 898
899 if (INTEL_REVID(dev) >= SKL_REVID_C0) {
900 /* WaEnableYV12BugFixInHalfSliceChicken7:skl */
901 WA_SET_BIT_MASKED(GEN9_HALF_SLICE_CHICKEN7,
902 GEN9_ENABLE_YV12_BUGFIX);
903 }
904
899 return 0; 905 return 0;
900} 906}
901 907