diff options
author | Charulatha V <charu@ti.com> | 2011-05-02 05:51:42 -0400 |
---|---|---|
committer | Tarun Kanti DebBarma <tarun.kanti@ti.com> | 2012-02-06 03:43:41 -0500 |
commit | c8eef65a2fc311f8edca47f2e4ac2cccb70eb192 (patch) | |
tree | d3be0559d9f02b16131dc9b46958e994fd3704f1 | |
parent | 803a24343f94c3eaeed35e69efa12a576258ca70 (diff) |
gpio/omap: avoid cpu checks during module ena/disable
Remove cpu-is checks while enabling/disabling OMAP GPIO module during a gpio
request/free.
Signed-off-by: Charulatha V <charu@ti.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Reviewed-by: Kevin Hilman <khilman@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
-rw-r--r-- | arch/arm/mach-omap2/gpio.c | 2 | ||||
-rw-r--r-- | arch/arm/plat-omap/include/plat/gpio.h | 1 | ||||
-rw-r--r-- | drivers/gpio/gpio-omap.c | 53 |
3 files changed, 26 insertions, 30 deletions
diff --git a/arch/arm/mach-omap2/gpio.c b/arch/arm/mach-omap2/gpio.c index 1d60fffccb32..bc9271a970a5 100644 --- a/arch/arm/mach-omap2/gpio.c +++ b/arch/arm/mach-omap2/gpio.c | |||
@@ -88,6 +88,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
88 | pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; | 88 | pdata->regs->clr_irqenable = OMAP24XX_GPIO_CLEARIRQENABLE1; |
89 | pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; | 89 | pdata->regs->debounce = OMAP24XX_GPIO_DEBOUNCE_VAL; |
90 | pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; | 90 | pdata->regs->debounce_en = OMAP24XX_GPIO_DEBOUNCE_EN; |
91 | pdata->regs->ctrl = OMAP24XX_GPIO_CTRL; | ||
91 | break; | 92 | break; |
92 | case 2: | 93 | case 2: |
93 | pdata->bank_type = METHOD_GPIO_44XX; | 94 | pdata->bank_type = METHOD_GPIO_44XX; |
@@ -104,6 +105,7 @@ static int omap2_gpio_dev_init(struct omap_hwmod *oh, void *unused) | |||
104 | pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; | 105 | pdata->regs->clr_irqenable = OMAP4_GPIO_IRQSTATUSCLR0; |
105 | pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; | 106 | pdata->regs->debounce = OMAP4_GPIO_DEBOUNCINGTIME; |
106 | pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; | 107 | pdata->regs->debounce_en = OMAP4_GPIO_DEBOUNCENABLE; |
108 | pdata->regs->ctrl = OMAP4_GPIO_CTRL; | ||
107 | break; | 109 | break; |
108 | default: | 110 | default: |
109 | WARN(1, "Invalid gpio bank_type\n"); | 111 | WARN(1, "Invalid gpio bank_type\n"); |
diff --git a/arch/arm/plat-omap/include/plat/gpio.h b/arch/arm/plat-omap/include/plat/gpio.h index 49ec751f630e..db94bd145bc2 100644 --- a/arch/arm/plat-omap/include/plat/gpio.h +++ b/arch/arm/plat-omap/include/plat/gpio.h | |||
@@ -188,6 +188,7 @@ struct omap_gpio_reg_offs { | |||
188 | u16 clr_irqenable; | 188 | u16 clr_irqenable; |
189 | u16 debounce; | 189 | u16 debounce; |
190 | u16 debounce_en; | 190 | u16 debounce_en; |
191 | u16 ctrl; | ||
191 | 192 | ||
192 | bool irqenable_inv; | 193 | bool irqenable_inv; |
193 | }; | 194 | }; |
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c index 2eed159d964e..5cc2c04cd0a6 100644 --- a/drivers/gpio/gpio-omap.c +++ b/drivers/gpio/gpio-omap.c | |||
@@ -83,6 +83,7 @@ struct gpio_bank { | |||
83 | 83 | ||
84 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) | 84 | #define GPIO_INDEX(bank, gpio) (gpio % bank->width) |
85 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) | 85 | #define GPIO_BIT(bank, gpio) (1 << GPIO_INDEX(bank, gpio)) |
86 | #define GPIO_MOD_CTRL_BIT BIT(0) | ||
86 | 87 | ||
87 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) | 88 | static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input) |
88 | { | 89 | { |
@@ -577,22 +578,18 @@ static int omap_gpio_request(struct gpio_chip *chip, unsigned offset) | |||
577 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); | 578 | __raw_writel(__raw_readl(reg) | (1 << offset), reg); |
578 | } | 579 | } |
579 | #endif | 580 | #endif |
580 | if (!cpu_class_is_omap1()) { | 581 | if (bank->regs->ctrl && !bank->mod_usage) { |
581 | if (!bank->mod_usage) { | 582 | void __iomem *reg = bank->base + bank->regs->ctrl; |
582 | void __iomem *reg = bank->base; | 583 | u32 ctrl; |
583 | u32 ctrl; | 584 | |
584 | 585 | ctrl = __raw_readl(reg); | |
585 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 586 | /* Module is enabled, clocks are not gated */ |
586 | reg += OMAP24XX_GPIO_CTRL; | 587 | ctrl &= ~GPIO_MOD_CTRL_BIT; |
587 | else if (cpu_is_omap44xx()) | 588 | __raw_writel(ctrl, reg); |
588 | reg += OMAP4_GPIO_CTRL; | ||
589 | ctrl = __raw_readl(reg); | ||
590 | /* Module is enabled, clocks are not gated */ | ||
591 | ctrl &= 0xFFFFFFFE; | ||
592 | __raw_writel(ctrl, reg); | ||
593 | } | ||
594 | bank->mod_usage |= 1 << offset; | ||
595 | } | 589 | } |
590 | |||
591 | bank->mod_usage |= 1 << offset; | ||
592 | |||
596 | spin_unlock_irqrestore(&bank->lock, flags); | 593 | spin_unlock_irqrestore(&bank->lock, flags); |
597 | 594 | ||
598 | return 0; | 595 | return 0; |
@@ -625,22 +622,18 @@ static void omap_gpio_free(struct gpio_chip *chip, unsigned offset) | |||
625 | __raw_writel(1 << offset, reg); | 622 | __raw_writel(1 << offset, reg); |
626 | } | 623 | } |
627 | #endif | 624 | #endif |
628 | if (!cpu_class_is_omap1()) { | 625 | bank->mod_usage &= ~(1 << offset); |
629 | bank->mod_usage &= ~(1 << offset); | 626 | |
630 | if (!bank->mod_usage) { | 627 | if (bank->regs->ctrl && !bank->mod_usage) { |
631 | void __iomem *reg = bank->base; | 628 | void __iomem *reg = bank->base + bank->regs->ctrl; |
632 | u32 ctrl; | 629 | u32 ctrl; |
633 | 630 | ||
634 | if (cpu_is_omap24xx() || cpu_is_omap34xx()) | 631 | ctrl = __raw_readl(reg); |
635 | reg += OMAP24XX_GPIO_CTRL; | 632 | /* Module is disabled, clocks are gated */ |
636 | else if (cpu_is_omap44xx()) | 633 | ctrl |= GPIO_MOD_CTRL_BIT; |
637 | reg += OMAP4_GPIO_CTRL; | 634 | __raw_writel(ctrl, reg); |
638 | ctrl = __raw_readl(reg); | ||
639 | /* Module is disabled, clocks are gated */ | ||
640 | ctrl |= 1; | ||
641 | __raw_writel(ctrl, reg); | ||
642 | } | ||
643 | } | 635 | } |
636 | |||
644 | _reset_gpio(bank, bank->chip.base + offset); | 637 | _reset_gpio(bank, bank->chip.base + offset); |
645 | spin_unlock_irqrestore(&bank->lock, flags); | 638 | spin_unlock_irqrestore(&bank->lock, flags); |
646 | } | 639 | } |