drm/radeon: fix bank tiling parameters on evergreen

Handle the 16 bank case.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

1 files changed, 11 insertions, 3 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e585a3b947eb..f4ef24f11419 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1986,10 +1986,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP)
                 rdev->config.evergreen.tile_config |= 1 << 4;
         else {
-                if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT)
-                        rdev->config.evergreen.tile_config |= 1 << 4;
-                else
+                switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
+                case 0: /* four banks */
                         rdev->config.evergreen.tile_config |= 0 << 4;
+                        break;
+                case 1: /* eight banks */
+                        rdev->config.evergreen.tile_config |= 1 << 4;
+                        break;
+                case 2: /* sixteen banks */
+                default:
+                        rdev->config.evergreen.tile_config |= 2 << 4;
+                        break;
+                }
         }
         rdev->config.evergreen.tile_config |= 0 << 8;
         rdev->config.evergreen.tile_config |=