diff options
| author | Sujith Manoharan <c_manoha@qca.qualcomm.com> | 2013-09-11 02:10:57 -0400 |
|---|---|---|
| committer | John W. Linville <linville@tuxdriver.com> | 2013-09-26 15:13:46 -0400 |
| commit | c6945455682c92b9b61f2cf354771e00da11492d (patch) | |
| tree | 764e3e26efe982f9cc29ea7365eedc0453946863 | |
| parent | 8aee318f8d94761546f06248ad87610e4104655a (diff) | |
ath9k: Fix calibration for AR9462
TX IQ calibration is disabled by default for AR9462, this
is done using the initvals (reg 0xa644).
But, to compensate for this, the AR_PHY_RX_DELAY register
should be set to the max allowed value when performing
calibration.
Signed-off-by: Sujith Manoharan <c_manoha@qca.qualcomm.com>
Signed-off-by: John W. Linville <linville@tuxdriver.com>
| -rw-r--r-- | drivers/net/wireless/ath/ath9k/ar9003_calib.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_calib.c b/drivers/net/wireless/ath/ath9k/ar9003_calib.c index 6988e1d081f2..6001bc0ebc55 100644 --- a/drivers/net/wireless/ath/ath9k/ar9003_calib.c +++ b/drivers/net/wireless/ath/ath9k/ar9003_calib.c | |||
| @@ -1019,6 +1019,7 @@ static bool ar9003_hw_init_cal(struct ath_hw *ah, | |||
| 1019 | bool is_reusable = true, status = true; | 1019 | bool is_reusable = true, status = true; |
| 1020 | bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false; | 1020 | bool run_rtt_cal = false, run_agc_cal, sep_iq_cal = false; |
| 1021 | bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); | 1021 | bool rtt = !!(ah->caps.hw_caps & ATH9K_HW_CAP_RTT); |
| 1022 | u32 rx_delay = 0; | ||
| 1022 | u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL | | 1023 | u32 agc_ctrl = 0, agc_supp_cals = AR_PHY_AGC_CONTROL_OFFSET_CAL | |
| 1023 | AR_PHY_AGC_CONTROL_FLTR_CAL | | 1024 | AR_PHY_AGC_CONTROL_FLTR_CAL | |
| 1024 | AR_PHY_AGC_CONTROL_PKDET_CAL; | 1025 | AR_PHY_AGC_CONTROL_PKDET_CAL; |
| @@ -1099,6 +1100,15 @@ skip_tx_iqcal: | |||
| 1099 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); | 1100 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); |
| 1100 | } | 1101 | } |
| 1101 | 1102 | ||
| 1103 | if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { | ||
| 1104 | rx_delay = REG_READ(ah, AR_PHY_RX_DELAY); | ||
| 1105 | /* Disable BB_active */ | ||
| 1106 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); | ||
| 1107 | udelay(5); | ||
| 1108 | REG_WRITE(ah, AR_PHY_RX_DELAY, AR_PHY_RX_DELAY_DELAY); | ||
| 1109 | REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); | ||
| 1110 | } | ||
| 1111 | |||
| 1102 | if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { | 1112 | if (run_agc_cal || !(ah->ah_flags & AH_FASTCC)) { |
| 1103 | /* Calibrate the AGC */ | 1113 | /* Calibrate the AGC */ |
| 1104 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, | 1114 | REG_WRITE(ah, AR_PHY_AGC_CONTROL, |
| @@ -1113,6 +1123,11 @@ skip_tx_iqcal: | |||
| 1113 | ar9003_hw_do_manual_peak_cal(ah, chan); | 1123 | ar9003_hw_do_manual_peak_cal(ah, chan); |
| 1114 | } | 1124 | } |
| 1115 | 1125 | ||
| 1126 | if (REG_READ(ah, AR_PHY_CL_CAL_CTL) & AR_PHY_CL_CAL_ENABLE) { | ||
| 1127 | REG_WRITE(ah, AR_PHY_RX_DELAY, rx_delay); | ||
| 1128 | udelay(5); | ||
| 1129 | } | ||
| 1130 | |||
| 1116 | if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal) | 1131 | if (ath9k_hw_mci_is_enabled(ah) && IS_CHAN_2GHZ(chan) && run_agc_cal) |
| 1117 | ar9003_mci_init_cal_done(ah); | 1132 | ar9003_mci_init_cal_done(ah); |
| 1118 | 1133 | ||