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authorTony Lindgren <tony@atomide.com>2013-10-11 18:40:07 -0400
committerTony Lindgren <tony@atomide.com>2013-10-11 18:40:07 -0400
commitc49f4984fd45be36502e903e7a5a6a4faff42931 (patch)
treef53768edb35290e7b5be2daf5deb477d905a2298
parentd0e639c9e06d44e713170031fe05fb60ebe680af (diff)
parent6cf02dbb4b71f1c0c9acec89ae2df3b2318135f4 (diff)
Merge tag 'for_3.13/dts_signed' of git://git.kernel.org/pub/scm/linux/kernel/git/bcousson/linux-omap-dt into omap-for-v3.13/dt
Add the minimal DTS support for DRA7xx based SoC core. Add the initial support for N900 and gta04 phones. Enable USB3 on OMAP5 evm board. Add support for cryto accelerators Add new IGEP AQUILA board Add AM33XX EDMA support Update HSUSB node to use the reset-gpios fmwk
Diffstat
-rw-r--r--Documentation/devicetree/bindings/crypto/omap-aes.txt31
-rw-r--r--Documentation/devicetree/bindings/crypto/omap-sham.txt28
-rw-r--r--Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt26
-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/am335x-base0033.dts16
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi311
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts18
-rw-r--r--arch/arm/boot/dts/am335x-boneblack.dts61
-rw-r--r--arch/arm/boot/dts/am335x-evm.dts721
-rw-r--r--arch/arm/boot/dts/am335x-evmsk.dts422
-rw-r--r--arch/arm/boot/dts/am335x-igep0033.dtsi265
-rw-r--r--arch/arm/boot/dts/am33xx.dtsi103
-rw-r--r--arch/arm/boot/dts/am4372.dtsi361
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts271
-rw-r--r--arch/arm/boot/dts/dra7.dtsi575
-rw-r--r--arch/arm/boot/dts/omap2420-h4.dts6
-rw-r--r--arch/arm/boot/dts/omap3-beagle-xm.dts65
-rw-r--r--arch/arm/boot/dts/omap3-beagle.dts44
-rw-r--r--arch/arm/boot/dts/omap3-devkit8000.dts2
-rw-r--r--arch/arm/boot/dts/omap3-gta04.dts168
-rw-r--r--arch/arm/boot/dts/omap3-igep.dtsi11
-rw-r--r--arch/arm/boot/dts/omap3-igep0020.dts70
-rw-r--r--arch/arm/boot/dts/omap3-igep0030.dts17
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts92
-rw-r--r--arch/arm/boot/dts/omap3.dtsi2
-rw-r--r--arch/arm/boot/dts/omap3430-sdp.dts22
-rw-r--r--arch/arm/boot/dts/omap4-panda-common.dtsi39
-rw-r--r--arch/arm/boot/dts/omap4-sdp.dts21
-rw-r--r--arch/arm/boot/dts/omap4.dtsi20
-rw-r--r--arch/arm/boot/dts/omap5-uevm.dts52
-rw-r--r--arch/arm/boot/dts/omap5.dtsi6
-rw-r--r--arch/arm/boot/dts/twl6030_omap4.dtsi38
-rw-r--r--include/dt-bindings/pinctrl/dra.h50
33 files changed, 3130 insertions, 810 deletions
diff --git a/Documentation/devicetree/bindings/crypto/omap-aes.txt b/Documentation/devicetree/bindings/crypto/omap-aes.txt
new file mode 100644
index 000000000000..fd9717653cbb
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-aes.txt
@@ -0,0 +1,31 @@
1OMAP SoC AES crypto Module
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 AES versions:
7 - "ti,omap2-aes" for OMAP2.
8 - "ti,omap3-aes" for OMAP3.
9 - "ti,omap4-aes" for OMAP4 and AM33XX.
10 Note that the OMAP2 and 3 versions are compatible (OMAP3 supports
11 more algorithms) but they are incompatible with OMAP4.
12- ti,hwmods: Name of the hwmod associated with the AES module
13- reg : Offset and length of the register set for the module
14- interrupts : the interrupt-specifier for the AES module.
15
16Optional properties:
17- dmas: DMA specifiers for tx and rx dma. See the DMA client binding,
18 Documentation/devicetree/bindings/dma/dma.txt
19- dma-names: DMA request names should include "tx" and "rx" if present.
20
21Example:
22 /* AM335x */
23 aes: aes@53500000 {
24 compatible = "ti,omap4-aes";
25 ti,hwmods = "aes";
26 reg = <0x53500000 0xa0>;
27 interrupts = <102>;
28 dmas = <&edma 6>,
29 <&edma 5>;
30 dma-names = "tx", "rx";
31 };
diff --git a/Documentation/devicetree/bindings/crypto/omap-sham.txt b/Documentation/devicetree/bindings/crypto/omap-sham.txt
new file mode 100644
index 000000000000..f839acd6f0ee
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/omap-sham.txt
@@ -0,0 +1,28 @@
1OMAP SoC SHA crypto Module
2
3Required properties:
4
5- compatible : Should contain entries for this and backward compatible
6 SHAM versions:
7 - "ti,omap2-sham" for OMAP2 & OMAP3.
8 - "ti,omap4-sham" for OMAP4 and AM33XX.
9 Note that these two versions are incompatible.
10- ti,hwmods: Name of the hwmod associated with the SHAM module
11- reg : Offset and length of the register set for the module
12- interrupts : the interrupt-specifier for the SHAM module.
13
14Optional properties:
15- dmas: DMA specifiers for the rx dma. See the DMA client binding,
16 Documentation/devicetree/bindings/dma/dma.txt
17- dma-names: DMA request name. Should be "rx" if a dma is present.
18
19Example:
20 /* AM335x */
21 sham: sham@53100000 {
22 compatible = "ti,omap4-sham";
23 ti,hwmods = "sham";
24 reg = <0x53100000 0x200>;
25 interrupts = <109>;
26 dmas = <&edma 36>;
27 dma-names = "rx";
28 };
diff --git a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
index ed271fc255b2..8c8908ab84ba 100644
--- a/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
+++ b/Documentation/devicetree/bindings/mmc/ti-omap-hsmmc.txt
@@ -20,8 +20,29 @@ ti,dual-volt: boolean, supports dual voltage cards
20ti,non-removable: non-removable slot (like eMMC) 20ti,non-removable: non-removable slot (like eMMC)
21ti,needs-special-reset: Requires a special softreset sequence 21ti,needs-special-reset: Requires a special softreset sequence
22ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed 22ti,needs-special-hs-handling: HSMMC IP needs special setting for handling High Speed
23dmas: List of DMA specifiers with the controller specific format
24as described in the generic DMA client binding. A tx and rx
25specifier is required.
26dma-names: List of DMA request names. These strings correspond
271:1 with the DMA specifiers listed in dmas. The string naming is
28to be "rx" and "tx" for RX and TX DMA requests, respectively.
29
30Examples:
31
32[hwmod populated DMA resources]
33
34 mmc1: mmc@0x4809c000 {
35 compatible = "ti,omap4-hsmmc";
36 reg = <0x4809c000 0x400>;
37 ti,hwmods = "mmc1";
38 ti,dual-volt;
39 bus-width = <4>;
40 vmmc-supply = <&vmmc>; /* phandle to regulator node */
41 ti,non-removable;
42 };
43
44[generic DMA request binding]
23 45
24Example:
25 mmc1: mmc@0x4809c000 { 46 mmc1: mmc@0x4809c000 {
26 compatible = "ti,omap4-hsmmc"; 47 compatible = "ti,omap4-hsmmc";
27 reg = <0x4809c000 0x400>; 48 reg = <0x4809c000 0x400>;
@@ -30,4 +51,7 @@ Example:
30 bus-width = <4>; 51 bus-width = <4>;
31 vmmc-supply = <&vmmc>; /* phandle to regulator node */ 52 vmmc-supply = <&vmmc>; /* phandle to regulator node */
32 ti,non-removable; 53 ti,non-removable;
54 dmas = <&edma 24
55 &edma 25>;
56 dma-names = "tx", "rx";
33 }; 57 };
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 802720e3e8fd..9df7d2c15e7d 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -172,7 +172,9 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
172 omap3-devkit8000.dtb \ 172 omap3-devkit8000.dtb \
173 omap3-beagle-xm.dtb \ 173 omap3-beagle-xm.dtb \
174 omap3-evm.dtb \ 174 omap3-evm.dtb \
175 omap3-n900.dtb \
175 omap3-tobi.dtb \ 176 omap3-tobi.dtb \
177 omap3-gta04.dtb \
176 omap3-igep0020.dtb \ 178 omap3-igep0020.dtb \
177 omap3-igep0030.dtb \ 179 omap3-igep0030.dtb \
178 omap4-panda.dtb \ 180 omap4-panda.dtb \
@@ -186,9 +188,11 @@ dtb-$(CONFIG_ARCH_OMAP2PLUS) += omap2420-h4.dtb \
186 am335x-evmsk.dtb \ 188 am335x-evmsk.dtb \
187 am335x-bone.dtb \ 189 am335x-bone.dtb \
188 am335x-boneblack.dtb \ 190 am335x-boneblack.dtb \
191 am335x-base0033.dtb \
189 am3517-evm.dtb \ 192 am3517-evm.dtb \
190 am3517_mt_ventoux.dtb \ 193 am3517_mt_ventoux.dtb \
191 am43x-epos-evm.dtb 194 am43x-epos-evm.dtb \
195 dra7-evm.dtb
192dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb 196dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
193dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb 197dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
194dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \ 198dtb-$(CONFIG_ARCH_U8500) += ste-snowball.dtb \
diff --git a/arch/arm/boot/dts/am335x-base0033.dts b/arch/arm/boot/dts/am335x-base0033.dts
new file mode 100644
index 000000000000..b4f95c2bbf74
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-base0033.dts
@@ -0,0 +1,16 @@
1/*
2 * am335x-base0033.dts - Device Tree file for IGEP AQUILA EXPANSION
3 *
4 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#include "am335x-igep0033.dtsi"
12
13/ {
14 model = "IGEP COM AM335x on AQUILA Expansion";
15 compatible = "isee,am335x-base0033", "isee,am335x-igep0033", "ti,am33xx";
16};
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 2f66deda9f5c..e3f27ec31718 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -21,177 +21,205 @@
21 reg = <0x80000000 0x10000000>; /* 256 MB */ 21 reg = <0x80000000 0x10000000>; /* 256 MB */
22 }; 22 };
23 23
24 am33xx_pinmux: pinmux@44e10800 { 24 leds {
25 pinctrl-names = "default"; 25 pinctrl-names = "default";
26 pinctrl-0 = <&clkout2_pin>; 26 pinctrl-0 = <&user_leds_s0>;
27
28 user_leds_s0: user_leds_s0 {
29 pinctrl-single,pins = <
30 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
31 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
32 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
33 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
34 >;
35 };
36 27
37 i2c0_pins: pinmux_i2c0_pins { 28 compatible = "gpio-leds";
38 pinctrl-single,pins = <
39 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
40 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
41 >;
42 };
43 29
44 uart0_pins: pinmux_uart0_pins { 30 led@2 {
45 pinctrl-single,pins = < 31 label = "beaglebone:green:heartbeat";
46 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 32 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
47 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 33 linux,default-trigger = "heartbeat";
48 >; 34 default-state = "off";
49 }; 35 };
50 36
51 clkout2_pin: pinmux_clkout2_pin { 37 led@3 {
52 pinctrl-single,pins = < 38 label = "beaglebone:green:mmc0";
53 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 39 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>;
54 >; 40 linux,default-trigger = "mmc0";
41 default-state = "off";
55 }; 42 };
56 43
57 cpsw_default: cpsw_default { 44 led@4 {
58 pinctrl-single,pins = < 45 label = "beaglebone:green:usr2";
59 /* Slave 1 */ 46 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
60 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */ 47 linux,default-trigger = "cpu0";
61 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */ 48 default-state = "off";
62 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
63 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
64 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
65 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
66 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
67 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
68 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
69 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
70 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
71 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
72 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
73 >;
74 }; 49 };
75 50
76 cpsw_sleep: cpsw_sleep { 51 led@5 {
77 pinctrl-single,pins = < 52 label = "beaglebone:green:usr3";
78 /* Slave 1 reset value */ 53 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>;
79 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 54 linux,default-trigger = "mmc1";
80 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 55 default-state = "off";
81 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
82 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
83 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
86 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
87 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
90 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
91 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 >;
93 }; 56 };
57 };
94 58
95 davinci_mdio_default: davinci_mdio_default { 59 vmmcsd_fixed: fixedregulator@0 {
96 pinctrl-single,pins = < 60 compatible = "regulator-fixed";
97 /* MDIO */ 61 regulator-name = "vmmcsd_fixed";
98 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 62 regulator-min-microvolt = <3300000>;
99 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 63 regulator-max-microvolt = <3300000>;
100 >; 64 };
101 }; 65};
102 66
103 davinci_mdio_sleep: davinci_mdio_sleep { 67&am33xx_pinmux {
104 pinctrl-single,pins = < 68 pinctrl-names = "default";
105 /* MDIO reset value */ 69 pinctrl-0 = <&clkout2_pin>;
106 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 70
107 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 71 user_leds_s0: user_leds_s0 {
108 >; 72 pinctrl-single,pins = <
109 }; 73 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
74 0x58 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a6.gpio1_22 */
75 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
76 0x60 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_a8.gpio1_24 */
77 >;
110 }; 78 };
111 79
112 ocp { 80 i2c0_pins: pinmux_i2c0_pins {
113 uart0: serial@44e09000 { 81 pinctrl-single,pins = <
114 pinctrl-names = "default"; 82 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
115 pinctrl-0 = <&uart0_pins>; 83 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
84 >;
85 };
116 86
117 status = "okay"; 87 uart0_pins: pinmux_uart0_pins {
118 }; 88 pinctrl-single,pins = <
89 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
90 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
91 >;
92 };
119 93
120 musb: usb@47400000 { 94 clkout2_pin: pinmux_clkout2_pin {
121 status = "okay"; 95 pinctrl-single,pins = <
96 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
97 >;
98 };
122 99
123 control@44e10000 { 100 cpsw_default: cpsw_default {
124 status = "okay"; 101 pinctrl-single,pins = <
125 }; 102 /* Slave 1 */
103 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
105 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
110 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
111 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
112 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
113 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
114 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
115 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
116 >;
117 };
126 118
127 usb-phy@47401300 { 119 cpsw_sleep: cpsw_sleep {
128 status = "okay"; 120 pinctrl-single,pins = <
129 }; 121 /* Slave 1 reset value */
122 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 >;
136 };
130 137
131 usb-phy@47401b00 { 138 davinci_mdio_default: davinci_mdio_default {
132 status = "okay"; 139 pinctrl-single,pins = <
133 }; 140 /* MDIO */
141 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
142 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
143 >;
144 };
134 145
135 usb@47401000 { 146 davinci_mdio_sleep: davinci_mdio_sleep {
136 status = "okay"; 147 pinctrl-single,pins = <
137 }; 148 /* MDIO reset value */
149 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
151 >;
152 };
138 153
139 usb@47401800 { 154 mmc1_pins: pinmux_mmc1_pins {
140 status = "okay"; 155 pinctrl-single,pins = <
141 dr_mode = "host"; 156 0x160 (PIN_INPUT | MUX_MODE7) /* GPIO0_6 */
142 }; 157 >;
158 };
143 159
144 dma-controller@07402000 { 160 emmc_pins: pinmux_emmc_pins {
145 status = "okay"; 161 pinctrl-single,pins = <
146 }; 162 0x80 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn1.mmc1_clk */
147 }; 163 0x84 (PIN_INPUT_PULLUP | MUX_MODE2) /* gpmc_csn2.mmc1_cmd */
164 0x00 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad0.mmc1_dat0 */
165 0x04 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad1.mmc1_dat1 */
166 0x08 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad2.mmc1_dat2 */
167 0x0c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad3.mmc1_dat3 */
168 0x10 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad4.mmc1_dat4 */
169 0x14 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad5.mmc1_dat5 */
170 0x18 (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad6.mmc1_dat6 */
171 0x1c (PIN_INPUT_PULLUP | MUX_MODE1) /* gpmc_ad7.mmc1_dat7 */
172 >;
173 };
174};
148 175
149 i2c0: i2c@44e0b000 { 176&uart0 {
150 pinctrl-names = "default"; 177 pinctrl-names = "default";
151 pinctrl-0 = <&i2c0_pins>; 178 pinctrl-0 = <&uart0_pins>;
152 179
153 status = "okay"; 180 status = "okay";
154 clock-frequency = <400000>; 181};
155 182
156 tps: tps@24 { 183&usb {
157 reg = <0x24>; 184 status = "okay";
158 };
159 185
160 }; 186 control@44e10000 {
187 status = "okay";
161 }; 188 };
162 189
163 leds { 190 usb-phy@47401300 {
164 pinctrl-names = "default"; 191 status = "okay";
165 pinctrl-0 = <&user_leds_s0>; 192 };
166 193
167 compatible = "gpio-leds"; 194 usb-phy@47401b00 {
195 status = "okay";
196 };
168 197
169 led@2 { 198 usb@47401000 {
170 label = "beaglebone:green:heartbeat"; 199 status = "okay";
171 gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>; 200 };
172 linux,default-trigger = "heartbeat";
173 default-state = "off";
174 };
175 201
176 led@3 { 202 usb@47401800 {
177 label = "beaglebone:green:mmc0"; 203 status = "okay";
178 gpios = <&gpio1 22 GPIO_ACTIVE_HIGH>; 204 dr_mode = "host";
179 linux,default-trigger = "mmc0"; 205 };
180 default-state = "off";
181 };
182 206
183 led@4 { 207 dma-controller@07402000 {
184 label = "beaglebone:green:usr2"; 208 status = "okay";
185 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>; 209 };
186 default-state = "off"; 210};
187 };
188 211
189 led@5 { 212&i2c0 {
190 label = "beaglebone:green:usr3"; 213 pinctrl-names = "default";
191 gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; 214 pinctrl-0 = <&i2c0_pins>;
192 default-state = "off"; 215
193 }; 216 status = "okay";
217 clock-frequency = <400000>;
218
219 tps: tps@24 {
220 reg = <0x24>;
194 }; 221 };
222
195}; 223};
196 224
197/include/ "tps65217.dtsi" 225/include/ "tps65217.dtsi"
@@ -260,3 +288,12 @@
260 pinctrl-0 = <&davinci_mdio_default>; 288 pinctrl-0 = <&davinci_mdio_default>;
261 pinctrl-1 = <&davinci_mdio_sleep>; 289 pinctrl-1 = <&davinci_mdio_sleep>;
262}; 290};
291
292&mmc1 {
293 status = "okay";
294 bus-width = <0x4>;
295 pinctrl-names = "default";
296 pinctrl-0 = <&mmc1_pins>;
297 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>;
298 cd-inverted;
299};
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index 7993c489982c..94ee427a6db1 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -9,3 +9,21 @@
9 9
10#include "am33xx.dtsi" 10#include "am33xx.dtsi"
11#include "am335x-bone-common.dtsi" 11#include "am335x-bone-common.dtsi"
12
13&ldo3_reg {
14 regulator-min-microvolt = <1800000>;
15 regulator-max-microvolt = <3300000>;
16 regulator-always-on;
17};
18
19&mmc1 {
20 vmmc-supply = <&ldo3_reg>;
21};
22
23&sham {
24 status = "okay";
25};
26
27&aes {
28 status = "okay";
29};
diff --git a/arch/arm/boot/dts/am335x-boneblack.dts b/arch/arm/boot/dts/am335x-boneblack.dts
index 197cadf72d2c..6b71ad95a5cf 100644
--- a/arch/arm/boot/dts/am335x-boneblack.dts
+++ b/arch/arm/boot/dts/am335x-boneblack.dts
@@ -15,3 +15,64 @@
15 regulator-max-microvolt = <1800000>; 15 regulator-max-microvolt = <1800000>;
16 regulator-always-on; 16 regulator-always-on;
17}; 17};
18
19&mmc1 {
20 vmmc-supply = <&vmmcsd_fixed>;
21};
22
23&mmc2 {
24 vmmc-supply = <&vmmcsd_fixed>;
25 pinctrl-names = "default";
26 pinctrl-0 = <&emmc_pins>;
27 bus-width = <8>;
28 status = "okay";
29 ti,vcc-aux-disable-is-sleep;
30};
31
32&am33xx_pinmux {
33 nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
34 pinctrl-single,pins = <
35 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
36 0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
37 0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
38 0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
39 0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
40 0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
41 0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
42 0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
43 0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
44 0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
45 0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
46 0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
47 0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
48 0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
49 0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
50 0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
51 0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
52 0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
53 0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
54 0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
55 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
56 >;
57 };
58 nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
59 pinctrl-single,pins = <
60 0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
61 >;
62 };
63};
64
65&lcdc {
66 status = "okay";
67};
68
69/ {
70 hdmi {
71 compatible = "ti,tilcdc,slave";
72 i2c = <&i2c0>;
73 pinctrl-names = "default", "off";
74 pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
75 pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
76 status = "okay";
77 };
78};
diff --git a/arch/arm/boot/dts/am335x-evm.dts b/arch/arm/boot/dts/am335x-evm.dts
index e8ec8756e498..eabacf9b8c31 100644
--- a/arch/arm/boot/dts/am335x-evm.dts
+++ b/arch/arm/boot/dts/am335x-evm.dts
@@ -24,324 +24,6 @@
24 reg = <0x80000000 0x10000000>; /* 256 MB */ 24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 }; 25 };
26 26
27 am33xx_pinmux: pinmux@44e10800 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
30
31 matrix_keypad_s0: matrix_keypad_s0 {
32 pinctrl-single,pins = <
33 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
34 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
35 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
36 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
37 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
38 >;
39 };
40
41 volume_keys_s0: volume_keys_s0 {
42 pinctrl-single,pins = <
43 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
44 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
45 >;
46 };
47
48 i2c0_pins: pinmux_i2c0_pins {
49 pinctrl-single,pins = <
50 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
51 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
52 >;
53 };
54
55 i2c1_pins: pinmux_i2c1_pins {
56 pinctrl-single,pins = <
57 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
58 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
59 >;
60 };
61
62 uart0_pins: pinmux_uart0_pins {
63 pinctrl-single,pins = <
64 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
65 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
66 >;
67 };
68
69 clkout2_pin: pinmux_clkout2_pin {
70 pinctrl-single,pins = <
71 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
72 >;
73 };
74
75 nandflash_pins_s0: nandflash_pins_s0 {
76 pinctrl-single,pins = <
77 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
78 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
79 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
80 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
81 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
82 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
83 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
84 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
85 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
86 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
87 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
88 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
89 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
90 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
91 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
92 >;
93 };
94
95 ecap0_pins: backlight_pins {
96 pinctrl-single,pins = <
97 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
98 >;
99 };
100
101 cpsw_default: cpsw_default {
102 pinctrl-single,pins = <
103 /* Slave 1 */
104 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
105 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
106 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
107 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
108 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
109 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
110 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
111 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
112 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
113 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
114 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
115 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
116 >;
117 };
118
119 cpsw_sleep: cpsw_sleep {
120 pinctrl-single,pins = <
121 /* Slave 1 reset value */
122 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
129 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
130 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
131 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 >;
135 };
136
137 davinci_mdio_default: davinci_mdio_default {
138 pinctrl-single,pins = <
139 /* MDIO */
140 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
141 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
142 >;
143 };
144
145 davinci_mdio_sleep: davinci_mdio_sleep {
146 pinctrl-single,pins = <
147 /* MDIO reset value */
148 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
149 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
150 >;
151 };
152 };
153
154 ocp {
155 uart0: serial@44e09000 {
156 pinctrl-names = "default";
157 pinctrl-0 = <&uart0_pins>;
158
159 status = "okay";
160 };
161
162 i2c0: i2c@44e0b000 {
163 pinctrl-names = "default";
164 pinctrl-0 = <&i2c0_pins>;
165
166 status = "okay";
167 clock-frequency = <400000>;
168
169 tps: tps@2d {
170 reg = <0x2d>;
171 };
172 };
173
174 musb: usb@47400000 {
175 status = "okay";
176
177 control@44e10000 {
178 status = "okay";
179 };
180
181 usb-phy@47401300 {
182 status = "okay";
183 };
184
185 usb-phy@47401b00 {
186 status = "okay";
187 };
188
189 usb@47401000 {
190 status = "okay";
191 };
192
193 usb@47401800 {
194 status = "okay";
195 dr_mode = "host";
196 };
197
198 dma-controller@07402000 {
199 status = "okay";
200 };
201 };
202
203 i2c1: i2c@4802a000 {
204 pinctrl-names = "default";
205 pinctrl-0 = <&i2c1_pins>;
206
207 status = "okay";
208 clock-frequency = <100000>;
209
210 lis331dlh: lis331dlh@18 {
211 compatible = "st,lis331dlh", "st,lis3lv02d";
212 reg = <0x18>;
213 Vdd-supply = <&lis3_reg>;
214 Vdd_IO-supply = <&lis3_reg>;
215
216 st,click-single-x;
217 st,click-single-y;
218 st,click-single-z;
219 st,click-thresh-x = <10>;
220 st,click-thresh-y = <10>;
221 st,click-thresh-z = <10>;
222 st,irq1-click;
223 st,irq2-click;
224 st,wakeup-x-lo;
225 st,wakeup-x-hi;
226 st,wakeup-y-lo;
227 st,wakeup-y-hi;
228 st,wakeup-z-lo;
229 st,wakeup-z-hi;
230 st,min-limit-x = <120>;
231 st,min-limit-y = <120>;
232 st,min-limit-z = <140>;
233 st,max-limit-x = <550>;
234 st,max-limit-y = <550>;
235 st,max-limit-z = <750>;
236 };
237
238 tsl2550: tsl2550@39 {
239 compatible = "taos,tsl2550";
240 reg = <0x39>;
241 };
242
243 tmp275: tmp275@48 {
244 compatible = "ti,tmp275";
245 reg = <0x48>;
246 };
247 };
248
249 elm: elm@48080000 {
250 status = "okay";
251 };
252
253 epwmss0: epwmss@48300000 {
254 status = "okay";
255
256 ecap0: ecap@48300100 {
257 status = "okay";
258 pinctrl-names = "default";
259 pinctrl-0 = <&ecap0_pins>;
260 };
261 };
262
263 gpmc: gpmc@50000000 {
264 status = "okay";
265 pinctrl-names = "default";
266 pinctrl-0 = <&nandflash_pins_s0>;
267 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
268 nand@0,0 {
269 reg = <0 0 0>; /* CS0, offset 0 */
270 nand-bus-width = <8>;
271 ti,nand-ecc-opt = "bch8";
272 gpmc,device-nand = "true";
273 gpmc,device-width = <1>;
274 gpmc,sync-clk-ps = <0>;
275 gpmc,cs-on-ns = <0>;
276 gpmc,cs-rd-off-ns = <44>;
277 gpmc,cs-wr-off-ns = <44>;
278 gpmc,adv-on-ns = <6>;
279 gpmc,adv-rd-off-ns = <34>;
280 gpmc,adv-wr-off-ns = <44>;
281 gpmc,we-on-ns = <0>;
282 gpmc,we-off-ns = <40>;
283 gpmc,oe-on-ns = <0>;
284 gpmc,oe-off-ns = <54>;
285 gpmc,access-ns = <64>;
286 gpmc,rd-cycle-ns = <82>;
287 gpmc,wr-cycle-ns = <82>;
288 gpmc,wait-on-read = "true";
289 gpmc,wait-on-write = "true";
290 gpmc,bus-turnaround-ns = <0>;
291 gpmc,cycle2cycle-delay-ns = <0>;
292 gpmc,clk-activation-ns = <0>;
293 gpmc,wait-monitoring-ns = <0>;
294 gpmc,wr-access-ns = <40>;
295 gpmc,wr-data-mux-bus-ns = <0>;
296
297 #address-cells = <1>;
298 #size-cells = <1>;
299 elm_id = <&elm>;
300
301 /* MTD partition table */
302 partition@0 {
303 label = "SPL1";
304 reg = <0x00000000 0x000020000>;
305 };
306
307 partition@1 {
308 label = "SPL2";
309 reg = <0x00020000 0x00020000>;
310 };
311
312 partition@2 {
313 label = "SPL3";
314 reg = <0x00040000 0x00020000>;
315 };
316
317 partition@3 {
318 label = "SPL4";
319 reg = <0x00060000 0x00020000>;
320 };
321
322 partition@4 {
323 label = "U-boot";
324 reg = <0x00080000 0x001e0000>;
325 };
326
327 partition@5 {
328 label = "environment";
329 reg = <0x00260000 0x00020000>;
330 };
331
332 partition@6 {
333 label = "Kernel";
334 reg = <0x00280000 0x00500000>;
335 };
336
337 partition@7 {
338 label = "File-System";
339 reg = <0x00780000 0x0F880000>;
340 };
341 };
342 };
343 };
344
345 vbat: fixedregulator@0 { 27 vbat: fixedregulator@0 {
346 compatible = "regulator-fixed"; 28 compatible = "regulator-fixed";
347 regulator-name = "vbat"; 29 regulator-name = "vbat";
@@ -403,6 +85,393 @@
403 brightness-levels = <0 51 53 56 62 75 101 152 255>; 85 brightness-levels = <0 51 53 56 62 75 101 152 255>;
404 default-brightness-level = <8>; 86 default-brightness-level = <8>;
405 }; 87 };
88
89 panel {
90 compatible = "ti,tilcdc,panel";
91 status = "okay";
92 pinctrl-names = "default";
93 pinctrl-0 = <&lcd_pins_s0>;
94 panel-info {
95 ac-bias = <255>;
96 ac-bias-intrpt = <0>;
97 dma-burst-sz = <16>;
98 bpp = <32>;
99 fdd = <0x80>;
100 sync-edge = <0>;
101 sync-ctrl = <1>;
102 raster-order = <0>;
103 fifo-th = <0>;
104 };
105
106 display-timings {
107 800x480p62 {
108 clock-frequency = <30000000>;
109 hactive = <800>;
110 vactive = <480>;
111 hfront-porch = <39>;
112 hback-porch = <39>;
113 hsync-len = <47>;
114 vback-porch = <29>;
115 vfront-porch = <13>;
116 vsync-len = <2>;
117 hsync-active = <1>;
118 vsync-active = <1>;
119 };
120 };
121 };
122};
123
124&am33xx_pinmux {
125 pinctrl-names = "default";
126 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>;
127
128 matrix_keypad_s0: matrix_keypad_s0 {
129 pinctrl-single,pins = <
130 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */
131 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */
132 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */
133 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */
134 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */
135 >;
136 };
137
138 volume_keys_s0: volume_keys_s0 {
139 pinctrl-single,pins = <
140 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */
141 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */
142 >;
143 };
144
145 i2c0_pins: pinmux_i2c0_pins {
146 pinctrl-single,pins = <
147 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
148 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
149 >;
150 };
151
152 i2c1_pins: pinmux_i2c1_pins {
153 pinctrl-single,pins = <
154 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */
155 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */
156 >;
157 };
158
159 uart0_pins: pinmux_uart0_pins {
160 pinctrl-single,pins = <
161 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
162 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
163 >;
164 };
165
166 clkout2_pin: pinmux_clkout2_pin {
167 pinctrl-single,pins = <
168 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
169 >;
170 };
171
172 nandflash_pins_s0: nandflash_pins_s0 {
173 pinctrl-single,pins = <
174 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
175 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
176 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
177 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
178 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
179 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
180 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
181 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
182 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
183 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
184 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
185 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
186 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
187 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
188 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
189 >;
190 };
191
192 ecap0_pins: backlight_pins {
193 pinctrl-single,pins = <
194 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */
195 >;
196 };
197
198 cpsw_default: cpsw_default {
199 pinctrl-single,pins = <
200 /* Slave 1 */
201 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
202 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
203 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
204 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
205 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
206 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
207 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
208 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
209 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
210 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
211 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
212 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
213 >;
214 };
215
216 cpsw_sleep: cpsw_sleep {
217 pinctrl-single,pins = <
218 /* Slave 1 reset value */
219 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
220 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
221 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
222 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
223 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
224 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
230 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
231 >;
232 };
233
234 davinci_mdio_default: davinci_mdio_default {
235 pinctrl-single,pins = <
236 /* MDIO */
237 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
238 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
239 >;
240 };
241
242 davinci_mdio_sleep: davinci_mdio_sleep {
243 pinctrl-single,pins = <
244 /* MDIO reset value */
245 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
246 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
247 >;
248 };
249
250 lcd_pins_s0: lcd_pins_s0 {
251 pinctrl-single,pins = <
252 0x20 0x01 /* gpmc_ad8.lcd_data16, OUTPUT | MODE1 */
253 0x24 0x01 /* gpmc_ad9.lcd_data17, OUTPUT | MODE1 */
254 0x28 0x01 /* gpmc_ad10.lcd_data18, OUTPUT | MODE1 */
255 0x2c 0x01 /* gpmc_ad11.lcd_data19, OUTPUT | MODE1 */
256 0x30 0x01 /* gpmc_ad12.lcd_data20, OUTPUT | MODE1 */
257 0x34 0x01 /* gpmc_ad13.lcd_data21, OUTPUT | MODE1 */
258 0x38 0x01 /* gpmc_ad14.lcd_data22, OUTPUT | MODE1 */
259 0x3c 0x01 /* gpmc_ad15.lcd_data23, OUTPUT | MODE1 */
260 0xa0 0x00 /* lcd_data0.lcd_data0, OUTPUT | MODE0 */
261 0xa4 0x00 /* lcd_data1.lcd_data1, OUTPUT | MODE0 */
262 0xa8 0x00 /* lcd_data2.lcd_data2, OUTPUT | MODE0 */
263 0xac 0x00 /* lcd_data3.lcd_data3, OUTPUT | MODE0 */
264 0xb0 0x00 /* lcd_data4.lcd_data4, OUTPUT | MODE0 */
265 0xb4 0x00 /* lcd_data5.lcd_data5, OUTPUT | MODE0 */
266 0xb8 0x00 /* lcd_data6.lcd_data6, OUTPUT | MODE0 */
267 0xbc 0x00 /* lcd_data7.lcd_data7, OUTPUT | MODE0 */
268 0xc0 0x00 /* lcd_data8.lcd_data8, OUTPUT | MODE0 */
269 0xc4 0x00 /* lcd_data9.lcd_data9, OUTPUT | MODE0 */
270 0xc8 0x00 /* lcd_data10.lcd_data10, OUTPUT | MODE0 */
271 0xcc 0x00 /* lcd_data11.lcd_data11, OUTPUT | MODE0 */
272 0xd0 0x00 /* lcd_data12.lcd_data12, OUTPUT | MODE0 */
273 0xd4 0x00 /* lcd_data13.lcd_data13, OUTPUT | MODE0 */
274 0xd8 0x00 /* lcd_data14.lcd_data14, OUTPUT | MODE0 */
275 0xdc 0x00 /* lcd_data15.lcd_data15, OUTPUT | MODE0 */
276 0xe0 0x00 /* lcd_vsync.lcd_vsync, OUTPUT | MODE0 */
277 0xe4 0x00 /* lcd_hsync.lcd_hsync, OUTPUT | MODE0 */
278 0xe8 0x00 /* lcd_pclk.lcd_pclk, OUTPUT | MODE0 */
279 0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OUTPUT | MODE0 */
280 >;
281 };
282};
283
284&uart0 {
285 pinctrl-names = "default";
286 pinctrl-0 = <&uart0_pins>;
287
288 status = "okay";
289};
290
291&i2c0 {
292 pinctrl-names = "default";
293 pinctrl-0 = <&i2c0_pins>;
294
295 status = "okay";
296 clock-frequency = <400000>;
297
298 tps: tps@2d {
299 reg = <0x2d>;
300 };
301};
302
303&usb {
304 status = "okay";
305
306 control@44e10000 {
307 status = "okay";
308 };
309
310 usb-phy@47401300 {
311 status = "okay";
312 };
313
314 usb-phy@47401b00 {
315 status = "okay";
316 };
317
318 usb@47401000 {
319 status = "okay";
320 };
321
322 usb@47401800 {
323 status = "okay";
324 dr_mode = "host";
325 };
326
327 dma-controller@07402000 {
328 status = "okay";
329 };
330};
331
332&i2c1 {
333 pinctrl-names = "default";
334 pinctrl-0 = <&i2c1_pins>;
335
336 status = "okay";
337 clock-frequency = <100000>;
338
339 lis331dlh: lis331dlh@18 {
340 compatible = "st,lis331dlh", "st,lis3lv02d";
341 reg = <0x18>;
342 Vdd-supply = <&lis3_reg>;
343 Vdd_IO-supply = <&lis3_reg>;
344
345 st,click-single-x;
346 st,click-single-y;
347 st,click-single-z;
348 st,click-thresh-x = <10>;
349 st,click-thresh-y = <10>;
350 st,click-thresh-z = <10>;
351 st,irq1-click;
352 st,irq2-click;
353 st,wakeup-x-lo;
354 st,wakeup-x-hi;
355 st,wakeup-y-lo;
356 st,wakeup-y-hi;
357 st,wakeup-z-lo;
358 st,wakeup-z-hi;
359 st,min-limit-x = <120>;
360 st,min-limit-y = <120>;
361 st,min-limit-z = <140>;
362 st,max-limit-x = <550>;
363 st,max-limit-y = <550>;
364 st,max-limit-z = <750>;
365 };
366
367 tsl2550: tsl2550@39 {
368 compatible = "taos,tsl2550";
369 reg = <0x39>;
370 };
371
372 tmp275: tmp275@48 {
373 compatible = "ti,tmp275";
374 reg = <0x48>;
375 };
376};
377
378&lcdc {
379 status = "okay";
380};
381
382&elm {
383 status = "okay";
384};
385
386&epwmss0 {
387 status = "okay";
388
389 ecap0: ecap@48300100 {
390 status = "okay";
391 pinctrl-names = "default";
392 pinctrl-0 = <&ecap0_pins>;
393 };
394};
395
396&gpmc {
397 status = "okay";
398 pinctrl-names = "default";
399 pinctrl-0 = <&nandflash_pins_s0>;
400 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
401 nand@0,0 {
402 reg = <0 0 0>; /* CS0, offset 0 */
403 nand-bus-width = <8>;
404 ti,nand-ecc-opt = "bch8";
405 gpmc,device-nand = "true";
406 gpmc,device-width = <1>;
407 gpmc,sync-clk-ps = <0>;
408 gpmc,cs-on-ns = <0>;
409 gpmc,cs-rd-off-ns = <44>;
410 gpmc,cs-wr-off-ns = <44>;
411 gpmc,adv-on-ns = <6>;
412 gpmc,adv-rd-off-ns = <34>;
413 gpmc,adv-wr-off-ns = <44>;
414 gpmc,we-on-ns = <0>;
415 gpmc,we-off-ns = <40>;
416 gpmc,oe-on-ns = <0>;
417 gpmc,oe-off-ns = <54>;
418 gpmc,access-ns = <64>;
419 gpmc,rd-cycle-ns = <82>;
420 gpmc,wr-cycle-ns = <82>;
421 gpmc,wait-on-read = "true";
422 gpmc,wait-on-write = "true";
423 gpmc,bus-turnaround-ns = <0>;
424 gpmc,cycle2cycle-delay-ns = <0>;
425 gpmc,clk-activation-ns = <0>;
426 gpmc,wait-monitoring-ns = <0>;
427 gpmc,wr-access-ns = <40>;
428 gpmc,wr-data-mux-bus-ns = <0>;
429
430 #address-cells = <1>;
431 #size-cells = <1>;
432 elm_id = <&elm>;
433
434 /* MTD partition table */
435 partition@0 {
436 label = "SPL1";
437 reg = <0x00000000 0x000020000>;
438 };
439
440 partition@1 {
441 label = "SPL2";
442 reg = <0x00020000 0x00020000>;
443 };
444
445 partition@2 {
446 label = "SPL3";
447 reg = <0x00040000 0x00020000>;
448 };
449
450 partition@3 {
451 label = "SPL4";
452 reg = <0x00060000 0x00020000>;
453 };
454
455 partition@4 {
456 label = "U-boot";
457 reg = <0x00080000 0x001e0000>;
458 };
459
460 partition@5 {
461 label = "environment";
462 reg = <0x00260000 0x00020000>;
463 };
464
465 partition@6 {
466 label = "Kernel";
467 reg = <0x00280000 0x00500000>;
468 };
469
470 partition@7 {
471 label = "File-System";
472 reg = <0x00780000 0x0F880000>;
473 };
474 };
406}; 475};
407 476
408#include "tps65910.dtsi" 477#include "tps65910.dtsi"
@@ -477,6 +546,8 @@
477 }; 546 };
478 547
479 vmmc_reg: regulator@12 { 548 vmmc_reg: regulator@12 {
549 regulator-min-microvolt = <1800000>;
550 regulator-max-microvolt = <3300000>;
480 regulator-always-on; 551 regulator-always-on;
481 }; 552 };
482 }; 553 };
@@ -517,3 +588,17 @@
517 ti,adc-channels = <4 5 6 7>; 588 ti,adc-channels = <4 5 6 7>;
518 }; 589 };
519}; 590};
591
592&mmc1 {
593 status = "okay";
594 vmmc-supply = <&vmmc_reg>;
595 bus-width = <4>;
596};
597
598&sham {
599 status = "okay";
600};
601
602&aes {
603 status = "okay";
604};
diff --git a/arch/arm/boot/dts/am335x-evmsk.dts b/arch/arm/boot/dts/am335x-evmsk.dts
index 4f339fa91c57..5f12b28dd593 100644
--- a/arch/arm/boot/dts/am335x-evmsk.dts
+++ b/arch/arm/boot/dts/am335x-evmsk.dts
@@ -31,210 +31,6 @@
31 reg = <0x80000000 0x10000000>; /* 256 MB */ 31 reg = <0x80000000 0x10000000>; /* 256 MB */
32 }; 32 };
33 33
34 am33xx_pinmux: pinmux@44e10800 {
35 pinctrl-names = "default";
36 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
37
38 user_leds_s0: user_leds_s0 {
39 pinctrl-single,pins = <
40 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
41 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
42 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
43 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
44 >;
45 };
46
47 gpio_keys_s0: gpio_keys_s0 {
48 pinctrl-single,pins = <
49 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
50 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
51 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
52 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
53 >;
54 };
55
56 i2c0_pins: pinmux_i2c0_pins {
57 pinctrl-single,pins = <
58 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
59 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
60 >;
61 };
62
63 uart0_pins: pinmux_uart0_pins {
64 pinctrl-single,pins = <
65 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
66 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
67 >;
68 };
69
70 clkout2_pin: pinmux_clkout2_pin {
71 pinctrl-single,pins = <
72 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
73 >;
74 };
75
76 ecap2_pins: backlight_pins {
77 pinctrl-single,pins = <
78 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
79 >;
80 };
81
82 cpsw_default: cpsw_default {
83 pinctrl-single,pins = <
84 /* Slave 1 */
85 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
86 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
87 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
88 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
89 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
90 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
91 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
92 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
93 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
94 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
95 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
96 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
97
98 /* Slave 2 */
99 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
100 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
101 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
102 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
103 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
104 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
105 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
106 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
107 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
108 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
109 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
110 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
111 >;
112 };
113
114 cpsw_sleep: cpsw_sleep {
115 pinctrl-single,pins = <
116 /* Slave 1 reset value */
117 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
118 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
119 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
120 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
121 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
122 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
123 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
124 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
125 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
126 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
127 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
128 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
129
130 /* Slave 2 reset value*/
131 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
132 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
133 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
134 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
135 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
136 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
137 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
138 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
139 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
140 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
141 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
142 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
143 >;
144 };
145
146 davinci_mdio_default: davinci_mdio_default {
147 pinctrl-single,pins = <
148 /* MDIO */
149 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
150 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
151 >;
152 };
153
154 davinci_mdio_sleep: davinci_mdio_sleep {
155 pinctrl-single,pins = <
156 /* MDIO reset value */
157 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
158 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
159 >;
160 };
161 };
162
163 ocp {
164 uart0: serial@44e09000 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&uart0_pins>;
167
168 status = "okay";
169 };
170
171 i2c0: i2c@44e0b000 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&i2c0_pins>;
174
175 status = "okay";
176 clock-frequency = <400000>;
177
178 tps: tps@2d {
179 reg = <0x2d>;
180 };
181
182 lis331dlh: lis331dlh@18 {
183 compatible = "st,lis331dlh", "st,lis3lv02d";
184 reg = <0x18>;
185 Vdd-supply = <&lis3_reg>;
186 Vdd_IO-supply = <&lis3_reg>;
187
188 st,click-single-x;
189 st,click-single-y;
190 st,click-single-z;
191 st,click-thresh-x = <10>;
192 st,click-thresh-y = <10>;
193 st,click-thresh-z = <10>;
194 st,irq1-click;
195 st,irq2-click;
196 st,wakeup-x-lo;
197 st,wakeup-x-hi;
198 st,wakeup-y-lo;
199 st,wakeup-y-hi;
200 st,wakeup-z-lo;
201 st,wakeup-z-hi;
202 st,min-limit-x = <120>;
203 st,min-limit-y = <120>;
204 st,min-limit-z = <140>;
205 st,max-limit-x = <550>;
206 st,max-limit-y = <550>;
207 st,max-limit-z = <750>;
208 };
209 };
210
211 musb: usb@47400000 {
212 status = "okay";
213
214 control@44e10000 {
215 status = "okay";
216 };
217
218 usb-phy@47401300 {
219 status = "okay";
220 };
221
222 usb@47401000 {
223 status = "okay";
224 };
225 };
226
227 epwmss2: epwmss@48304000 {
228 status = "okay";
229
230 ecap2: ecap@48304100 {
231 status = "okay";
232 pinctrl-names = "default";
233 pinctrl-0 = <&ecap2_pins>;
234 };
235 };
236 };
237
238 vbat: fixedregulator@0 { 34 vbat: fixedregulator@0 {
239 compatible = "regulator-fixed"; 35 compatible = "regulator-fixed";
240 regulator-name = "vbat"; 36 regulator-name = "vbat";
@@ -321,6 +117,208 @@
321 }; 117 };
322}; 118};
323 119
120&am33xx_pinmux {
121 pinctrl-names = "default";
122 pinctrl-0 = <&gpio_keys_s0 &clkout2_pin>;
123
124 user_leds_s0: user_leds_s0 {
125 pinctrl-single,pins = <
126 0x10 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad4.gpio1_4 */
127 0x14 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad5.gpio1_5 */
128 0x18 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad6.gpio1_6 */
129 0x1c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad7.gpio1_7 */
130 >;
131 };
132
133 gpio_keys_s0: gpio_keys_s0 {
134 pinctrl-single,pins = <
135 0x94 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_oen_ren.gpio2_3 */
136 0x90 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_advn_ale.gpio2_2 */
137 0x70 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_wait0.gpio0_30 */
138 0x9c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ben0_cle.gpio2_5 */
139 >;
140 };
141
142 i2c0_pins: pinmux_i2c0_pins {
143 pinctrl-single,pins = <
144 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
145 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
146 >;
147 };
148
149 uart0_pins: pinmux_uart0_pins {
150 pinctrl-single,pins = <
151 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
152 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
153 >;
154 };
155
156 clkout2_pin: pinmux_clkout2_pin {
157 pinctrl-single,pins = <
158 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
159 >;
160 };
161
162 ecap2_pins: backlight_pins {
163 pinctrl-single,pins = <
164 0x19c 0x4 /* mcasp0_ahclkr.ecap2_in_pwm2_out MODE4 */
165 >;
166 };
167
168 cpsw_default: cpsw_default {
169 pinctrl-single,pins = <
170 /* Slave 1 */
171 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */
172 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */
173 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */
174 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */
175 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */
176 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */
177 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */
178 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */
179 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */
180 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */
181 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */
182 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */
183
184 /* Slave 2 */
185 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a0.rgmii2_tctl */
186 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a1.rgmii2_rctl */
187 0x48 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a2.rgmii2_td3 */
188 0x4c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a3.rgmii2_td2 */
189 0x50 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a4.rgmii2_td1 */
190 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a5.rgmii2_td0 */
191 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* gpmc_a6.rgmii2_tclk */
192 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a7.rgmii2_rclk */
193 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a8.rgmii2_rd3 */
194 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a9.rgmii2_rd2 */
195 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a10.rgmii2_rd1 */
196 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* gpmc_a11.rgmii2_rd0 */
197 >;
198 };
199
200 cpsw_sleep: cpsw_sleep {
201 pinctrl-single,pins = <
202 /* Slave 1 reset value */
203 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
204 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
205 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
206 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
207 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
208 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
209 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
210 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
211 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
212 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
213 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
214 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
215
216 /* Slave 2 reset value*/
217 0x40 (PIN_INPUT_PULLDOWN | MUX_MODE7)
218 0x44 (PIN_INPUT_PULLDOWN | MUX_MODE7)
219 0x48 (PIN_INPUT_PULLDOWN | MUX_MODE7)
220 0x4c (PIN_INPUT_PULLDOWN | MUX_MODE7)
221 0x50 (PIN_INPUT_PULLDOWN | MUX_MODE7)
222 0x54 (PIN_INPUT_PULLDOWN | MUX_MODE7)
223 0x58 (PIN_INPUT_PULLDOWN | MUX_MODE7)
224 0x5c (PIN_INPUT_PULLDOWN | MUX_MODE7)
225 0x60 (PIN_INPUT_PULLDOWN | MUX_MODE7)
226 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7)
227 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7)
228 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7)
229 >;
230 };
231
232 davinci_mdio_default: davinci_mdio_default {
233 pinctrl-single,pins = <
234 /* MDIO */
235 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
236 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
237 >;
238 };
239
240 davinci_mdio_sleep: davinci_mdio_sleep {
241 pinctrl-single,pins = <
242 /* MDIO reset value */
243 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
244 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
245 >;
246 };
247};
248
249&uart0 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&uart0_pins>;
252
253 status = "okay";
254};
255
256&i2c0 {
257 pinctrl-names = "default";
258 pinctrl-0 = <&i2c0_pins>;
259
260 status = "okay";
261 clock-frequency = <400000>;
262
263 tps: tps@2d {
264 reg = <0x2d>;
265 };
266
267 lis331dlh: lis331dlh@18 {
268 compatible = "st,lis331dlh", "st,lis3lv02d";
269 reg = <0x18>;
270 Vdd-supply = <&lis3_reg>;
271 Vdd_IO-supply = <&lis3_reg>;
272
273 st,click-single-x;
274 st,click-single-y;
275 st,click-single-z;
276 st,click-thresh-x = <10>;
277 st,click-thresh-y = <10>;
278 st,click-thresh-z = <10>;
279 st,irq1-click;
280 st,irq2-click;
281 st,wakeup-x-lo;
282 st,wakeup-x-hi;
283 st,wakeup-y-lo;
284 st,wakeup-y-hi;
285 st,wakeup-z-lo;
286 st,wakeup-z-hi;
287 st,min-limit-x = <120>;
288 st,min-limit-y = <120>;
289 st,min-limit-z = <140>;
290 st,max-limit-x = <550>;
291 st,max-limit-y = <550>;
292 st,max-limit-z = <750>;
293 };
294};
295
296&usb {
297 status = "okay";
298
299 control@44e10000 {
300 status = "okay";
301 };
302
303 usb-phy@47401300 {
304 status = "okay";
305 };
306
307 usb@47401000 {
308 status = "okay";
309 };
310};
311
312&epwmss2 {
313 status = "okay";
314
315 ecap2: ecap@48304100 {
316 status = "okay";
317 pinctrl-names = "default";
318 pinctrl-0 = <&ecap2_pins>;
319 };
320};
321
324#include "tps65910.dtsi" 322#include "tps65910.dtsi"
325 323
326&tps { 324&tps {
@@ -393,6 +391,8 @@
393 }; 391 };
394 392
395 vmmc_reg: regulator@12 { 393 vmmc_reg: regulator@12 {
394 regulator-min-microvolt = <1800000>;
395 regulator-max-microvolt = <3300000>;
396 regulator-always-on; 396 regulator-always-on;
397 }; 397 };
398 }; 398 };
@@ -419,3 +419,17 @@
419 phy_id = <&davinci_mdio>, <1>; 419 phy_id = <&davinci_mdio>, <1>;
420 phy-mode = "rgmii-txid"; 420 phy-mode = "rgmii-txid";
421}; 421};
422
423&mmc1 {
424 status = "okay";
425 vmmc-supply = <&vmmc_reg>;
426 bus-width = <4>;
427};
428
429&sham {
430 status = "okay";
431};
432
433&aes {
434 status = "okay";
435};
diff --git a/arch/arm/boot/dts/am335x-igep0033.dtsi b/arch/arm/boot/dts/am335x-igep0033.dtsi
new file mode 100644
index 000000000000..06eba076bfcd
--- /dev/null
+++ b/arch/arm/boot/dts/am335x-igep0033.dtsi
@@ -0,0 +1,265 @@
1/*
2 * am335x-igep0033.dtsi - Device Tree file for IGEP COM AQUILA AM335x
3 *
4 * Copyright (C) 2013 ISEE 2007 SL - http://www.isee.biz
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11/dts-v1/;
12
13#include "am33xx.dtsi"
14
15/ {
16 cpus {
17 cpu@0 {
18 cpu0-supply = <&vdd1_reg>;
19 };
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x80000000 0x10000000>; /* 256 MB */
25 };
26
27 leds {
28 pinctrl-names = "default";
29 pinctrl-0 = <&leds_pins>;
30
31 compatible = "gpio-leds";
32
33 led@0 {
34 label = "com:green:user";
35 gpios = <&gpio1 23 GPIO_ACTIVE_HIGH>;
36 default-state = "on";
37 };
38 };
39
40 vbat: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "vbat";
43 regulator-min-microvolt = <5000000>;
44 regulator-max-microvolt = <5000000>;
45 regulator-boot-on;
46 };
47};
48
49&am33xx_pinmux {
50 i2c0_pins: pinmux_i2c0_pins {
51 pinctrl-single,pins = <
52 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
53 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
54 >;
55 };
56
57 nandflash_pins: pinmux_nandflash_pins {
58 pinctrl-single,pins = <
59 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
60 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
61 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
62 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
63 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
64 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
65 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
66 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
67 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
68 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */
69 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
70 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
71 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
72 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
73 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
74 >;
75 };
76
77 uart0_pins: pinmux_uart0_pins {
78 pinctrl-single,pins = <
79 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */
80 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
81 >;
82 };
83
84 leds_pins: pinmux_leds_pins {
85 pinctrl-single,pins = <
86 0x5c (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a7.gpio1_23 */
87 >;
88 };
89};
90
91&cpsw_emac0 {
92 phy_id = <&davinci_mdio>, <0>;
93};
94
95&cpsw_emac1 {
96 phy_id = <&davinci_mdio>, <1>;
97};
98
99&elm {
100 status = "okay";
101};
102
103&gpmc {
104 status = "okay";
105 pinctrl-names = "default";
106 pinctrl-0 = <&nandflash_pins>;
107
108 ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
109
110 nand@0,0 {
111 reg = <0 0 0>; /* CS0, offset 0 */
112 nand-bus-width = <8>;
113 ti,nand-ecc-opt = "bch8";
114 gpmc,device-nand = "true";
115 gpmc,device-width = <1>;
116 gpmc,sync-clk-ps = <0>;
117 gpmc,cs-on-ns = <0>;
118 gpmc,cs-rd-off-ns = <44>;
119 gpmc,cs-wr-off-ns = <44>;
120 gpmc,adv-on-ns = <6>;
121 gpmc,adv-rd-off-ns = <34>;
122 gpmc,adv-wr-off-ns = <44>;
123 gpmc,we-on-ns = <0>;
124 gpmc,we-off-ns = <40>;
125 gpmc,oe-on-ns = <0>;
126 gpmc,oe-off-ns = <54>;
127 gpmc,access-ns = <64>;
128 gpmc,rd-cycle-ns = <82>;
129 gpmc,wr-cycle-ns = <82>;
130 gpmc,wait-on-read = "true";
131 gpmc,wait-on-write = "true";
132 gpmc,bus-turnaround-ns = <0>;
133 gpmc,cycle2cycle-delay-ns = <0>;
134 gpmc,clk-activation-ns = <0>;
135 gpmc,wait-monitoring-ns = <0>;
136 gpmc,wr-access-ns = <40>;
137 gpmc,wr-data-mux-bus-ns = <0>;
138
139 #address-cells = <1>;
140 #size-cells = <1>;
141 elm_id = <&elm>;
142
143 /* MTD partition table */
144 partition@0 {
145 label = "SPL";
146 reg = <0x00000000 0x000080000>;
147 };
148
149 partition@1 {
150 label = "U-boot";
151 reg = <0x00080000 0x001e0000>;
152 };
153
154 partition@2 {
155 label = "U-Boot Env";
156 reg = <0x00260000 0x00020000>;
157 };
158
159 partition@3 {
160 label = "Kernel";
161 reg = <0x00280000 0x00500000>;
162 };
163
164 partition@4 {
165 label = "File System";
166 reg = <0x00780000 0x007880000>;
167 };
168 };
169};
170
171&i2c0 {
172 status = "okay";
173 pinctrl-names = "default";
174 pinctrl-0 = <&i2c0_pins>;
175
176 clock-frequency = <400000>;
177
178 tps: tps@2d {
179 reg = <0x2d>;
180 };
181};
182
183&uart0 {
184 status = "okay";
185 pinctrl-names = "default";
186 pinctrl-0 = <&uart0_pins>;
187};
188
189#include "tps65910.dtsi"
190
191&tps {
192 vcc1-supply = <&vbat>;
193 vcc2-supply = <&vbat>;
194 vcc3-supply = <&vbat>;
195 vcc4-supply = <&vbat>;
196 vcc5-supply = <&vbat>;
197 vcc6-supply = <&vbat>;
198 vcc7-supply = <&vbat>;
199 vccio-supply = <&vbat>;
200
201 regulators {
202 vrtc_reg: regulator@0 {
203 regulator-always-on;
204 };
205
206 vio_reg: regulator@1 {
207 regulator-always-on;
208 };
209
210 vdd1_reg: regulator@2 {
211 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
212 regulator-name = "vdd_mpu";
213 regulator-min-microvolt = <912500>;
214 regulator-max-microvolt = <1312500>;
215 regulator-boot-on;
216 regulator-always-on;
217 };
218
219 vdd2_reg: regulator@3 {
220 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
221 regulator-name = "vdd_core";
222 regulator-min-microvolt = <912500>;
223 regulator-max-microvolt = <1150000>;
224 regulator-boot-on;
225 regulator-always-on;
226 };
227
228 vdd3_reg: regulator@4 {
229 regulator-always-on;
230 };
231
232 vdig1_reg: regulator@5 {
233 regulator-always-on;
234 };
235
236 vdig2_reg: regulator@6 {
237 regulator-always-on;
238 };
239
240 vpll_reg: regulator@7 {
241 regulator-always-on;
242 };
243
244 vdac_reg: regulator@8 {
245 regulator-always-on;
246 };
247
248 vaux1_reg: regulator@9 {
249 regulator-always-on;
250 };
251
252 vaux2_reg: regulator@10 {
253 regulator-always-on;
254 };
255
256 vaux33_reg: regulator@11 {
257 regulator-always-on;
258 };
259
260 vmmc_reg: regulator@12 {
261 regulator-always-on;
262 };
263 };
264};
265
diff --git a/arch/arm/boot/dts/am33xx.dtsi b/arch/arm/boot/dts/am33xx.dtsi
index f9c5da9c7fe1..7db3c81d1563 100644
--- a/arch/arm/boot/dts/am33xx.dtsi
+++ b/arch/arm/boot/dts/am33xx.dtsi
@@ -30,6 +30,8 @@
30 usb1 = &usb1; 30 usb1 = &usb1;
31 phy0 = &usb0_phy; 31 phy0 = &usb0_phy;
32 phy1 = &usb1_phy; 32 phy1 = &usb1_phy;
33 ethernet0 = &cpsw_emac0;
34 ethernet1 = &cpsw_emac1;
33 }; 35 };
34 36
35 cpus { 37 cpus {
@@ -57,6 +59,11 @@
57 }; 59 };
58 }; 60 };
59 61
62 pmu {
63 compatible = "arm,cortex-a8-pmu";
64 interrupts = <3>;
65 };
66
60 /* 67 /*
61 * The soc node represents the soc top level view. It is uses for IPs 68 * The soc node represents the soc top level view. It is uses for IPs
62 * that are not memory mapped in the MPU view or for the MPU itself. 69 * that are not memory mapped in the MPU view or for the MPU itself.
@@ -100,13 +107,25 @@
100 reg = <0x48200000 0x1000>; 107 reg = <0x48200000 0x1000>;
101 }; 108 };
102 109
110 edma: edma@49000000 {
111 compatible = "ti,edma3";
112 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
113 reg = <0x49000000 0x10000>,
114 <0x44e10f90 0x10>;
115 interrupts = <12 13 14>;
116 #dma-cells = <1>;
117 dma-channels = <64>;
118 ti,edma-regions = <4>;
119 ti,edma-slots = <256>;
120 };
121
103 gpio0: gpio@44e07000 { 122 gpio0: gpio@44e07000 {
104 compatible = "ti,omap4-gpio"; 123 compatible = "ti,omap4-gpio";
105 ti,hwmods = "gpio1"; 124 ti,hwmods = "gpio1";
106 gpio-controller; 125 gpio-controller;
107 #gpio-cells = <2>; 126 #gpio-cells = <2>;
108 interrupt-controller; 127 interrupt-controller;
109 #interrupt-cells = <1>; 128 #interrupt-cells = <2>;
110 reg = <0x44e07000 0x1000>; 129 reg = <0x44e07000 0x1000>;
111 interrupts = <96>; 130 interrupts = <96>;
112 }; 131 };
@@ -117,7 +136,7 @@
117 gpio-controller; 136 gpio-controller;
118 #gpio-cells = <2>; 137 #gpio-cells = <2>;
119 interrupt-controller; 138 interrupt-controller;
120 #interrupt-cells = <1>; 139 #interrupt-cells = <2>;
121 reg = <0x4804c000 0x1000>; 140 reg = <0x4804c000 0x1000>;
122 interrupts = <98>; 141 interrupts = <98>;
123 }; 142 };
@@ -128,7 +147,7 @@
128 gpio-controller; 147 gpio-controller;
129 #gpio-cells = <2>; 148 #gpio-cells = <2>;
130 interrupt-controller; 149 interrupt-controller;
131 #interrupt-cells = <1>; 150 #interrupt-cells = <2>;
132 reg = <0x481ac000 0x1000>; 151 reg = <0x481ac000 0x1000>;
133 interrupts = <32>; 152 interrupts = <32>;
134 }; 153 };
@@ -139,7 +158,7 @@
139 gpio-controller; 158 gpio-controller;
140 #gpio-cells = <2>; 159 #gpio-cells = <2>;
141 interrupt-controller; 160 interrupt-controller;
142 #interrupt-cells = <1>; 161 #interrupt-cells = <2>;
143 reg = <0x481ae000 0x1000>; 162 reg = <0x481ae000 0x1000>;
144 interrupts = <62>; 163 interrupts = <62>;
145 }; 164 };
@@ -228,6 +247,44 @@
228 status = "disabled"; 247 status = "disabled";
229 }; 248 };
230 249
250 mmc1: mmc@48060000 {
251 compatible = "ti,omap4-hsmmc";
252 ti,hwmods = "mmc1";
253 ti,dual-volt;
254 ti,needs-special-reset;
255 ti,needs-special-hs-handling;
256 dmas = <&edma 24
257 &edma 25>;
258 dma-names = "tx", "rx";
259 interrupts = <64>;
260 interrupt-parent = <&intc>;
261 reg = <0x48060000 0x1000>;
262 status = "disabled";
263 };
264
265 mmc2: mmc@481d8000 {
266 compatible = "ti,omap4-hsmmc";
267 ti,hwmods = "mmc2";
268 ti,needs-special-reset;
269 dmas = <&edma 2
270 &edma 3>;
271 dma-names = "tx", "rx";
272 interrupts = <28>;
273 interrupt-parent = <&intc>;
274 reg = <0x481d8000 0x1000>;
275 status = "disabled";
276 };
277
278 mmc3: mmc@47810000 {
279 compatible = "ti,omap4-hsmmc";
280 ti,hwmods = "mmc3";
281 ti,needs-special-reset;
282 interrupts = <29>;
283 interrupt-parent = <&intc>;
284 reg = <0x47810000 0x1000>;
285 status = "disabled";
286 };
287
231 wdt2: wdt@44e35000 { 288 wdt2: wdt@44e35000 {
232 compatible = "ti,omap3-wdt"; 289 compatible = "ti,omap3-wdt";
233 ti,hwmods = "wd_timer2"; 290 ti,hwmods = "wd_timer2";
@@ -323,6 +380,11 @@
323 interrupts = <65>; 380 interrupts = <65>;
324 ti,spi-num-cs = <2>; 381 ti,spi-num-cs = <2>;
325 ti,hwmods = "spi0"; 382 ti,hwmods = "spi0";
383 dmas = <&edma 16
384 &edma 17
385 &edma 18
386 &edma 19>;
387 dma-names = "tx0", "rx0", "tx1", "rx1";
326 status = "disabled"; 388 status = "disabled";
327 }; 389 };
328 390
@@ -334,6 +396,11 @@
334 interrupts = <125>; 396 interrupts = <125>;
335 ti,spi-num-cs = <2>; 397 ti,spi-num-cs = <2>;
336 ti,hwmods = "spi1"; 398 ti,hwmods = "spi1";
399 dmas = <&edma 42
400 &edma 43
401 &edma 44
402 &edma 45>;
403 dma-names = "tx0", "rx0", "tx1", "rx1";
337 status = "disabled"; 404 status = "disabled";
338 }; 405 };
339 406
@@ -617,6 +684,15 @@
617 status = "disabled"; 684 status = "disabled";
618 }; 685 };
619 686
687 lcdc: lcdc@4830e000 {
688 compatible = "ti,am33xx-tilcdc";
689 reg = <0x4830e000 0x1000>;
690 interrupt-parent = <&intc>;
691 interrupts = <36>;
692 ti,hwmods = "lcdc";
693 status = "disabled";
694 };
695
620 tscadc: tscadc@44e0d000 { 696 tscadc: tscadc@44e0d000 {
621 compatible = "ti,am3359-tscadc"; 697 compatible = "ti,am3359-tscadc";
622 reg = <0x44e0d000 0x1000>; 698 reg = <0x44e0d000 0x1000>;
@@ -645,5 +721,24 @@
645 #size-cells = <1>; 721 #size-cells = <1>;
646 status = "disabled"; 722 status = "disabled";
647 }; 723 };
724
725 sham: sham@53100000 {
726 compatible = "ti,omap4-sham";
727 ti,hwmods = "sham";
728 reg = <0x53100000 0x200>;
729 interrupts = <109>;
730 dmas = <&edma 36>;
731 dma-names = "rx";
732 };
733
734 aes: aes@53500000 {
735 compatible = "ti,omap4-aes";
736 ti,hwmods = "aes";
737 reg = <0x53500000 0xa0>;
738 interrupts = <103>;
739 dmas = <&edma 6>,
740 <&edma 5>;
741 dma-names = "tx", "rx";
742 };
648 }; 743 };
649}; 744};
diff --git a/arch/arm/boot/dts/am4372.dtsi b/arch/arm/boot/dts/am4372.dtsi
index ddc1df77ac52..a403172430bc 100644
--- a/arch/arm/boot/dts/am4372.dtsi
+++ b/arch/arm/boot/dts/am4372.dtsi
@@ -22,8 +22,12 @@
22 }; 22 };
23 23
24 cpus { 24 cpus {
25 #address-cells = <1>;
26 #size-cells = <0>;
25 cpu@0 { 27 cpu@0 {
26 compatible = "arm,cortex-a9"; 28 compatible = "arm,cortex-a9";
29 device_type = "cpu";
30 reg = <0>;
27 }; 31 };
28 }; 32 };
29 33
@@ -45,6 +49,47 @@
45 compatible = "ti,am4372-uart","ti,omap2-uart"; 49 compatible = "ti,am4372-uart","ti,omap2-uart";
46 reg = <0x44e09000 0x2000>; 50 reg = <0x44e09000 0x2000>;
47 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 51 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
52 ti,hwmods = "uart1";
53 };
54
55 uart1: serial@48022000 {
56 compatible = "ti,am4372-uart","ti,omap2-uart";
57 reg = <0x48022000 0x2000>;
58 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
59 ti,hwmods = "uart2";
60 status = "disabled";
61 };
62
63 uart2: serial@48024000 {
64 compatible = "ti,am4372-uart","ti,omap2-uart";
65 reg = <0x48024000 0x2000>;
66 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
67 ti,hwmods = "uart3";
68 status = "disabled";
69 };
70
71 uart3: serial@481a6000 {
72 compatible = "ti,am4372-uart","ti,omap2-uart";
73 reg = <0x481a6000 0x2000>;
74 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
75 ti,hwmods = "uart4";
76 status = "disabled";
77 };
78
79 uart4: serial@481a8000 {
80 compatible = "ti,am4372-uart","ti,omap2-uart";
81 reg = <0x481a8000 0x2000>;
82 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
83 ti,hwmods = "uart5";
84 status = "disabled";
85 };
86
87 uart5: serial@481aa000 {
88 compatible = "ti,am4372-uart","ti,omap2-uart";
89 reg = <0x481aa000 0x2000>;
90 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
91 ti,hwmods = "uart6";
92 status = "disabled";
48 }; 93 };
49 94
50 timer1: timer@44e31000 { 95 timer1: timer@44e31000 {
@@ -52,17 +97,333 @@
52 reg = <0x44e31000 0x400>; 97 reg = <0x44e31000 0x400>;
53 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 98 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
54 ti,timer-alwon; 99 ti,timer-alwon;
100 ti,hwmods = "timer1";
55 }; 101 };
56 102
57 timer2: timer@48040000 { 103 timer2: timer@48040000 {
58 compatible = "ti,am4372-timer","ti,am335x-timer"; 104 compatible = "ti,am4372-timer","ti,am335x-timer";
59 reg = <0x48040000 0x400>; 105 reg = <0x48040000 0x400>;
60 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 106 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
107 ti,hwmods = "timer2";
108 };
109
110 timer3: timer@48042000 {
111 compatible = "ti,am4372-timer","ti,am335x-timer";
112 reg = <0x48042000 0x400>;
113 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
114 ti,hwmods = "timer3";
115 status = "disabled";
116 };
117
118 timer4: timer@48044000 {
119 compatible = "ti,am4372-timer","ti,am335x-timer";
120 reg = <0x48044000 0x400>;
121 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
122 ti,timer-pwm;
123 ti,hwmods = "timer4";
124 status = "disabled";
125 };
126
127 timer5: timer@48046000 {
128 compatible = "ti,am4372-timer","ti,am335x-timer";
129 reg = <0x48046000 0x400>;
130 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
131 ti,timer-pwm;
132 ti,hwmods = "timer5";
133 status = "disabled";
134 };
135
136 timer6: timer@48048000 {
137 compatible = "ti,am4372-timer","ti,am335x-timer";
138 reg = <0x48048000 0x400>;
139 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
140 ti,timer-pwm;
141 ti,hwmods = "timer6";
142 status = "disabled";
143 };
144
145 timer7: timer@4804a000 {
146 compatible = "ti,am4372-timer","ti,am335x-timer";
147 reg = <0x4804a000 0x400>;
148 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
149 ti,timer-pwm;
150 ti,hwmods = "timer7";
151 status = "disabled";
152 };
153
154 timer8: timer@481c1000 {
155 compatible = "ti,am4372-timer","ti,am335x-timer";
156 reg = <0x481c1000 0x400>;
157 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
158 ti,hwmods = "timer8";
159 status = "disabled";
160 };
161
162 timer9: timer@4833d000 {
163 compatible = "ti,am4372-timer","ti,am335x-timer";
164 reg = <0x4833d000 0x400>;
165 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
166 ti,hwmods = "timer9";
167 status = "disabled";
168 };
169
170 timer10: timer@4833f000 {
171 compatible = "ti,am4372-timer","ti,am335x-timer";
172 reg = <0x4833f000 0x400>;
173 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
174 ti,hwmods = "timer10";
175 status = "disabled";
176 };
177
178 timer11: timer@48341000 {
179 compatible = "ti,am4372-timer","ti,am335x-timer";
180 reg = <0x48341000 0x400>;
181 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "timer11";
183 status = "disabled";
61 }; 184 };
62 185
63 counter32k: counter@44e86000 { 186 counter32k: counter@44e86000 {
64 compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 187 compatible = "ti,am4372-counter32k","ti,omap-counter32k";
65 reg = <0x44e86000 0x40>; 188 reg = <0x44e86000 0x40>;
189 ti,hwmods = "counter_32k";
190 };
191
192 rtc@44e3e000 {
193 compatible = "ti,am4372-rtc","ti,da830-rtc";
194 reg = <0x44e3e000 0x1000>;
195 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH
196 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
197 ti,hwmods = "rtc";
198 status = "disabled";
199 };
200
201 wdt@44e35000 {
202 compatible = "ti,am4372-wdt","ti,omap3-wdt";
203 reg = <0x44e35000 0x1000>;
204 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
205 ti,hwmods = "wd_timer2";
206 status = "disabled";
207 };
208
209 gpio0: gpio@44e07000 {
210 compatible = "ti,am4372-gpio","ti,omap4-gpio";
211 reg = <0x44e07000 0x1000>;
212 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
213 gpio-controller;
214 #gpio-cells = <2>;
215 interrupt-controller;
216 #interrupt-cells = <2>;
217 ti,hwmods = "gpio1";
218 status = "disabled";
219 };
220
221 gpio1: gpio@4804c000 {
222 compatible = "ti,am4372-gpio","ti,omap4-gpio";
223 reg = <0x4804c000 0x1000>;
224 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
225 gpio-controller;
226 #gpio-cells = <2>;
227 interrupt-controller;
228 #interrupt-cells = <2>;
229 ti,hwmods = "gpio2";
230 status = "disabled";
231 };
232
233 gpio2: gpio@481ac000 {
234 compatible = "ti,am4372-gpio","ti,omap4-gpio";
235 reg = <0x481ac000 0x1000>;
236 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
237 gpio-controller;
238 #gpio-cells = <2>;
239 interrupt-controller;
240 #interrupt-cells = <2>;
241 ti,hwmods = "gpio3";
242 status = "disabled";
243 };
244
245 gpio3: gpio@481ae000 {
246 compatible = "ti,am4372-gpio","ti,omap4-gpio";
247 reg = <0x481ae000 0x1000>;
248 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
249 gpio-controller;
250 #gpio-cells = <2>;
251 interrupt-controller;
252 #interrupt-cells = <2>;
253 ti,hwmods = "gpio4";
254 status = "disabled";
255 };
256
257 gpio4: gpio@48320000 {
258 compatible = "ti,am4372-gpio","ti,omap4-gpio";
259 reg = <0x48320000 0x1000>;
260 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
261 gpio-controller;
262 #gpio-cells = <2>;
263 interrupt-controller;
264 #interrupt-cells = <2>;
265 ti,hwmods = "gpio5";
266 status = "disabled";
267 };
268
269 gpio5: gpio@48322000 {
270 compatible = "ti,am4372-gpio","ti,omap4-gpio";
271 reg = <0x48322000 0x1000>;
272 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
273 gpio-controller;
274 #gpio-cells = <2>;
275 interrupt-controller;
276 #interrupt-cells = <2>;
277 ti,hwmods = "gpio6";
278 status = "disabled";
279 };
280
281 i2c0: i2c@44e0b000 {
282 compatible = "ti,am4372-i2c","ti,omap4-i2c";
283 reg = <0x44e0b000 0x1000>;
284 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
285 ti,hwmods = "i2c1";
286 #address-cells = <1>;
287 #size-cells = <0>;
288 status = "disabled";
289 };
290
291 i2c1: i2c@4802a000 {
292 compatible = "ti,am4372-i2c","ti,omap4-i2c";
293 reg = <0x4802a000 0x1000>;
294 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
295 ti,hwmods = "i2c2";
296 #address-cells = <1>;
297 #size-cells = <0>;
298 status = "disabled";
299 };
300
301 i2c2: i2c@4819c000 {
302 compatible = "ti,am4372-i2c","ti,omap4-i2c";
303 reg = <0x4819c000 0x1000>;
304 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
305 ti,hwmods = "i2c3";
306 #address-cells = <1>;
307 #size-cells = <0>;
308 status = "disabled";
309 };
310
311 spi0: spi@48030000 {
312 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
313 reg = <0x48030000 0x400>;
314 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
315 ti,hwmods = "spi0";
316 #address-cells = <1>;
317 #size-cells = <0>;
318 status = "disabled";
319 };
320
321 spi1: spi@481a0000 {
322 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
323 reg = <0x481a0000 0x400>;
324 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
325 ti,hwmods = "spi1";
326 #address-cells = <1>;
327 #size-cells = <0>;
328 status = "disabled";
329 };
330
331 spi2: spi@481a2000 {
332 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
333 reg = <0x481a2000 0x400>;
334 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
335 ti,hwmods = "spi2";
336 #address-cells = <1>;
337 #size-cells = <0>;
338 status = "disabled";
339 };
340
341 spi3: spi@481a4000 {
342 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
343 reg = <0x481a4000 0x400>;
344 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
345 ti,hwmods = "spi3";
346 #address-cells = <1>;
347 #size-cells = <0>;
348 status = "disabled";
349 };
350
351 spi4: spi@48345000 {
352 compatible = "ti,am4372-mcspi","ti,omap4-mcspi";
353 reg = <0x48345000 0x400>;
354 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
355 ti,hwmods = "spi4";
356 #address-cells = <1>;
357 #size-cells = <0>;
358 status = "disabled";
359 };
360
361 mac: ethernet@4a100000 {
362 compatible = "ti,am4372-cpsw","ti,cpsw";
363 reg = <0x4a100000 0x800
364 0x4a101200 0x100>;
365 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH
366 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH
367 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH
368 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
369 ti,hwmods = "cpgmac0";
370 status = "disabled";
371 };
372
373 epwmss0: epwmss@48300000 {
374 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
375 reg = <0x48300000 0x10>;
376 ti,hwmods = "epwmss0";
377 status = "disabled";
378 };
379
380 epwmss1: epwmss@48302000 {
381 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
382 reg = <0x48302000 0x10>;
383 ti,hwmods = "epwmss1";
384 status = "disabled";
385 };
386
387 epwmss2: epwmss@48304000 {
388 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
389 reg = <0x48304000 0x10>;
390 ti,hwmods = "epwmss2";
391 status = "disabled";
392 };
393
394 epwmss3: epwmss@48306000 {
395 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
396 reg = <0x48306000 0x10>;
397 ti,hwmods = "epwmss3";
398 status = "disabled";
399 };
400
401 epwmss4: epwmss@48308000 {
402 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
403 reg = <0x48308000 0x10>;
404 ti,hwmods = "epwmss4";
405 status = "disabled";
406 };
407
408 epwmss5: epwmss@4830a000 {
409 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss";
410 reg = <0x4830a000 0x10>;
411 ti,hwmods = "epwmss5";
412 status = "disabled";
413 };
414
415 aes: aes@53501000 {
416 compatible = "ti,omap4-aes";
417 ti,hwmods = "aes";
418 reg = <0x53501000 0xa0>;
419 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
420 };
421
422 des: des@53701000 {
423 compatible = "ti,omap4-des";
424 ti,hwmods = "des";
425 reg = <0x53701000 0xa0>;
426 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
66 }; 427 };
67 }; 428 };
68}; 429};
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
new file mode 100644
index 000000000000..3abf5f41e5cc
--- /dev/null
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -0,0 +1,271 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8/dts-v1/;
9
10#include "dra7.dtsi"
11
12/ {
13 model = "TI DRA7";
14 compatible = "ti,dra7-evm", "ti,dra752", "ti,dra7";
15
16 memory {
17 device_type = "memory";
18 reg = <0x80000000 0x60000000>; /* 1536 MB */
19 };
20
21 mmc2_3v3: fixedregulator-mmc2 {
22 compatible = "regulator-fixed";
23 regulator-name = "mmc2_3v3";
24 regulator-min-microvolt = <3300000>;
25 regulator-max-microvolt = <3300000>;
26 };
27};
28
29&dra7_pmx_core {
30 i2c1_pins: pinmux_i2c1_pins {
31 pinctrl-single,pins = <
32 0x400 (PIN_INPUT | MUX_MODE0) /* i2c1_sda */
33 0x404 (PIN_INPUT | MUX_MODE0) /* i2c1_scl */
34 >;
35 };
36
37 i2c2_pins: pinmux_i2c2_pins {
38 pinctrl-single,pins = <
39 0x408 (PIN_INPUT | MUX_MODE0) /* i2c2_sda */
40 0x40c (PIN_INPUT | MUX_MODE0) /* i2c2_scl */
41 >;
42 };
43
44 i2c3_pins: pinmux_i2c3_pins {
45 pinctrl-single,pins = <
46 0x410 (PIN_INPUT | MUX_MODE0) /* i2c3_sda */
47 0x414 (PIN_INPUT | MUX_MODE0) /* i2c3_scl */
48 >;
49 };
50
51 mcspi1_pins: pinmux_mcspi1_pins {
52 pinctrl-single,pins = <
53 0x3a4 (PIN_INPUT | MUX_MODE0) /* spi2_clk */
54 0x3a8 (PIN_INPUT | MUX_MODE0) /* spi2_d1 */
55 0x3ac (PIN_INPUT | MUX_MODE0) /* spi2_d0 */
56 0x3b0 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
57 0x3b4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs1 */
58 0x3b8 (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs2 */
59 0x3bc (PIN_INPUT_SLEW | MUX_MODE6) /* spi2_cs3 */
60 >;
61 };
62
63 mcspi2_pins: pinmux_mcspi2_pins {
64 pinctrl-single,pins = <
65 0x3c0 (PIN_INPUT | MUX_MODE0) /* spi2_sclk */
66 0x3c4 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
67 0x3c8 (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_d1 */
68 0x3cc (PIN_INPUT_SLEW | MUX_MODE0) /* spi2_cs0 */
69 >;
70 };
71
72 uart1_pins: pinmux_uart1_pins {
73 pinctrl-single,pins = <
74 0x3e0 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_rxd */
75 0x3e4 (PIN_INPUT_SLEW | MUX_MODE0) /* uart1_txd */
76 0x3e8 (PIN_INPUT | MUX_MODE3) /* uart1_ctsn */
77 0x3ec (PIN_INPUT | MUX_MODE3) /* uart1_rtsn */
78 >;
79 };
80
81 uart2_pins: pinmux_uart2_pins {
82 pinctrl-single,pins = <
83 0x3f0 (PIN_INPUT | MUX_MODE0) /* uart2_rxd */
84 0x3f4 (PIN_INPUT | MUX_MODE0) /* uart2_txd */
85 0x3f8 (PIN_INPUT | MUX_MODE0) /* uart2_ctsn */
86 0x3fc (PIN_INPUT | MUX_MODE0) /* uart2_rtsn */
87 >;
88 };
89
90 uart3_pins: pinmux_uart3_pins {
91 pinctrl-single,pins = <
92 0x248 (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_rxd */
93 0x24c (PIN_INPUT_SLEW | MUX_MODE0) /* uart3_txd */
94 >;
95 };
96};
97
98&i2c1 {
99 status = "okay";
100 pinctrl-names = "default";
101 pinctrl-0 = <&i2c1_pins>;
102 clock-frequency = <400000>;
103
104 tps659038: tps659038@58 {
105 compatible = "ti,tps659038";
106 reg = <0x58>;
107
108 tps659038_pmic {
109 compatible = "ti,tps659038-pmic";
110
111 regulators {
112 smps123_reg: smps123 {
113 /* VDD_MPU */
114 regulator-name = "smps123";
115 regulator-min-microvolt = < 850000>;
116 regulator-max-microvolt = <1250000>;
117 regulator-always-on;
118 regulator-boot-on;
119 };
120
121 smps45_reg: smps45 {
122 /* VDD_DSPEVE */
123 regulator-name = "smps45";
124 regulator-min-microvolt = < 850000>;
125 regulator-max-microvolt = <1150000>;
126 regulator-boot-on;
127 };
128
129 smps6_reg: smps6 {
130 /* VDD_GPU - over VDD_SMPS6 */
131 regulator-name = "smps6";
132 regulator-min-microvolt = <850000>;
133 regulator-max-microvolt = <12500000>;
134 regulator-boot-on;
135 };
136
137 smps7_reg: smps7 {
138 /* CORE_VDD */
139 regulator-name = "smps7";
140 regulator-min-microvolt = <850000>;
141 regulator-max-microvolt = <1030000>;
142 regulator-always-on;
143 regulator-boot-on;
144 };
145
146 smps8_reg: smps8 {
147 /* VDD_IVAHD */
148 regulator-name = "smps8";
149 regulator-min-microvolt = < 850000>;
150 regulator-max-microvolt = <1250000>;
151 regulator-boot-on;
152 };
153
154 smps9_reg: smps9 {
155 /* VDDS1V8 */
156 regulator-name = "smps9";
157 regulator-min-microvolt = <1800000>;
158 regulator-max-microvolt = <1800000>;
159 regulator-always-on;
160 regulator-boot-on;
161 };
162
163 ldo1_reg: ldo1 {
164 /* LDO1_OUT --> SDIO */
165 regulator-name = "ldo1";
166 regulator-min-microvolt = <1800000>;
167 regulator-max-microvolt = <3300000>;
168 regulator-boot-on;
169 };
170
171 ldo2_reg: ldo2 {
172 /* VDD_RTCIO */
173 /* LDO2 -> VDDSHV5, LDO2 also goes to CAN_PHY_3V3 */
174 regulator-name = "ldo2";
175 regulator-min-microvolt = <3300000>;
176 regulator-max-microvolt = <3300000>;
177 regulator-boot-on;
178 };
179
180 ldo3_reg: ldo3 {
181 /* VDDA_1V8_PHY */
182 regulator-name = "ldo3";
183 regulator-min-microvolt = <1800000>;
184 regulator-max-microvolt = <1800000>;
185 regulator-boot-on;
186 };
187
188 ldo9_reg: ldo9 {
189 /* VDD_RTC */
190 regulator-name = "ldo9";
191 regulator-min-microvolt = <1050000>;
192 regulator-max-microvolt = <1050000>;
193 regulator-boot-on;
194 };
195
196 ldoln_reg: ldoln {
197 /* VDDA_1V8_PLL */
198 regulator-name = "ldoln";
199 regulator-min-microvolt = <1800000>;
200 regulator-max-microvolt = <1800000>;
201 regulator-always-on;
202 regulator-boot-on;
203 };
204
205 ldousb_reg: ldousb {
206 /* VDDA_3V_USB: VDDA_USBHS33 */
207 regulator-name = "ldousb";
208 regulator-min-microvolt = <3300000>;
209 regulator-max-microvolt = <3300000>;
210 regulator-boot-on;
211 };
212 };
213 };
214 };
215};
216
217&i2c2 {
218 status = "okay";
219 pinctrl-names = "default";
220 pinctrl-0 = <&i2c2_pins>;
221 clock-frequency = <400000>;
222};
223
224&i2c3 {
225 status = "okay";
226 pinctrl-names = "default";
227 pinctrl-0 = <&i2c3_pins>;
228 clock-frequency = <3400000>;
229};
230
231&mcspi1 {
232 status = "okay";
233 pinctrl-names = "default";
234 pinctrl-0 = <&mcspi1_pins>;
235};
236
237&mcspi2 {
238 status = "okay";
239 pinctrl-names = "default";
240 pinctrl-0 = <&mcspi2_pins>;
241};
242
243&uart1 {
244 status = "okay";
245 pinctrl-names = "default";
246 pinctrl-0 = <&uart1_pins>;
247};
248
249&uart2 {
250 status = "okay";
251 pinctrl-names = "default";
252 pinctrl-0 = <&uart2_pins>;
253};
254
255&uart3 {
256 status = "okay";
257 pinctrl-names = "default";
258 pinctrl-0 = <&uart3_pins>;
259};
260
261&mmc1 {
262 status = "okay";
263 vmmc-supply = <&ldo1_reg>;
264 bus-width = <4>;
265};
266
267&mmc2 {
268 status = "okay";
269 vmmc-supply = <&mmc2_3v3>;
270 bus-width = <8>;
271};
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
new file mode 100644
index 000000000000..c01ef769761f
--- /dev/null
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -0,0 +1,575 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 * Based on "omap4.dtsi"
8 */
9
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11#include <dt-bindings/pinctrl/dra.h>
12
13#include "skeleton.dtsi"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18
19 compatible = "ti,dra7xx";
20 interrupt-parent = <&gic>;
21
22 aliases {
23 serial0 = &uart1;
24 serial1 = &uart2;
25 serial2 = &uart3;
26 serial3 = &uart4;
27 serial4 = &uart5;
28 serial5 = &uart6;
29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a15";
38 reg = <0>;
39 };
40 cpu@1 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a15";
43 reg = <1>;
44 };
45 };
46
47 timer {
48 compatible = "arm,armv7-timer";
49 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
50 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
51 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
52 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
53 };
54
55 gic: interrupt-controller@48211000 {
56 compatible = "arm,cortex-a15-gic";
57 interrupt-controller;
58 #interrupt-cells = <3>;
59 reg = <0x48211000 0x1000>,
60 <0x48212000 0x1000>,
61 <0x48214000 0x2000>,
62 <0x48216000 0x2000>;
63 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
64 };
65
66 /*
67 * The soc node represents the soc top level view. It is uses for IPs
68 * that are not memory mapped in the MPU view or for the MPU itself.
69 */
70 soc {
71 compatible = "ti,omap-infra";
72 mpu {
73 compatible = "ti,omap5-mpu";
74 ti,hwmods = "mpu";
75 };
76 };
77
78 /*
79 * XXX: Use a flat representation of the SOC interconnect.
80 * The real OMAP interconnect network is quite complex.
81 * Since that will not bring real advantage to represent that in DT for
82 * the moment, just use a fake OCP bus entry to represent the whole bus
83 * hierarchy.
84 */
85 ocp {
86 compatible = "ti,omap4-l3-noc", "simple-bus";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 ranges;
90 ti,hwmods = "l3_main_1", "l3_main_2";
91 reg = <0x44000000 0x2000>,
92 <0x44800000 0x3000>;
93 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
94 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
95
96 counter32k: counter@4ae04000 {
97 compatible = "ti,omap-counter32k";
98 reg = <0x4ae04000 0x40>;
99 ti,hwmods = "counter_32k";
100 };
101
102 dra7_pmx_core: pinmux@4a003400 {
103 compatible = "pinctrl-single";
104 reg = <0x4a003400 0x0464>;
105 #address-cells = <1>;
106 #size-cells = <0>;
107 pinctrl-single,register-width = <32>;
108 pinctrl-single,function-mask = <0x3fffffff>;
109 };
110
111 sdma: dma-controller@4a056000 {
112 compatible = "ti,omap4430-sdma";
113 reg = <0x4a056000 0x1000>;
114 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
115 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
116 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
117 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
118 #dma-cells = <1>;
119 #dma-channels = <32>;
120 #dma-requests = <127>;
121 };
122
123 gpio1: gpio@4ae10000 {
124 compatible = "ti,omap4-gpio";
125 reg = <0x4ae10000 0x200>;
126 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
127 ti,hwmods = "gpio1";
128 gpio-controller;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <1>;
132 };
133
134 gpio2: gpio@48055000 {
135 compatible = "ti,omap4-gpio";
136 reg = <0x48055000 0x200>;
137 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
138 ti,hwmods = "gpio2";
139 gpio-controller;
140 #gpio-cells = <2>;
141 interrupt-controller;
142 #interrupt-cells = <1>;
143 };
144
145 gpio3: gpio@48057000 {
146 compatible = "ti,omap4-gpio";
147 reg = <0x48057000 0x200>;
148 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
149 ti,hwmods = "gpio3";
150 gpio-controller;
151 #gpio-cells = <2>;
152 interrupt-controller;
153 #interrupt-cells = <1>;
154 };
155
156 gpio4: gpio@48059000 {
157 compatible = "ti,omap4-gpio";
158 reg = <0x48059000 0x200>;
159 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
160 ti,hwmods = "gpio4";
161 gpio-controller;
162 #gpio-cells = <2>;
163 interrupt-controller;
164 #interrupt-cells = <1>;
165 };
166
167 gpio5: gpio@4805b000 {
168 compatible = "ti,omap4-gpio";
169 reg = <0x4805b000 0x200>;
170 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
171 ti,hwmods = "gpio5";
172 gpio-controller;
173 #gpio-cells = <2>;
174 interrupt-controller;
175 #interrupt-cells = <1>;
176 };
177
178 gpio6: gpio@4805d000 {
179 compatible = "ti,omap4-gpio";
180 reg = <0x4805d000 0x200>;
181 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
182 ti,hwmods = "gpio6";
183 gpio-controller;
184 #gpio-cells = <2>;
185 interrupt-controller;
186 #interrupt-cells = <1>;
187 };
188
189 gpio7: gpio@48051000 {
190 compatible = "ti,omap4-gpio";
191 reg = <0x48051000 0x200>;
192 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
193 ti,hwmods = "gpio7";
194 gpio-controller;
195 #gpio-cells = <2>;
196 interrupt-controller;
197 #interrupt-cells = <1>;
198 };
199
200 gpio8: gpio@48053000 {
201 compatible = "ti,omap4-gpio";
202 reg = <0x48053000 0x200>;
203 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
204 ti,hwmods = "gpio8";
205 gpio-controller;
206 #gpio-cells = <2>;
207 interrupt-controller;
208 #interrupt-cells = <1>;
209 };
210
211 uart1: serial@4806a000 {
212 compatible = "ti,omap4-uart";
213 reg = <0x4806a000 0x100>;
214 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
215 ti,hwmods = "uart1";
216 clock-frequency = <48000000>;
217 status = "disabled";
218 };
219
220 uart2: serial@4806c000 {
221 compatible = "ti,omap4-uart";
222 reg = <0x4806c000 0x100>;
223 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
224 ti,hwmods = "uart2";
225 clock-frequency = <48000000>;
226 status = "disabled";
227 };
228
229 uart3: serial@48020000 {
230 compatible = "ti,omap4-uart";
231 reg = <0x48020000 0x100>;
232 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
233 ti,hwmods = "uart3";
234 clock-frequency = <48000000>;
235 status = "disabled";
236 };
237
238 uart4: serial@4806e000 {
239 compatible = "ti,omap4-uart";
240 reg = <0x4806e000 0x100>;
241 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
242 ti,hwmods = "uart4";
243 clock-frequency = <48000000>;
244 status = "disabled";
245 };
246
247 uart5: serial@48066000 {
248 compatible = "ti,omap4-uart";
249 reg = <0x48066000 0x100>;
250 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
251 ti,hwmods = "uart5";
252 clock-frequency = <48000000>;
253 status = "disabled";
254 };
255
256 uart6: serial@48068000 {
257 compatible = "ti,omap4-uart";
258 reg = <0x48068000 0x100>;
259 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
260 ti,hwmods = "uart6";
261 clock-frequency = <48000000>;
262 status = "disabled";
263 };
264
265 uart7: serial@48420000 {
266 compatible = "ti,omap4-uart";
267 reg = <0x48420000 0x100>;
268 ti,hwmods = "uart7";
269 clock-frequency = <48000000>;
270 status = "disabled";
271 };
272
273 uart8: serial@48422000 {
274 compatible = "ti,omap4-uart";
275 reg = <0x48422000 0x100>;
276 ti,hwmods = "uart8";
277 clock-frequency = <48000000>;
278 status = "disabled";
279 };
280
281 uart9: serial@48424000 {
282 compatible = "ti,omap4-uart";
283 reg = <0x48424000 0x100>;
284 ti,hwmods = "uart9";
285 clock-frequency = <48000000>;
286 status = "disabled";
287 };
288
289 uart10: serial@4ae2b000 {
290 compatible = "ti,omap4-uart";
291 reg = <0x4ae2b000 0x100>;
292 ti,hwmods = "uart10";
293 clock-frequency = <48000000>;
294 status = "disabled";
295 };
296
297 timer1: timer@4ae18000 {
298 compatible = "ti,omap5430-timer";
299 reg = <0x4ae18000 0x80>;
300 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
301 ti,hwmods = "timer1";
302 ti,timer-alwon;
303 };
304
305 timer2: timer@48032000 {
306 compatible = "ti,omap5430-timer";
307 reg = <0x48032000 0x80>;
308 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
309 ti,hwmods = "timer2";
310 };
311
312 timer3: timer@48034000 {
313 compatible = "ti,omap5430-timer";
314 reg = <0x48034000 0x80>;
315 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
316 ti,hwmods = "timer3";
317 };
318
319 timer4: timer@48036000 {
320 compatible = "ti,omap5430-timer";
321 reg = <0x48036000 0x80>;
322 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
323 ti,hwmods = "timer4";
324 };
325
326 timer5: timer@48820000 {
327 compatible = "ti,omap5430-timer";
328 reg = <0x48820000 0x80>;
329 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
330 ti,hwmods = "timer5";
331 ti,timer-dsp;
332 };
333
334 timer6: timer@48822000 {
335 compatible = "ti,omap5430-timer";
336 reg = <0x48822000 0x80>;
337 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
338 ti,hwmods = "timer6";
339 ti,timer-dsp;
340 ti,timer-pwm;
341 };
342
343 timer7: timer@48824000 {
344 compatible = "ti,omap5430-timer";
345 reg = <0x48824000 0x80>;
346 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
347 ti,hwmods = "timer7";
348 ti,timer-dsp;
349 };
350
351 timer8: timer@48826000 {
352 compatible = "ti,omap5430-timer";
353 reg = <0x48826000 0x80>;
354 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
355 ti,hwmods = "timer8";
356 ti,timer-dsp;
357 ti,timer-pwm;
358 };
359
360 timer9: timer@4803e000 {
361 compatible = "ti,omap5430-timer";
362 reg = <0x4803e000 0x80>;
363 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
364 ti,hwmods = "timer9";
365 };
366
367 timer10: timer@48086000 {
368 compatible = "ti,omap5430-timer";
369 reg = <0x48086000 0x80>;
370 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
371 ti,hwmods = "timer10";
372 };
373
374 timer11: timer@48088000 {
375 compatible = "ti,omap5430-timer";
376 reg = <0x48088000 0x80>;
377 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
378 ti,hwmods = "timer11";
379 ti,timer-pwm;
380 };
381
382 timer13: timer@48828000 {
383 compatible = "ti,omap5430-timer";
384 reg = <0x48828000 0x80>;
385 ti,hwmods = "timer13";
386 status = "disabled";
387 };
388
389 timer14: timer@4882a000 {
390 compatible = "ti,omap5430-timer";
391 reg = <0x4882a000 0x80>;
392 ti,hwmods = "timer14";
393 status = "disabled";
394 };
395
396 timer15: timer@4882c000 {
397 compatible = "ti,omap5430-timer";
398 reg = <0x4882c000 0x80>;
399 ti,hwmods = "timer15";
400 status = "disabled";
401 };
402
403 timer16: timer@4882e000 {
404 compatible = "ti,omap5430-timer";
405 reg = <0x4882e000 0x80>;
406 ti,hwmods = "timer16";
407 status = "disabled";
408 };
409
410 wdt2: wdt@4ae14000 {
411 compatible = "ti,omap4-wdt";
412 reg = <0x4ae14000 0x80>;
413 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
414 ti,hwmods = "wd_timer2";
415 };
416
417 i2c1: i2c@48070000 {
418 compatible = "ti,omap4-i2c";
419 reg = <0x48070000 0x100>;
420 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
421 #address-cells = <1>;
422 #size-cells = <0>;
423 ti,hwmods = "i2c1";
424 status = "disabled";
425 };
426
427 i2c2: i2c@48072000 {
428 compatible = "ti,omap4-i2c";
429 reg = <0x48072000 0x100>;
430 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
431 #address-cells = <1>;
432 #size-cells = <0>;
433 ti,hwmods = "i2c2";
434 status = "disabled";
435 };
436
437 i2c3: i2c@48060000 {
438 compatible = "ti,omap4-i2c";
439 reg = <0x48060000 0x100>;
440 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
441 #address-cells = <1>;
442 #size-cells = <0>;
443 ti,hwmods = "i2c3";
444 status = "disabled";
445 };
446
447 i2c4: i2c@4807a000 {
448 compatible = "ti,omap4-i2c";
449 reg = <0x4807a000 0x100>;
450 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
451 #address-cells = <1>;
452 #size-cells = <0>;
453 ti,hwmods = "i2c4";
454 status = "disabled";
455 };
456
457 i2c5: i2c@4807c000 {
458 compatible = "ti,omap4-i2c";
459 reg = <0x4807c000 0x100>;
460 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 ti,hwmods = "i2c5";
464 status = "disabled";
465 };
466
467 mmc1: mmc@4809c000 {
468 compatible = "ti,omap4-hsmmc";
469 reg = <0x4809c000 0x400>;
470 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
471 ti,hwmods = "mmc1";
472 ti,dual-volt;
473 ti,needs-special-reset;
474 dmas = <&sdma 61>, <&sdma 62>;
475 dma-names = "tx", "rx";
476 status = "disabled";
477 };
478
479 mmc2: mmc@480b4000 {
480 compatible = "ti,omap4-hsmmc";
481 reg = <0x480b4000 0x400>;
482 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
483 ti,hwmods = "mmc2";
484 ti,needs-special-reset;
485 dmas = <&sdma 47>, <&sdma 48>;
486 dma-names = "tx", "rx";
487 status = "disabled";
488 };
489
490 mmc3: mmc@480ad000 {
491 compatible = "ti,omap4-hsmmc";
492 reg = <0x480ad000 0x400>;
493 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
494 ti,hwmods = "mmc3";
495 ti,needs-special-reset;
496 dmas = <&sdma 77>, <&sdma 78>;
497 dma-names = "tx", "rx";
498 status = "disabled";
499 };
500
501 mmc4: mmc@480d1000 {
502 compatible = "ti,omap4-hsmmc";
503 reg = <0x480d1000 0x400>;
504 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
505 ti,hwmods = "mmc4";
506 ti,needs-special-reset;
507 dmas = <&sdma 57>, <&sdma 58>;
508 dma-names = "tx", "rx";
509 status = "disabled";
510 };
511
512 mcspi1: spi@48098000 {
513 compatible = "ti,omap4-mcspi";
514 reg = <0x48098000 0x200>;
515 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
516 #address-cells = <1>;
517 #size-cells = <0>;
518 ti,hwmods = "mcspi1";
519 ti,spi-num-cs = <4>;
520 dmas = <&sdma 35>,
521 <&sdma 36>,
522 <&sdma 37>,
523 <&sdma 38>,
524 <&sdma 39>,
525 <&sdma 40>,
526 <&sdma 41>,
527 <&sdma 42>;
528 dma-names = "tx0", "rx0", "tx1", "rx1",
529 "tx2", "rx2", "tx3", "rx3";
530 status = "disabled";
531 };
532
533 mcspi2: spi@4809a000 {
534 compatible = "ti,omap4-mcspi";
535 reg = <0x4809a000 0x200>;
536 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
537 #address-cells = <1>;
538 #size-cells = <0>;
539 ti,hwmods = "mcspi2";
540 ti,spi-num-cs = <2>;
541 dmas = <&sdma 43>,
542 <&sdma 44>,
543 <&sdma 45>,
544 <&sdma 46>;
545 dma-names = "tx0", "rx0", "tx1", "rx1";
546 status = "disabled";
547 };
548
549 mcspi3: spi@480b8000 {
550 compatible = "ti,omap4-mcspi";
551 reg = <0x480b8000 0x200>;
552 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
553 #address-cells = <1>;
554 #size-cells = <0>;
555 ti,hwmods = "mcspi3";
556 ti,spi-num-cs = <2>;
557 dmas = <&sdma 15>, <&sdma 16>;
558 dma-names = "tx0", "rx0";
559 status = "disabled";
560 };
561
562 mcspi4: spi@480ba000 {
563 compatible = "ti,omap4-mcspi";
564 reg = <0x480ba000 0x200>;
565 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
566 #address-cells = <1>;
567 #size-cells = <0>;
568 ti,hwmods = "mcspi4";
569 ti,spi-num-cs = <1>;
570 dmas = <&sdma 70>, <&sdma 71>;
571 dma-names = "tx0", "rx0";
572 status = "disabled";
573 };
574 };
575};
diff --git a/arch/arm/boot/dts/omap2420-h4.dts b/arch/arm/boot/dts/omap2420-h4.dts
index 224c08f472f4..34cdecb4fdda 100644
--- a/arch/arm/boot/dts/omap2420-h4.dts
+++ b/arch/arm/boot/dts/omap2420-h4.dts
@@ -50,15 +50,15 @@
50 label = "bootloader"; 50 label = "bootloader";
51 reg = <0 0x20000>; 51 reg = <0 0x20000>;
52 }; 52 };
53 partition@0x20000 { 53 partition@20000 {
54 label = "params"; 54 label = "params";
55 reg = <0x20000 0x20000>; 55 reg = <0x20000 0x20000>;
56 }; 56 };
57 partition@0x40000 { 57 partition@40000 {
58 label = "kernel"; 58 label = "kernel";
59 reg = <0x40000 0x200000>; 59 reg = <0x40000 0x200000>;
60 }; 60 };
61 partition@0x240000 { 61 partition@240000 {
62 label = "file-system"; 62 label = "file-system";
63 reg = <0x240000 0x3dc0000>; 63 reg = <0x240000 0x3dc0000>;
64 }; 64 };
diff --git a/arch/arm/boot/dts/omap3-beagle-xm.dts b/arch/arm/boot/dts/omap3-beagle-xm.dts
index 0c514dc8460c..0f7cfc503bf9 100644
--- a/arch/arm/boot/dts/omap3-beagle-xm.dts
+++ b/arch/arm/boot/dts/omap3-beagle-xm.dts
@@ -69,6 +69,23 @@
69 }; 69 };
70 70
71 }; 71 };
72
73 /* HS USB Port 2 Power */
74 hsusb2_power: hsusb2_power_reg {
75 compatible = "regulator-fixed";
76 regulator-name = "hsusb2_vbus";
77 regulator-min-microvolt = <3300000>;
78 regulator-max-microvolt = <3300000>;
79 gpio = <&twl_gpio 18 0>; /* GPIO LEDA */
80 startup-delay-us = <70000>;
81 };
82
83 /* HS USB Host PHY on PORT 2 */
84 hsusb2_phy: hsusb2_phy {
85 compatible = "usb-nop-xceiv";
86 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
87 vcc-supply = <&hsusb2_power>;
88 };
72}; 89};
73 90
74&omap3_pmx_wkup { 91&omap3_pmx_wkup {
@@ -79,6 +96,37 @@
79 }; 96 };
80}; 97};
81 98
99&omap3_pmx_core {
100 pinctrl-names = "default";
101 pinctrl-0 = <
102 &hsusbb2_pins
103 >;
104
105 uart3_pins: pinmux_uart3_pins {
106 pinctrl-single,pins = <
107 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
108 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
109 >;
110 };
111
112 hsusbb2_pins: pinmux_hsusbb2_pins {
113 pinctrl-single,pins = <
114 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
115 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
116 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
117 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
118 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
119 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
120 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
121 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
122 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
123 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
124 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
125 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
126 >;
127 };
128};
129
82&i2c1 { 130&i2c1 {
83 clock-frequency = <2600000>; 131 clock-frequency = <2600000>;
84 132
@@ -148,15 +196,6 @@
148 power = <50>; 196 power = <50>;
149}; 197};
150 198
151&omap3_pmx_core {
152 uart3_pins: pinmux_uart3_pins {
153 pinctrl-single,pins = <
154 0x16e (PIN_INPUT | PIN_OFF_WAKEUPENABLE | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */
155 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx OUTPUT | MODE0 */
156 >;
157 };
158};
159
160&uart3 { 199&uart3 {
161 pinctrl-names = "default"; 200 pinctrl-names = "default";
162 pinctrl-0 = <&uart3_pins>; 201 pinctrl-0 = <&uart3_pins>;
@@ -166,3 +205,11 @@
166 pinctrl-names = "default"; 205 pinctrl-names = "default";
167 pinctrl-0 = <&gpio1_pins>; 206 pinctrl-0 = <&gpio1_pins>;
168}; 207};
208
209&usbhshost {
210 port2-mode = "ehci-phy";
211};
212
213&usbhsehci {
214 phys = <0 &hsusb2_phy>;
215};
diff --git a/arch/arm/boot/dts/omap3-beagle.dts b/arch/arm/boot/dts/omap3-beagle.dts
index dfd83103657a..7669c16259a5 100644
--- a/arch/arm/boot/dts/omap3-beagle.dts
+++ b/arch/arm/boot/dts/omap3-beagle.dts
@@ -44,17 +44,6 @@
44 }; 44 };
45 }; 45 };
46 46
47 /* HS USB Port 2 RESET */
48 hsusb2_reset: hsusb2_reset_reg {
49 compatible = "regulator-fixed";
50 regulator-name = "hsusb2_reset";
51 regulator-min-microvolt = <3300000>;
52 regulator-max-microvolt = <3300000>;
53 gpio = <&gpio5 19 0>; /* gpio_147 */
54 startup-delay-us = <70000>;
55 enable-active-high;
56 };
57
58 /* HS USB Port 2 Power */ 47 /* HS USB Port 2 Power */
59 hsusb2_power: hsusb2_power_reg { 48 hsusb2_power: hsusb2_power_reg {
60 compatible = "regulator-fixed"; 49 compatible = "regulator-fixed";
@@ -68,7 +57,7 @@
68 /* HS USB Host PHY on PORT 2 */ 57 /* HS USB Host PHY on PORT 2 */
69 hsusb2_phy: hsusb2_phy { 58 hsusb2_phy: hsusb2_phy {
70 compatible = "usb-nop-xceiv"; 59 compatible = "usb-nop-xceiv";
71 reset-supply = <&hsusb2_reset>; 60 reset-gpios = <&gpio5 19 GPIO_ACTIVE_LOW>; /* gpio_147 */
72 vcc-supply = <&hsusb2_power>; 61 vcc-supply = <&hsusb2_power>;
73 }; 62 };
74 63
@@ -101,18 +90,18 @@
101 90
102 hsusbb2_pins: pinmux_hsusbb2_pins { 91 hsusbb2_pins: pinmux_hsusbb2_pins {
103 pinctrl-single,pins = < 92 pinctrl-single,pins = <
104 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_clk */ 93 0x5c0 (PIN_OUTPUT | MUX_MODE3) /* etk_d10.hsusb2_clk */
105 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_stp */ 94 0x5c2 (PIN_OUTPUT | MUX_MODE3) /* etk_d11.hsusb2_stp */
106 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dir */ 95 0x5c4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d12.hsusb2_dir */
107 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_nxt */ 96 0x5c6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d13.hsusb2_nxt */
108 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat0 */ 97 0x5c8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d14.hsusb2_data0 */
109 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat1 */ 98 0x5cA (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d15.hsusb2_data1 */
110 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat2 */ 99 0x1a4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi1_cs3.hsusb2_data2 */
111 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat3 */ 100 0x1a6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_clk.hsusb2_data7 */
112 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat4 */ 101 0x1a8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_simo.hsusb2_data4 */
113 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat5 */ 102 0x1aa (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_somi.hsusb2_data5 */
114 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat6 */ 103 0x1ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs0.hsusb2_data6 */
115 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* usbb2_ulpitll_clk.usbb1_ulpiphy_dat7 */ 104 0x1ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* mcspi2_cs1.hsusb2_data3 */
116 >; 105 >;
117 }; 106 };
118 107
@@ -180,3 +169,10 @@
180 pinctrl-names = "default"; 169 pinctrl-names = "default";
181 pinctrl-0 = <&gpio1_pins>; 170 pinctrl-0 = <&gpio1_pins>;
182}; 171};
172
173&usb_otg_hs {
174 interface-type = <0>;
175 usb-phy = <&usb2_phy>;
176 mode = <3>;
177 power = <50>;
178};
diff --git a/arch/arm/boot/dts/omap3-devkit8000.dts b/arch/arm/boot/dts/omap3-devkit8000.dts
index 7ef282795dd4..4665421bb7bc 100644
--- a/arch/arm/boot/dts/omap3-devkit8000.dts
+++ b/arch/arm/boot/dts/omap3-devkit8000.dts
@@ -125,7 +125,7 @@
125 nand-bus-width = <16>; 125 nand-bus-width = <16>;
126 126
127 gpmc,device-nand; 127 gpmc,device-nand;
128 gpmc,sync-clki-ps = <0>; 128 gpmc,sync-clk-ps = <0>;
129 gpmc,cs-on-ns = <0>; 129 gpmc,cs-on-ns = <0>;
130 gpmc,cs-rd-off-ns = <44>; 130 gpmc,cs-rd-off-ns = <44>;
131 gpmc,cs-wr-off-ns = <44>; 131 gpmc,cs-wr-off-ns = <44>;
diff --git a/arch/arm/boot/dts/omap3-gta04.dts b/arch/arm/boot/dts/omap3-gta04.dts
new file mode 100644
index 000000000000..a84684a95891
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-gta04.dts
@@ -0,0 +1,168 @@
1/*
2 * Copyright (C) 2013 Marek Belisko <marek@goldelico.com>
3 *
4 * Based on omap3-beagle-xm.dts
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10/dts-v1/;
11
12#include "omap36xx.dtsi"
13
14/ {
15 model = "OMAP3 GTA04";
16 compatible = "ti,omap3-gta04", "ti,omap3";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&vcc>;
21 };
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x20000000>; /* 512 MB */
27 };
28
29 gpio-keys {
30 compatible = "gpio-keys";
31
32 aux-button {
33 label = "aux";
34 linux,code = <169>;
35 gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
36 gpio-key,wakeup;
37 };
38 };
39};
40
41&omap3_pmx_core {
42 uart1_pins: pinmux_uart1_pins {
43 pinctrl-single,pins = <
44 0x152 (PIN_INPUT | MUX_MODE0) /* uart1_rx.uart1_rx */
45 0x14c (PIN_OUTPUT |MUX_MODE0) /* uart1_tx.uart1_tx */
46 >;
47 };
48
49 uart2_pins: pinmux_uart2_pins {
50 pinctrl-single,pins = <
51 0x14a (PIN_INPUT | MUX_MODE0) /* uart2_rx.uart2_rx */
52 0x148 (PIN_OUTPUT | MUX_MODE0) /* uart2_tx.uart2_tx */
53 >;
54 };
55
56 uart3_pins: pinmux_uart3_pins {
57 pinctrl-single,pins = <
58 0x16e (PIN_INPUT | MUX_MODE0) /* uart3_rx.uart3_rx */
59 0x170 (PIN_OUTPUT | MUX_MODE0) /* uart3_tx.uart3_tx */
60 >;
61 };
62
63 mmc1_pins: pinmux_mmc1_pins {
64 pinctrl-single,pins = <
65 0x114 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */
66 0x116 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */
67 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */
68 0x11a (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */
69 0x11c (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */
70 0x11e (PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */
71 >;
72 };
73};
74
75&i2c1 {
76 clock-frequency = <2600000>;
77
78 twl: twl@48 {
79 reg = <0x48>;
80 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
81 interrupt-parent = <&intc>;
82 };
83};
84
85#include "twl4030.dtsi"
86#include "twl4030_omap3.dtsi"
87
88&i2c2 {
89 clock-frequency = <400000>;
90
91 /* pressure sensor */
92 bmp085@77 {
93 compatible = "bosch,bmp085";
94 reg = <0x77>;
95 };
96
97 /* leds */
98 tca6507@45 {
99 compatible = "ti,tca6507";
100 #address-cells = <1>;
101 #size-cells = <0>;
102 reg = <0x45>;
103
104 gta04_led0: red_aux@0 {
105 label = "gta04:red:aux";
106 reg = <0x0>;
107 };
108
109 gta04_led1: green_aux@1 {
110 label = "gta04:green:aux";
111 reg = <0x1>;
112 };
113
114 gta04_led3: red_power@3 {
115 label = "gta04:red:power";
116 reg = <0x3>;
117 linux,default-trigger = "default-on";
118 };
119
120 gta04_led4: green_power@4 {
121 label = "gta04:green:power";
122 reg = <0x4>;
123 };
124 };
125};
126
127&i2c3 {
128 clock-frequency = <100000>;
129};
130
131&usb_otg_hs {
132 interface-type = <0>;
133 usb-phy = <&usb2_phy>;
134 mode = <3>;
135 power = <50>;
136};
137
138&mmc1 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&mmc1_pins>;
141 vmmc-supply = <&vmmc1>;
142 vmmc_aux-supply = <&vsim>;
143 bus-width = <4>;
144};
145
146&mmc2 {
147 status = "disabled";
148};
149
150&mmc3 {
151 status = "disabled";
152};
153
154&uart1 {
155 pinctrl-names = "default";
156 pinctrl-0 = <&uart1_pins>;
157};
158
159&uart2 {
160 pinctrl-names = "default";
161 pinctrl-0 = <&uart2_pins>;
162};
163
164&uart3 {
165 pinctrl-names = "default";
166 pinctrl-0 = <&uart3_pins>;
167};
168
diff --git a/arch/arm/boot/dts/omap3-igep.dtsi b/arch/arm/boot/dts/omap3-igep.dtsi
index 2326d11462a5..ba1e58b7b7e3 100644
--- a/arch/arm/boot/dts/omap3-igep.dtsi
+++ b/arch/arm/boot/dts/omap3-igep.dtsi
@@ -77,6 +77,8 @@
77 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ 77 0x1a2 (PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */
78 >; 78 >;
79 }; 79 };
80
81 leds_pins: pinmux_leds_pins { };
80}; 82};
81 83
82&i2c1 { 84&i2c1 {
@@ -141,3 +143,12 @@
141&twl_gpio { 143&twl_gpio {
142 ti,use-leds; 144 ti,use-leds;
143}; 145};
146
147&usb_otg_hs {
148 interface-type = <0>;
149 usb-phy = <&usb2_phy>;
150 phys = <&usb2_phy>;
151 phy-names = "usb2-phy";
152 mode = <3>;
153 power = <50>;
154};
diff --git a/arch/arm/boot/dts/omap3-igep0020.dts b/arch/arm/boot/dts/omap3-igep0020.dts
index e8c48284587c..750ce84fc195 100644
--- a/arch/arm/boot/dts/omap3-igep0020.dts
+++ b/arch/arm/boot/dts/omap3-igep0020.dts
@@ -16,7 +16,10 @@
16 compatible = "isee,omap3-igep0020", "ti,omap3"; 16 compatible = "isee,omap3-igep0020", "ti,omap3";
17 17
18 leds { 18 leds {
19 pinctrl-names = "default";
20 pinctrl-0 = <&leds_pins>;
19 compatible = "gpio-leds"; 21 compatible = "gpio-leds";
22
20 boot { 23 boot {
21 label = "omap3:green:boot"; 24 label = "omap3:green:boot";
22 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 25 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
@@ -52,6 +55,55 @@
52 regulator-name = "vdd33a"; 55 regulator-name = "vdd33a";
53 regulator-always-on; 56 regulator-always-on;
54 }; 57 };
58
59 /* HS USB Port 1 Power */
60 hsusb1_power: hsusb1_power_reg {
61 compatible = "regulator-fixed";
62 regulator-name = "hsusb1_vbus";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 gpio = <&twl_gpio 18 GPIO_ACTIVE_LOW>; /* GPIO LEDA */
66 startup-delay-us = <70000>;
67 };
68
69 /* HS USB Host PHY on PORT 1 */
70 hsusb1_phy: hsusb1_phy {
71 compatible = "usb-nop-xceiv";
72 reset-gpios = <&gpio1 24 GPIO_ACTIVE_LOW>; /* gpio_24 */
73 vcc-supply = <&hsusb1_power>;
74 };
75};
76
77&omap3_pmx_core {
78 pinctrl-names = "default";
79 pinctrl-0 = <
80 &hsusbb1_pins
81 >;
82
83 hsusbb1_pins: pinmux_hsusbb1_pins {
84 pinctrl-single,pins = <
85 0x5aa (PIN_OUTPUT | MUX_MODE3) /* etk_ctl.hsusb1_clk */
86 0x5a8 (PIN_OUTPUT | MUX_MODE3) /* etk_clk.hsusb1_stp */
87 0x5bc (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d8.hsusb1_dir */
88 0x5be (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d9.hsusb1_nxt */
89 0x5ac (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d0.hsusb1_data0 */
90 0x5ae (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d1.hsusb1_data1 */
91 0x5b0 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d2.hsusb1_data2 */
92 0x5b2 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d3.hsusb1_data7 */
93 0x5b4 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d4.hsusb1_data4 */
94 0x5b6 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d5.hsusb1_data5 */
95 0x5b8 (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d6.hsusb1_data6 */
96 0x5ba (PIN_INPUT_PULLDOWN | MUX_MODE3) /* etk_d7.hsusb1_data3 */
97 >;
98 };
99};
100
101&leds_pins {
102 pinctrl-single,pins = <
103 0x5c4 (PIN_OUTPUT | MUX_MODE4) /* etk_d12.gpio_26 */
104 0x5c6 (PIN_OUTPUT | MUX_MODE4) /* etk_d13.gpio_27 */
105 0x5c8 (PIN_OUTPUT | MUX_MODE4) /* etk_d14.gpio_28 */
106 >;
55}; 107};
56 108
57&i2c3 { 109&i2c3 {
@@ -99,19 +151,19 @@
99 label = "SPL"; 151 label = "SPL";
100 reg = <0 0x100000>; 152 reg = <0 0x100000>;
101 }; 153 };
102 partition@0x80000 { 154 partition@80000 {
103 label = "U-Boot"; 155 label = "U-Boot";
104 reg = <0x100000 0x180000>; 156 reg = <0x100000 0x180000>;
105 }; 157 };
106 partition@0x1c0000 { 158 partition@1c0000 {
107 label = "Environment"; 159 label = "Environment";
108 reg = <0x280000 0x100000>; 160 reg = <0x280000 0x100000>;
109 }; 161 };
110 partition@0x280000 { 162 partition@280000 {
111 label = "Kernel"; 163 label = "Kernel";
112 reg = <0x380000 0x300000>; 164 reg = <0x380000 0x300000>;
113 }; 165 };
114 partition@0x780000 { 166 partition@780000 {
115 label = "Filesystem"; 167 label = "Filesystem";
116 reg = <0x680000 0x1f980000>; 168 reg = <0x680000 0x1f980000>;
117 }; 169 };
@@ -147,7 +199,7 @@
147 gpmc,cycle2cycle-diffcsen; 199 gpmc,cycle2cycle-diffcsen;
148 200
149 interrupt-parent = <&gpio6>; 201 interrupt-parent = <&gpio6>;
150 interrupts = <16 8>; 202 interrupts = <16 IRQ_TYPE_LEVEL_LOW>;
151 vmmc-supply = <&vddvario>; 203 vmmc-supply = <&vddvario>;
152 vmmc_aux-supply = <&vdd33a>; 204 vmmc_aux-supply = <&vdd33a>;
153 reg-io-width = <4>; 205 reg-io-width = <4>;
@@ -155,3 +207,11 @@
155 smsc,save-mac-address; 207 smsc,save-mac-address;
156 }; 208 };
157}; 209};
210
211&usbhshost {
212 port1-mode = "ehci-phy";
213};
214
215&usbhsehci {
216 phys = <&hsusb1_phy>;
217};
diff --git a/arch/arm/boot/dts/omap3-igep0030.dts b/arch/arm/boot/dts/omap3-igep0030.dts
index 644d05383836..525e6d9b0978 100644
--- a/arch/arm/boot/dts/omap3-igep0030.dts
+++ b/arch/arm/boot/dts/omap3-igep0030.dts
@@ -16,7 +16,10 @@
16 compatible = "isee,omap3-igep0030", "ti,omap3"; 16 compatible = "isee,omap3-igep0030", "ti,omap3";
17 17
18 leds { 18 leds {
19 pinctrl-names = "default";
20 pinctrl-0 = <&leds_pins>;
19 compatible = "gpio-leds"; 21 compatible = "gpio-leds";
22
20 boot { 23 boot {
21 label = "omap3:green:boot"; 24 label = "omap3:green:boot";
22 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>; 25 gpios = <&twl_gpio 13 GPIO_ACTIVE_LOW>;
@@ -43,6 +46,12 @@
43 }; 46 };
44}; 47};
45 48
49&leds_pins {
50 pinctrl-single,pins = <
51 0x5b0 (PIN_OUTPUT | MUX_MODE4) /* etk_d2.gpio_16 */
52 >;
53};
54
46&gpmc { 55&gpmc {
47 ranges = <0 0 0x00000000 0x20000000>; 56 ranges = <0 0 0x00000000 0x20000000>;
48 57
@@ -74,19 +83,19 @@
74 label = "SPL"; 83 label = "SPL";
75 reg = <0 0x100000>; 84 reg = <0 0x100000>;
76 }; 85 };
77 partition@0x80000 { 86 partition@80000 {
78 label = "U-Boot"; 87 label = "U-Boot";
79 reg = <0x100000 0x180000>; 88 reg = <0x100000 0x180000>;
80 }; 89 };
81 partition@0x1c0000 { 90 partition@1c0000 {
82 label = "Environment"; 91 label = "Environment";
83 reg = <0x280000 0x100000>; 92 reg = <0x280000 0x100000>;
84 }; 93 };
85 partition@0x280000 { 94 partition@280000 {
86 label = "Kernel"; 95 label = "Kernel";
87 reg = <0x380000 0x300000>; 96 reg = <0x380000 0x300000>;
88 }; 97 };
89 partition@0x780000 { 98 partition@780000 {
90 label = "Filesystem"; 99 label = "Filesystem";
91 reg = <0x680000 0x1f980000>; 100 reg = <0x680000 0x1f980000>;
92 }; 101 };
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
new file mode 100644
index 000000000000..d64fa04e83f6
--- /dev/null
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -0,0 +1,92 @@
1/*
2 * Copyright (C) 2013 Pavel Machek <pavel@ucw.cz>
3 * Copyright 2013 Aaro Koskinen <aaro.koskinen@iki.fi>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 (or later) as
7 * published by the Free Software Foundation.
8 */
9
10/dts-v1/;
11
12#include "omap34xx.dtsi"
13
14/ {
15 model = "Nokia N900";
16 compatible = "nokia,omap3-n900", "ti,omap3";
17
18 cpus {
19 cpu@0 {
20 cpu0-supply = <&vcc>;
21 };
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x80000000 0x10000000>; /* 256 MB */
27 };
28
29};
30
31&i2c1 {
32 clock-frequency = <2200000>;
33
34 twl: twl@48 {
35 reg = <0x48>;
36 interrupts = <7>; /* SYS_NIRQ cascaded to intc */
37 interrupt-parent = <&intc>;
38 };
39};
40
41#include "twl4030.dtsi"
42
43&twl_gpio {
44 ti,pullups = <0x0>;
45 ti,pulldowns = <0x03ff3f>; /* BIT(0..5) | BIT(8..17) */
46};
47
48&i2c2 {
49 clock-frequency = <400000>;
50};
51
52&i2c3 {
53 clock-frequency = <100000>;
54};
55
56&mmc1 {
57 status = "disabled";
58};
59
60&mmc2 {
61 status = "disabled";
62};
63
64&mmc3 {
65 status = "disabled";
66};
67
68&mcspi1 {
69 /*
70 * For some reason, touchscreen is necessary for screen to work at
71 * all on real hw. It works well without it on emulator.
72 *
73 * Also... order in the device tree actually matters here.
74 */
75 tsc2005@0 {
76 compatible = "tsc2005";
77 spi-max-frequency = <6000000>;
78 reg = <0>;
79 };
80 mipid@2 {
81 compatible = "acx565akm";
82 spi-max-frequency = <6000000>;
83 reg = <2>;
84 };
85};
86
87&usb_otg_hs {
88 interface-type = <0>;
89 usb-phy = <&usb2_phy>;
90 mode = <2>;
91 power = <50>;
92};
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 7d95cda1fae4..16420ae16004 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -111,7 +111,7 @@
111 pinctrl-single,function-mask = <0x7f1f>; 111 pinctrl-single,function-mask = <0x7f1f>;
112 }; 112 };
113 113
114 omap3_pmx_wkup: pinmux@0x48002a00 { 114 omap3_pmx_wkup: pinmux@48002a00 {
115 compatible = "ti,omap3-padconf", "pinctrl-single"; 115 compatible = "ti,omap3-padconf", "pinctrl-single";
116 reg = <0x48002a00 0x5c>; 116 reg = <0x48002a00 0x5c>;
117 #address-cells = <1>; 117 #address-cells = <1>;
diff --git a/arch/arm/boot/dts/omap3430-sdp.dts b/arch/arm/boot/dts/omap3430-sdp.dts
index e2249bcc3e63..281914ed0151 100644
--- a/arch/arm/boot/dts/omap3430-sdp.dts
+++ b/arch/arm/boot/dts/omap3430-sdp.dts
@@ -84,15 +84,15 @@
84 label = "bootloader-nor"; 84 label = "bootloader-nor";
85 reg = <0 0x40000>; 85 reg = <0 0x40000>;
86 }; 86 };
87 partition@0x40000 { 87 partition@40000 {
88 label = "params-nor"; 88 label = "params-nor";
89 reg = <0x40000 0x40000>; 89 reg = <0x40000 0x40000>;
90 }; 90 };
91 partition@0x80000 { 91 partition@80000 {
92 label = "kernel-nor"; 92 label = "kernel-nor";
93 reg = <0x80000 0x200000>; 93 reg = <0x80000 0x200000>;
94 }; 94 };
95 partition@0x280000 { 95 partition@280000 {
96 label = "filesystem-nor"; 96 label = "filesystem-nor";
97 reg = <0x240000 0x7d80000>; 97 reg = <0x240000 0x7d80000>;
98 }; 98 };
@@ -125,19 +125,19 @@
125 label = "xloader-nand"; 125 label = "xloader-nand";
126 reg = <0 0x80000>; 126 reg = <0 0x80000>;
127 }; 127 };
128 partition@0x80000 { 128 partition@80000 {
129 label = "bootloader-nand"; 129 label = "bootloader-nand";
130 reg = <0x80000 0x140000>; 130 reg = <0x80000 0x140000>;
131 }; 131 };
132 partition@0x1c0000 { 132 partition@1c0000 {
133 label = "params-nand"; 133 label = "params-nand";
134 reg = <0x1c0000 0xc0000>; 134 reg = <0x1c0000 0xc0000>;
135 }; 135 };
136 partition@0x280000 { 136 partition@280000 {
137 label = "kernel-nand"; 137 label = "kernel-nand";
138 reg = <0x280000 0x500000>; 138 reg = <0x280000 0x500000>;
139 }; 139 };
140 partition@0x780000 { 140 partition@780000 {
141 label = "filesystem-nand"; 141 label = "filesystem-nand";
142 reg = <0x780000 0x7880000>; 142 reg = <0x780000 0x7880000>;
143 }; 143 };
@@ -170,19 +170,19 @@
170 label = "xloader-onenand"; 170 label = "xloader-onenand";
171 reg = <0 0x80000>; 171 reg = <0 0x80000>;
172 }; 172 };
173 partition@0x80000 { 173 partition@80000 {
174 label = "bootloader-onenand"; 174 label = "bootloader-onenand";
175 reg = <0x80000 0x40000>; 175 reg = <0x80000 0x40000>;
176 }; 176 };
177 partition@0xc0000 { 177 partition@c0000 {
178 label = "params-onenand"; 178 label = "params-onenand";
179 reg = <0xc0000 0x20000>; 179 reg = <0xc0000 0x20000>;
180 }; 180 };
181 partition@0xe0000 { 181 partition@e0000 {
182 label = "kernel-onenand"; 182 label = "kernel-onenand";
183 reg = <0xe0000 0x200000>; 183 reg = <0xe0000 0x200000>;
184 }; 184 };
185 partition@0x2e0000 { 185 partition@2e0000 {
186 label = "filesystem-onenand"; 186 label = "filesystem-onenand";
187 reg = <0x2e0000 0xfd20000>; 187 reg = <0x2e0000 0xfd20000>;
188 }; 188 };
diff --git a/arch/arm/boot/dts/omap4-panda-common.dtsi b/arch/arm/boot/dts/omap4-panda-common.dtsi
index 814ab67c8c29..3e6801cecd04 100644
--- a/arch/arm/boot/dts/omap4-panda-common.dtsi
+++ b/arch/arm/boot/dts/omap4-panda-common.dtsi
@@ -60,22 +60,6 @@
60 "AFMR", "Line In"; 60 "AFMR", "Line In";
61 }; 61 };
62 62
63 /*
64 * Temp hack: Need to be replaced with the proper gpio-controlled
65 * reset driver as soon it will be merged.
66 * http://thread.gmane.org/gmane.linux.drivers.devicetree/36830
67 */
68 /* HS USB Port 1 RESET */
69 hsusb1_reset: hsusb1_reset_reg {
70 compatible = "regulator-fixed";
71 regulator-name = "hsusb1_reset";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&gpio2 30 0>; /* gpio_62 */
75 startup-delay-us = <70000>;
76 enable-active-high;
77 };
78
79 /* HS USB Port 1 Power */ 63 /* HS USB Port 1 Power */
80 hsusb1_power: hsusb1_power_reg { 64 hsusb1_power: hsusb1_power_reg {
81 compatible = "regulator-fixed"; 65 compatible = "regulator-fixed";
@@ -97,7 +81,7 @@
97 /* HS USB Host PHY on PORT 1 */ 81 /* HS USB Host PHY on PORT 1 */
98 hsusb1_phy: hsusb1_phy { 82 hsusb1_phy: hsusb1_phy {
99 compatible = "usb-nop-xceiv"; 83 compatible = "usb-nop-xceiv";
100 reset-supply = <&hsusb1_reset>; 84 reset-gpios = <&gpio2 30 GPIO_ACTIVE_LOW>; /* gpio_62 */
101 vcc-supply = <&hsusb1_power>; 85 vcc-supply = <&hsusb1_power>;
102 /** 86 /**
103 * FIXME: 87 * FIXME:
@@ -122,23 +106,9 @@
122 }; 106 };
123}; 107};
124 108
125&omap4_pmx_wkup {
126 pinctrl-names = "default";
127 pinctrl-0 = <
128 &twl6030_wkup_pins
129 >;
130
131 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
132 pinctrl-single,pins = <
133 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
134 >;
135 };
136};
137
138&omap4_pmx_core { 109&omap4_pmx_core {
139 pinctrl-names = "default"; 110 pinctrl-names = "default";
140 pinctrl-0 = < 111 pinctrl-0 = <
141 &twl6030_pins
142 &twl6040_pins 112 &twl6040_pins
143 &mcpdm_pins 113 &mcpdm_pins
144 &mcbsp1_pins 114 &mcbsp1_pins
@@ -147,12 +117,6 @@
147 &hsusbb1_pins 117 &hsusbb1_pins
148 >; 118 >;
149 119
150 twl6030_pins: pinmux_twl6030_pins {
151 pinctrl-single,pins = <
152 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
153 >;
154 };
155
156 twl6040_pins: pinmux_twl6040_pins { 120 twl6040_pins: pinmux_twl6040_pins {
157 pinctrl-single,pins = < 121 pinctrl-single,pins = <
158 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ 122 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
@@ -305,6 +269,7 @@
305}; 269};
306 270
307#include "twl6030.dtsi" 271#include "twl6030.dtsi"
272#include "twl6030_omap4.dtsi"
308 273
309&i2c2 { 274&i2c2 {
310 pinctrl-names = "default"; 275 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4-sdp.dts b/arch/arm/boot/dts/omap4-sdp.dts
index 4f78380ecdb8..5fc3f43c5a81 100644
--- a/arch/arm/boot/dts/omap4-sdp.dts
+++ b/arch/arm/boot/dts/omap4-sdp.dts
@@ -155,23 +155,9 @@
155 }; 155 };
156}; 156};
157 157
158&omap4_pmx_wkup {
159 pinctrl-names = "default";
160 pinctrl-0 = <
161 &twl6030_wkup_pins
162 >;
163
164 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
165 pinctrl-single,pins = <
166 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
167 >;
168 };
169};
170
171&omap4_pmx_core { 158&omap4_pmx_core {
172 pinctrl-names = "default"; 159 pinctrl-names = "default";
173 pinctrl-0 = < 160 pinctrl-0 = <
174 &twl6030_pins
175 &twl6040_pins 161 &twl6040_pins
176 &mcpdm_pins 162 &mcpdm_pins
177 &dmic_pins 163 &dmic_pins
@@ -206,12 +192,6 @@
206 >; 192 >;
207 }; 193 };
208 194
209 twl6030_pins: pinmux_twl6030_pins {
210 pinctrl-single,pins = <
211 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
212 >;
213 };
214
215 twl6040_pins: pinmux_twl6040_pins { 195 twl6040_pins: pinmux_twl6040_pins {
216 pinctrl-single,pins = < 196 pinctrl-single,pins = <
217 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */ 197 0xe0 (PIN_OUTPUT | MUX_MODE3) /* hdq_sio.gpio_127 */
@@ -370,6 +350,7 @@
370}; 350};
371 351
372#include "twl6030.dtsi" 352#include "twl6030.dtsi"
353#include "twl6030_omap4.dtsi"
373 354
374&i2c2 { 355&i2c2 {
375 pinctrl-names = "default"; 356 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 22d9f2b593d4..6be1f5678f1a 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -56,7 +56,7 @@
56 cache-level = <2>; 56 cache-level = <2>;
57 }; 57 };
58 58
59 local-timer@0x48240600 { 59 local-timer@48240600 {
60 compatible = "arm,cortex-a9-twd-timer"; 60 compatible = "arm,cortex-a9-twd-timer";
61 reg = <0x48240600 0x20>; 61 reg = <0x48240600 0x20>;
62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 62 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>;
@@ -663,5 +663,23 @@
663 ram-bits = <12>; 663 ram-bits = <12>;
664 ti,has-mailbox; 664 ti,has-mailbox;
665 }; 665 };
666
667 aes: aes@4b501000 {
668 compatible = "ti,omap4-aes";
669 ti,hwmods = "aes";
670 reg = <0x4b501000 0xa0>;
671 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
672 dmas = <&sdma 111>, <&sdma 110>;
673 dma-names = "tx", "rx";
674 };
675
676 des: des@480a5000 {
677 compatible = "ti,omap4-des";
678 ti,hwmods = "des";
679 reg = <0x480a5000 0xa0>;
680 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
681 dmas = <&sdma 117>, <&sdma 116>;
682 dma-names = "tx", "rx";
683 };
666 }; 684 };
667}; 685};
diff --git a/arch/arm/boot/dts/omap5-uevm.dts b/arch/arm/boot/dts/omap5-uevm.dts
index 65d7b601651c..d784b3a00410 100644
--- a/arch/arm/boot/dts/omap5-uevm.dts
+++ b/arch/arm/boot/dts/omap5-uevm.dts
@@ -27,21 +27,10 @@
27 regulator-max-microvolt = <3000000>; 27 regulator-max-microvolt = <3000000>;
28 }; 28 };
29 29
30 /* HS USB Port 2 RESET */
31 hsusb2_reset: hsusb2_reset_reg {
32 compatible = "regulator-fixed";
33 regulator-name = "hsusb2_reset";
34 regulator-min-microvolt = <3300000>;
35 regulator-max-microvolt = <3300000>;
36 gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; /* gpio3_80 HUB_NRESET */
37 startup-delay-us = <70000>;
38 enable-active-high;
39 };
40
41 /* HS USB Host PHY on PORT 2 */ 30 /* HS USB Host PHY on PORT 2 */
42 hsusb2_phy: hsusb2_phy { 31 hsusb2_phy: hsusb2_phy {
43 compatible = "usb-nop-xceiv"; 32 compatible = "usb-nop-xceiv";
44 reset-supply = <&hsusb2_reset>; 33 reset-gpios = <&gpio3 16 GPIO_ACTIVE_LOW>; /* gpio3_80 HUB_NRESET */
45 /** 34 /**
46 * FIXME 35 * FIXME
47 * Put the right clock phandle here when available 36 * Put the right clock phandle here when available
@@ -51,21 +40,10 @@
51 clock-frequency = <19200000>; 40 clock-frequency = <19200000>;
52 }; 41 };
53 42
54 /* HS USB Port 3 RESET */
55 hsusb3_reset: hsusb3_reset_reg {
56 compatible = "regulator-fixed";
57 regulator-name = "hsusb3_reset";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 gpio = <&gpio3 15 GPIO_ACTIVE_HIGH>; /* gpio3_79 ETH_NRESET */
61 startup-delay-us = <70000>;
62 enable-active-high;
63 };
64
65 /* HS USB Host PHY on PORT 3 */ 43 /* HS USB Host PHY on PORT 3 */
66 hsusb3_phy: hsusb3_phy { 44 hsusb3_phy: hsusb3_phy {
67 compatible = "usb-nop-xceiv"; 45 compatible = "usb-nop-xceiv";
68 reset-supply = <&hsusb3_reset>; 46 reset-gpios = <&gpio3 15 GPIO_ACTIVE_LOW>; /* gpio3_79 ETH_NRESET */
69 }; 47 };
70 48
71 leds { 49 leds {
@@ -271,6 +249,14 @@
271 reg = <0x48>; 249 reg = <0x48>;
272 interrupt-controller; 250 interrupt-controller;
273 #interrupt-cells = <2>; 251 #interrupt-cells = <2>;
252 ti,system-power-controller;
253
254 extcon_usb3: palmas_usb {
255 compatible = "ti,palmas-usb-vid";
256 ti,enable-vbus-detection;
257 ti,enable-id-detection;
258 ti,wakeup;
259 };
274 260
275 palmas_pmic { 261 palmas_pmic {
276 compatible = "ti,palmas-pmic"; 262 compatible = "ti,palmas-pmic";
@@ -334,9 +320,18 @@
334 ti,smps-range = <0x80>; 320 ti,smps-range = <0x80>;
335 }; 321 };
336 322
337 smps10_reg: smps10 { 323 smps10_out2_reg: smps10_out2 {
338 /* VBUS_5V_OTG */ 324 /* VBUS_5V_OTG */
339 regulator-name = "smps10"; 325 regulator-name = "smps10_out2";
326 regulator-min-microvolt = <5000000>;
327 regulator-max-microvolt = <5000000>;
328 regulator-always-on;
329 regulator-boot-on;
330 };
331
332 smps10_out1_reg: smps10_out1 {
333 /* VBUS_5V_OTG */
334 regulator-name = "smps10_out1";
340 regulator-min-microvolt = <5000000>; 335 regulator-min-microvolt = <5000000>;
341 regulator-max-microvolt = <5000000>; 336 regulator-max-microvolt = <5000000>;
342 regulator-always-on; 337 regulator-always-on;
@@ -470,6 +465,11 @@
470 phys = <0 &hsusb2_phy &hsusb3_phy>; 465 phys = <0 &hsusb2_phy &hsusb3_phy>;
471}; 466};
472 467
468&usb3 {
469 extcon = <&extcon_usb3>;
470 vbus-supply = <&smps10_out1_reg>;
471};
472
473&mcspi1 { 473&mcspi1 {
474 474
475}; 475};
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 7cdea1bfea09..6192c458bea1 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -604,7 +604,7 @@
604 ti,hwmods = "wd_timer2"; 604 ti,hwmods = "wd_timer2";
605 }; 605 };
606 606
607 emif1: emif@0x4c000000 { 607 emif1: emif@4c000000 {
608 compatible = "ti,emif-4d5"; 608 compatible = "ti,emif-4d5";
609 ti,hwmods = "emif1"; 609 ti,hwmods = "emif1";
610 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 610 phy-type = <2>; /* DDR PHY type: Intelli PHY */
@@ -615,7 +615,7 @@
615 hw-caps-temp-alert; 615 hw-caps-temp-alert;
616 }; 616 };
617 617
618 emif2: emif@0x4d000000 { 618 emif2: emif@4d000000 {
619 compatible = "ti,emif-4d5"; 619 compatible = "ti,emif-4d5";
620 ti,hwmods = "emif2"; 620 ti,hwmods = "emif2";
621 phy-type = <2>; /* DDR PHY type: Intelli PHY */ 621 phy-type = <2>; /* DDR PHY type: Intelli PHY */
@@ -634,7 +634,7 @@
634 ti,type = <2>; 634 ti,type = <2>;
635 }; 635 };
636 636
637 omap_dwc3@4a020000 { 637 usb3: omap_dwc3@4a020000 {
638 compatible = "ti,dwc3"; 638 compatible = "ti,dwc3";
639 ti,hwmods = "usb_otg_ss"; 639 ti,hwmods = "usb_otg_ss";
640 reg = <0x4a020000 0x10000>; 640 reg = <0x4a020000 0x10000>;
diff --git a/arch/arm/boot/dts/twl6030_omap4.dtsi b/arch/arm/boot/dts/twl6030_omap4.dtsi
new file mode 100644
index 000000000000..a4fa5703c42b
--- /dev/null
+++ b/arch/arm/boot/dts/twl6030_omap4.dtsi
@@ -0,0 +1,38 @@
1/*
2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9&twl {
10 /*
11 * On most OMAP4 platforms, the twl6030 IRQ line is connected
12 * to the SYS_NIRQ1 line on OMAP and the twl6030 MSECURE line is
13 * connected to the fref_clk0_out.sys_drm_msecure line.
14 * Therefore, configure the defaults for the SYS_NIRQ1 and
15 * fref_clk0_out.sys_drm_msecure pins here.
16 */
17 pinctrl-names = "default";
18 pinctrl-0 = <
19 &twl6030_pins
20 &twl6030_wkup_pins
21 >;
22};
23
24&omap4_pmx_wkup {
25 twl6030_wkup_pins: pinmux_twl6030_wkup_pins {
26 pinctrl-single,pins = <
27 0x14 (PIN_OUTPUT | MUX_MODE2) /* fref_clk0_out.sys_drm_msecure */
28 >;
29 };
30};
31
32&omap4_pmx_core {
33 twl6030_pins: pinmux_twl6030_pins {
34 pinctrl-single,pins = <
35 0x15e (WAKEUP_EN | PIN_INPUT_PULLUP | MUX_MODE0) /* sys_nirq1.sys_nirq1 */
36 >;
37 };
38};
diff --git a/include/dt-bindings/pinctrl/dra.h b/include/dt-bindings/pinctrl/dra.h
new file mode 100644
index 000000000000..002a2855c046
--- /dev/null
+++ b/include/dt-bindings/pinctrl/dra.h
@@ -0,0 +1,50 @@
1/*
2 * This header provides constants for DRA pinctrl bindings.
3 *
4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
5 * Author: Rajendra Nayak <rnayak@ti.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#ifndef _DT_BINDINGS_PINCTRL_DRA_H
13#define _DT_BINDINGS_PINCTRL_DRA_H
14
15/* DRA7 mux mode options for each pin. See TRM for options */
16#define MUX_MODE0 0x0
17#define MUX_MODE1 0x1
18#define MUX_MODE2 0x2
19#define MUX_MODE3 0x3
20#define MUX_MODE4 0x4
21#define MUX_MODE5 0x5
22#define MUX_MODE6 0x6
23#define MUX_MODE7 0x7
24#define MUX_MODE8 0x8
25#define MUX_MODE9 0x9
26#define MUX_MODE10 0xa
27#define MUX_MODE11 0xb
28#define MUX_MODE12 0xc
29#define MUX_MODE13 0xd
30#define MUX_MODE14 0xe
31#define MUX_MODE15 0xf
32
33#define PULL_ENA (1 << 16)
34#define PULL_UP (1 << 17)
35#define INPUT_EN (1 << 18)
36#define SLEWCONTROL (1 << 19)
37#define WAKEUP_EN (1 << 24)
38#define WAKEUP_EVENT (1 << 25)
39
40/* Active pin states */
41#define PIN_OUTPUT 0
42#define PIN_OUTPUT_PULLUP (PIN_OUTPUT | PULL_ENA | PULL_UP)
43#define PIN_OUTPUT_PULLDOWN (PIN_OUTPUT | PULL_ENA)
44#define PIN_INPUT INPUT_EN
45#define PIN_INPUT_SLEW (INPUT_EN | SLEWCONTROL)
46#define PIN_INPUT_PULLUP (PULL_ENA | INPUT_EN | PULL_UP)
47#define PIN_INPUT_PULLDOWN (PULL_ENA | INPUT_EN)
48
49#endif
50
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-17 14:36:57 -0400