diff options
author | Jack Morgenstein <jackm@mellanox.co.il> | 2005-12-15 22:59:01 -0500 |
---|---|---|
committer | Roland Dreier <rolandd@cisco.com> | 2005-12-15 22:59:01 -0500 |
commit | c4342d8a4d95e18b957b898dbf5bfce28fca2780 (patch) | |
tree | fbaaaa50351a71f03b013b86ba32ef01bea19472 | |
parent | d1646f86a2a05a956adbb163c81a81bd621f055e (diff) |
IB/mthca: Fix corner cases in max_rd_atomic value handling in modify QP
sae and sre bits should only be set when setting sra_max. Further, in
the old code, if the caller specifies max_rd_atomic = 0, the sre and
sae bits are still set, with the result that the QP ends up with
max_rd_atomic = 1 in effect.
Signed-off-by: Jack Morgenstein <jackm@mellanox.co.il>
Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il>
Signed-off-by: Roland Dreier <rolandd@cisco.com>
-rw-r--r-- | drivers/infiniband/hw/mthca/mthca_qp.c | 10 |
1 files changed, 6 insertions, 4 deletions
diff --git a/drivers/infiniband/hw/mthca/mthca_qp.c b/drivers/infiniband/hw/mthca/mthca_qp.c index e826c9ff5d70..d786ef443614 100644 --- a/drivers/infiniband/hw/mthca/mthca_qp.c +++ b/drivers/infiniband/hw/mthca/mthca_qp.c | |||
@@ -747,9 +747,7 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |||
747 | qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey); | 747 | qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey); |
748 | qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) | | 748 | qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) | |
749 | (MTHCA_FLIGHT_LIMIT << 24) | | 749 | (MTHCA_FLIGHT_LIMIT << 24) | |
750 | MTHCA_QP_BIT_SRE | | 750 | MTHCA_QP_BIT_SWE); |
751 | MTHCA_QP_BIT_SWE | | ||
752 | MTHCA_QP_BIT_SAE); | ||
753 | if (qp->sq_policy == IB_SIGNAL_ALL_WR) | 751 | if (qp->sq_policy == IB_SIGNAL_ALL_WR) |
754 | qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC); | 752 | qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC); |
755 | if (attr_mask & IB_QP_RETRY_CNT) { | 753 | if (attr_mask & IB_QP_RETRY_CNT) { |
@@ -758,9 +756,13 @@ int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask) | |||
758 | } | 756 | } |
759 | 757 | ||
760 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { | 758 | if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { |
761 | if (attr->max_rd_atomic) | 759 | if (attr->max_rd_atomic) { |
760 | qp_context->params1 |= | ||
761 | cpu_to_be32(MTHCA_QP_BIT_SRE | | ||
762 | MTHCA_QP_BIT_SAE); | ||
762 | qp_context->params1 |= | 763 | qp_context->params1 |= |
763 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); | 764 | cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21); |
765 | } | ||
764 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX); | 766 | qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX); |
765 | } | 767 | } |
766 | 768 | ||