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authorArnd Bergmann <arnd@arndb.de>2013-06-21 05:46:56 -0400
committerArnd Bergmann <arnd@arndb.de>2013-06-21 05:46:56 -0400
commitc20e459fcc7d5d86a359b19f54362fb6fb77c6aa (patch)
tree67874c7e922932af6f25793775d0ca781b2697c2
parente43995ad58264f5113a27d4c6c75edadcf126840 (diff)
parentd63dc0514d56e108cc96e334ca26b538263e52a2 (diff)
Merge tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/soc
From Heiko Stuebner: Adds basic support for Rockchip Cortex-A9 SoCs. * tag 'v3.11-rockchip-basics' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: arm: add basic support for Rockchip RK3066a boards arm: add debug uarts for rockchip rk29xx and rk3xxx series arm: Add basic clocks for Rockchip rk3066a SoCs clocksource: dw_apb_timer_of: use clocksource_of_init clocksource: dw_apb_timer_of: select DW_APB_TIMER clocksource: dw_apb_timer_of: add clock-handling clocksource: dw_apb_timer_of: enable the use the clocksource as sched clock Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--Documentation/devicetree/bindings/rtc/dw-apb.txt19
-rw-r--r--arch/arm/Kconfig2
-rw-r--r--arch/arm/Kconfig.debug34
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/boot/dts/rk3066a-clocks.dtsi299
-rw-r--r--arch/arm/boot/dts/rk3066a.dtsi390
-rw-r--r--arch/arm/include/debug/rockchip.S42
-rw-r--r--arch/arm/mach-picoxcell/Kconfig1
-rw-r--r--arch/arm/mach-picoxcell/common.c2
-rw-r--r--arch/arm/mach-rockchip/Kconfig16
-rw-r--r--arch/arm/mach-rockchip/Makefile1
-rw-r--r--arch/arm/mach-rockchip/rockchip.c52
-rw-r--r--arch/arm/mach-socfpga/Kconfig1
-rw-r--r--arch/arm/mach-socfpga/socfpga.c2
-rw-r--r--drivers/clocksource/Kconfig2
-rw-r--r--drivers/clocksource/dw_apb_timer_of.c95
-rw-r--r--include/linux/dw_apb_timer.h1
17 files changed, 921 insertions, 39 deletions
diff --git a/Documentation/devicetree/bindings/rtc/dw-apb.txt b/Documentation/devicetree/bindings/rtc/dw-apb.txt
index 93e2b0f048e6..eb2327b2bdb3 100644
--- a/Documentation/devicetree/bindings/rtc/dw-apb.txt
+++ b/Documentation/devicetree/bindings/rtc/dw-apb.txt
@@ -5,9 +5,20 @@ Required properties:
5- reg: physical base address of the controller and length of memory mapped 5- reg: physical base address of the controller and length of memory mapped
6 region. 6 region.
7- interrupts: IRQ line for the timer. 7- interrupts: IRQ line for the timer.
8- either clocks+clock-names or clock-frequency properties
9
10Optional properties:
11- clocks : list of clock specifiers, corresponding to entries in
12 the clock-names property;
13- clock-names : should contain "timer" and "pclk" entries, matching entries
14 in the clocks property.
8- clock-frequency: The frequency in HZ of the timer. 15- clock-frequency: The frequency in HZ of the timer.
9- clock-freq: For backwards compatibility with picoxcell 16- clock-freq: For backwards compatibility with picoxcell
10 17
18If using the clock specifiers, the pclk clock is optional, as not all
19systems may use one.
20
21
11Example: 22Example:
12 23
13 timer1: timer@ffc09000 { 24 timer1: timer@ffc09000 {
@@ -23,3 +34,11 @@ Example:
23 clock-frequency = <200000000>; 34 clock-frequency = <200000000>;
24 reg = <0xffd00000 0x1000>; 35 reg = <0xffd00000 0x1000>;
25 }; 36 };
37
38 timer3: timer@ffe00000 {
39 compatible = "snps,dw-apb-timer-osc";
40 interrupts = <0 170 4>;
41 reg = <0xffe00000 0x1000>;
42 clocks = <&timer_clk>, <&timer_pclk>;
43 clock-names = "timer", "pclk";
44 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 4fd8ed7021ce..ccd78c912cbf 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -982,6 +982,8 @@ source "arch/arm/mach-mmp/Kconfig"
982 982
983source "arch/arm/mach-realview/Kconfig" 983source "arch/arm/mach-realview/Kconfig"
984 984
985source "arch/arm/mach-rockchip/Kconfig"
986
985source "arch/arm/mach-sa1100/Kconfig" 987source "arch/arm/mach-sa1100/Kconfig"
986 988
987source "arch/arm/plat-samsung/Kconfig" 989source "arch/arm/plat-samsung/Kconfig"
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 394d2a4064e1..ab95f07e1541 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -399,6 +399,13 @@ choice
399 their output to the standard serial port on the RealView 399 their output to the standard serial port on the RealView
400 PB1176 platform. 400 PB1176 platform.
401 401
402 config DEBUG_ROCKCHIP_UART
403 bool "Kernel low-level debugging messages via Rockchip UART"
404 depends on ARCH_ROCKCHIP
405 help
406 Say Y here if you want kernel low-level debugging support
407 on Rockchip based platforms.
408
402 config DEBUG_S3C_UART0 409 config DEBUG_S3C_UART0
403 depends on PLAT_SAMSUNG 410 depends on PLAT_SAMSUNG
404 select DEBUG_EXYNOS_UART if ARCH_EXYNOS 411 select DEBUG_EXYNOS_UART if ARCH_EXYNOS
@@ -643,6 +650,32 @@ endchoice
643 650
644choice 651choice
645 prompt "Low-level debug console UART" 652 prompt "Low-level debug console UART"
653 depends on DEBUG_ROCKCHIP_UART
654
655 config DEBUG_RK29_UART0
656 bool "RK29 UART0"
657
658 config DEBUG_RK29_UART1
659 bool "RK29 UART1"
660
661 config DEBUG_RK29_UART2
662 bool "RK29 UART2"
663
664 config DEBUG_RK3X_UART0
665 bool "RK3X UART0"
666
667 config DEBUG_RK3X_UART1
668 bool "RK3X UART1"
669
670 config DEBUG_RK3X_UART2
671 bool "RK3X UART2"
672
673 config DEBUG_RK3X_UART3
674 bool "RK3X UART3"
675endchoice
676
677choice
678 prompt "Low-level debug console UART"
646 depends on DEBUG_LL && DEBUG_TEGRA_UART 679 depends on DEBUG_LL && DEBUG_TEGRA_UART
647 680
648 config TEGRA_DEBUG_UART_AUTO_ODMDATA 681 config TEGRA_DEBUG_UART_AUTO_ODMDATA
@@ -697,6 +730,7 @@ config DEBUG_LL_INCLUDE
697 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART 730 default "debug/picoxcell.S" if DEBUG_PICOXCELL_UART
698 default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \ 731 default "debug/pxa.S" if DEBUG_PXA_UART1 || DEBUG_MMP_UART2 || \
699 DEBUG_MMP_UART3 732 DEBUG_MMP_UART3
733 default "debug/rockchip.S" if DEBUG_ROCKCHIP_UART
700 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1 734 default "debug/sirf.S" if DEBUG_SIRFPRIMA2_UART1 || DEBUG_SIRFMARCO_UART1
701 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART 735 default "debug/socfpga.S" if DEBUG_SOCFPGA_UART
702 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1 736 default "debug/sunxi.S" if DEBUG_SUNXI_UART0 || DEBUG_SUNXI_UART1
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 5a1c48ac5bc5..daf19a86b8eb 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -172,6 +172,7 @@ machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
172machine-$(CONFIG_ARCH_PRIMA2) += prima2 172machine-$(CONFIG_ARCH_PRIMA2) += prima2
173machine-$(CONFIG_ARCH_PXA) += pxa 173machine-$(CONFIG_ARCH_PXA) += pxa
174machine-$(CONFIG_ARCH_REALVIEW) += realview 174machine-$(CONFIG_ARCH_REALVIEW) += realview
175machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
175machine-$(CONFIG_ARCH_RPC) += rpc 176machine-$(CONFIG_ARCH_RPC) += rpc
176machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx 177machine-$(CONFIG_ARCH_S3C24XX) += s3c24xx
177machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx 178machine-$(CONFIG_ARCH_S3C64XX) += s3c64xx
diff --git a/arch/arm/boot/dts/rk3066a-clocks.dtsi b/arch/arm/boot/dts/rk3066a-clocks.dtsi
new file mode 100644
index 000000000000..6e307fc4c451
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a-clocks.dtsi
@@ -0,0 +1,299 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16/ {
17 clocks {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 ranges;
21
22 /*
23 * This is a dummy clock, to be used as placeholder on
24 * other mux clocks when a specific parent clock is not
25 * yet implemented. It should be dropped when the driver
26 * is complete.
27 */
28 dummy: dummy {
29 compatible = "fixed-clock";
30 clock-frequency = <0>;
31 #clock-cells = <0>;
32 };
33
34 xin24m: xin24m {
35 compatible = "fixed-clock";
36 clock-frequency = <24000000>;
37 #clock-cells = <0>;
38 };
39
40 dummy48m: dummy48m {
41 compatible = "fixed-clock";
42 clock-frequency = <48000000>;
43 #clock-cells = <0>;
44 };
45
46 dummy150m: dummy150m {
47 compatible = "fixed-clock";
48 clock-frequency = <150000000>;
49 #clock-cells = <0>;
50 };
51
52 clk_gates0: gate-clk@200000d0 {
53 compatible = "rockchip,rk2928-gate-clk";
54 reg = <0x200000d0 0x4>;
55 clocks = <&dummy>, <&dummy>,
56 <&dummy>, <&dummy>,
57 <&dummy>, <&dummy>,
58 <&dummy>, <&dummy>,
59 <&dummy>, <&dummy>,
60 <&dummy>, <&dummy>,
61 <&dummy>, <&dummy>,
62 <&dummy>, <&dummy>;
63
64 clock-output-names =
65 "gate_core_periph", "gate_cpu_gpll",
66 "gate_ddrphy", "gate_aclk_cpu",
67 "gate_hclk_cpu", "gate_pclk_cpu",
68 "gate_atclk_cpu", "gate_i2s0",
69 "gate_i2s0_frac", "gate_i2s1",
70 "gate_i2s1_frac", "gate_i2s2",
71 "gate_i2s2_frac", "gate_spdif",
72 "gate_spdif_frac", "gate_testclk";
73
74 #clock-cells = <1>;
75 };
76
77 clk_gates1: gate-clk@200000d4 {
78 compatible = "rockchip,rk2928-gate-clk";
79 reg = <0x200000d4 0x4>;
80 clocks = <&xin24m>, <&xin24m>,
81 <&xin24m>, <&dummy>,
82 <&dummy>, <&xin24m>,
83 <&xin24m>, <&dummy>,
84 <&xin24m>, <&dummy>,
85 <&xin24m>, <&dummy>,
86 <&xin24m>, <&dummy>,
87 <&xin24m>, <&dummy>;
88
89 clock-output-names =
90 "gate_timer0", "gate_timer1",
91 "gate_timer2", "gate_jtag",
92 "gate_aclk_lcdc1_src", "gate_otgphy0",
93 "gate_otgphy1", "gate_ddr_gpll",
94 "gate_uart0", "gate_frac_uart0",
95 "gate_uart1", "gate_frac_uart1",
96 "gate_uart2", "gate_frac_uart2",
97 "gate_uart3", "gate_frac_uart3";
98
99 #clock-cells = <1>;
100 };
101
102 clk_gates2: gate-clk@200000d8 {
103 compatible = "rockchip,rk2928-gate-clk";
104 reg = <0x200000d8 0x4>;
105 clocks = <&clk_gates2 1>, <&dummy>,
106 <&dummy>, <&dummy>,
107 <&dummy>, <&dummy>,
108 <&clk_gates2 3>, <&dummy>,
109 <&dummy>, <&dummy>,
110 <&dummy>, <&dummy48m>,
111 <&dummy>, <&dummy48m>,
112 <&dummy>, <&dummy>;
113
114 clock-output-names =
115 "gate_periph_src", "gate_aclk_periph",
116 "gate_hclk_periph", "gate_pclk_periph",
117 "gate_smc", "gate_mac",
118 "gate_hsadc", "gate_hsadc_frac",
119 "gate_saradc", "gate_spi0",
120 "gate_spi1", "gate_mmc0",
121 "gate_mac_lbtest", "gate_mmc1",
122 "gate_emmc", "gate_tsadc";
123
124 #clock-cells = <1>;
125 };
126
127 clk_gates3: gate-clk@200000dc {
128 compatible = "rockchip,rk2928-gate-clk";
129 reg = <0x200000dc 0x4>;
130 clocks = <&dummy>, <&dummy>,
131 <&dummy>, <&dummy>,
132 <&dummy>, <&dummy>,
133 <&dummy>, <&dummy>,
134 <&dummy>, <&dummy>,
135 <&dummy>, <&dummy>,
136 <&dummy>, <&dummy>,
137 <&dummy>, <&dummy>;
138
139 clock-output-names =
140 "gate_aclk_lcdc0_src", "gate_dclk_lcdc0",
141 "gate_dclk_lcdc1", "gate_pclkin_cif0",
142 "gate_pclkin_cif1", "reserved",
143 "reserved", "gate_cif0_out",
144 "gate_cif1_out", "gate_aclk_vepu",
145 "gate_hclk_vepu", "gate_aclk_vdpu",
146 "gate_hclk_vdpu", "gate_gpu_src",
147 "reserved", "gate_xin27m";
148
149 #clock-cells = <1>;
150 };
151
152 clk_gates4: gate-clk@200000e0 {
153 compatible = "rockchip,rk2928-gate-clk";
154 reg = <0x200000e0 0x4>;
155 clocks = <&clk_gates2 2>, <&clk_gates2 3>,
156 <&clk_gates2 1>, <&clk_gates2 1>,
157 <&clk_gates2 1>, <&clk_gates2 2>,
158 <&clk_gates2 2>, <&clk_gates2 2>,
159 <&clk_gates0 4>, <&clk_gates0 4>,
160 <&clk_gates0 3>, <&clk_gates0 3>,
161 <&clk_gates0 3>, <&clk_gates2 3>,
162 <&clk_gates0 4>;
163
164 clock-output-names =
165 "gate_hclk_peri_axi_matrix", "gate_pclk_peri_axi_matrix",
166 "gate_aclk_cpu_peri", "gate_aclk_peri_axi_matrix",
167 "gate_aclk_pei_niu", "gate_hclk_usb_peri",
168 "gate_hclk_peri_ahb_arbi", "gate_hclk_emem_peri",
169 "gate_hclk_cpubus", "gate_hclk_ahb2apb",
170 "gate_aclk_strc_sys", "gate_aclk_l2mem_con",
171 "gate_aclk_intmem", "gate_pclk_tsadc",
172 "gate_hclk_hdmi";
173
174 #clock-cells = <1>;
175 };
176
177 clk_gates5: gate-clk@200000e4 {
178 compatible = "rockchip,rk2928-gate-clk";
179 reg = <0x200000e4 0x4>;
180 clocks = <&clk_gates0 3>, <&clk_gates2 1>,
181 <&clk_gates0 5>, <&clk_gates0 5>,
182 <&clk_gates0 5>, <&clk_gates0 5>,
183 <&clk_gates0 4>, <&clk_gates0 5>,
184 <&clk_gates2 1>, <&clk_gates2 2>,
185 <&clk_gates2 2>, <&clk_gates2 2>,
186 <&clk_gates2 2>, <&clk_gates4 5>,
187 <&clk_gates4 5>, <&dummy>;
188
189 clock-output-names =
190 "gate_aclk_dmac1", "gate_aclk_dmac2",
191 "gate_pclk_efuse", "gate_pclk_tzpc",
192 "gate_pclk_grf", "gate_pclk_pmu",
193 "gate_hclk_rom", "gate_pclk_ddrupctl",
194 "gate_aclk_smc", "gate_hclk_nandc",
195 "gate_hclk_mmc0", "gate_hclk_mmc1",
196 "gate_hclk_emmc", "gate_hclk_otg0",
197 "gate_hclk_otg1", "gate_aclk_gpu";
198
199 #clock-cells = <1>;
200 };
201
202 clk_gates6: gate-clk@200000e8 {
203 compatible = "rockchip,rk2928-gate-clk";
204 reg = <0x200000e8 0x4>;
205 clocks = <&clk_gates3 0>, <&clk_gates0 4>,
206 <&clk_gates0 4>, <&clk_gates1 4>,
207 <&clk_gates0 4>, <&clk_gates3 0>,
208 <&clk_gates0 4>, <&clk_gates1 4>,
209 <&clk_gates3 0>, <&clk_gates0 4>,
210 <&clk_gates0 4>, <&clk_gates1 4>,
211 <&clk_gates0 4>, <&clk_gates3 0>,
212 <&dummy>, <&dummy>;
213
214 clock-output-names =
215 "gate_aclk_lcdc0", "gate_hclk_lcdc0",
216 "gate_hclk_lcdc1", "gate_aclk_lcdc1",
217 "gate_hclk_cif0", "gate_aclk_cif0",
218 "gate_hclk_cif1", "gate_aclk_cif1",
219 "gate_aclk_ipp", "gate_hclk_ipp",
220 "gate_hclk_rga", "gate_aclk_rga",
221 "gate_hclk_vio_bus", "gate_aclk_vio0",
222 "gate_aclk_vcodec", "gate_shclk_vio_h2h";
223
224 #clock-cells = <1>;
225 };
226
227 clk_gates7: gate-clk@200000ec {
228 compatible = "rockchip,rk2928-gate-clk";
229 reg = <0x200000ec 0x4>;
230 clocks = <&clk_gates2 2>, <&clk_gates0 4>,
231 <&clk_gates0 4>, <&clk_gates0 4>,
232 <&clk_gates0 4>, <&clk_gates2 2>,
233 <&clk_gates2 2>, <&clk_gates0 5>,
234 <&clk_gates0 5>, <&clk_gates0 5>,
235 <&clk_gates0 5>, <&clk_gates2 3>,
236 <&clk_gates2 3>, <&clk_gates2 3>,
237 <&clk_gates2 3>, <&clk_gates2 3>;
238
239 clock-output-names =
240 "gate_hclk_emac", "gate_hclk_spdif",
241 "gate_hclk_i2s0_2ch", "gate_hclk_i2s1_2ch",
242 "gate_hclk_i2s_8ch", "gate_hclk_hsadc",
243 "gate_hclk_pidf", "gate_pclk_timer0",
244 "gate_pclk_timer1", "gate_pclk_timer2",
245 "gate_pclk_pwm01", "gate_pclk_pwm23",
246 "gate_pclk_spi0", "gate_pclk_spi1",
247 "gate_pclk_saradc", "gate_pclk_wdt";
248
249 #clock-cells = <1>;
250 };
251
252 clk_gates8: gate-clk@200000f0 {
253 compatible = "rockchip,rk2928-gate-clk";
254 reg = <0x200000f0 0x4>;
255 clocks = <&clk_gates0 5>, <&clk_gates0 5>,
256 <&clk_gates2 3>, <&clk_gates2 3>,
257 <&clk_gates0 5>, <&clk_gates0 5>,
258 <&clk_gates2 3>, <&clk_gates2 3>,
259 <&clk_gates2 3>, <&clk_gates0 5>,
260 <&clk_gates0 5>, <&clk_gates0 5>,
261 <&clk_gates2 3>, <&clk_gates2 3>,
262 <&dummy>, <&clk_gates0 5>;
263
264 clock-output-names =
265 "gate_pclk_uart0", "gate_pclk_uart1",
266 "gate_pclk_uart2", "gate_pclk_uart3",
267 "gate_pclk_i2c0", "gate_pclk_i2c1",
268 "gate_pclk_i2c2", "gate_pclk_i2c3",
269 "gate_pclk_i2c4", "gate_pclk_gpio0",
270 "gate_pclk_gpio1", "gate_pclk_gpio2",
271 "gate_pclk_gpio3", "gate_pclk_gpio4",
272 "reserved", "gate_pclk_gpio6";
273
274 #clock-cells = <1>;
275 };
276
277 clk_gates9: gate-clk@200000f4 {
278 compatible = "rockchip,rk2928-gate-clk";
279 reg = <0x200000f4 0x4>;
280 clocks = <&dummy>, <&clk_gates0 5>,
281 <&dummy>, <&dummy>,
282 <&dummy>, <&clk_gates1 4>,
283 <&clk_gates0 5>, <&dummy>,
284 <&dummy>, <&dummy>,
285 <&dummy>;
286
287 clock-output-names =
288 "gate_clk_core_dbg", "gate_pclk_dbg",
289 "gate_clk_trace", "gate_atclk",
290 "gate_clk_l2c", "gate_aclk_vio1",
291 "gate_pclk_publ", "gate_aclk_intmem0",
292 "gate_aclk_intmem1", "gate_aclk_intmem2",
293 "gate_aclk_intmem3";
294
295 #clock-cells = <1>;
296 };
297 };
298
299};
diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
new file mode 100644
index 000000000000..56bfac93d3f6
--- /dev/null
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -0,0 +1,390 @@
1/*
2 * Copyright (c) 2013 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18#include <dt-bindings/interrupt-controller/arm-gic.h>
19#include <dt-bindings/pinctrl/rockchip.h>
20#include "skeleton.dtsi"
21#include "rk3066a-clocks.dtsi"
22
23/ {
24 compatible = "rockchip,rk3066a";
25 interrupt-parent = <&gic>;
26
27 cpus {
28 #address-cells = <1>;
29 #size-cells = <0>;
30
31 cpu@0 {
32 device_type = "cpu";
33 compatible = "arm,cortex-a9";
34 next-level-cache = <&L2>;
35 reg = <0x0>;
36 };
37 cpu@1 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a9";
40 next-level-cache = <&L2>;
41 reg = <0x1>;
42 };
43 };
44
45 soc {
46 #address-cells = <1>;
47 #size-cells = <1>;
48 compatible = "simple-bus";
49 ranges;
50
51 gic: interrupt-controller@1013d000 {
52 compatible = "arm,cortex-a9-gic";
53 interrupt-controller;
54 #interrupt-cells = <3>;
55 reg = <0x1013d000 0x1000>,
56 <0x1013c100 0x0100>;
57 };
58
59 L2: l2-cache-controller@10138000 {
60 compatible = "arm,pl310-cache";
61 reg = <0x10138000 0x1000>;
62 cache-unified;
63 cache-level = <2>;
64 };
65
66 local-timer@1013c600 {
67 compatible = "arm,cortex-a9-twd-timer";
68 reg = <0x1013c600 0x20>;
69 interrupts = <GIC_PPI 13 0x304>;
70 clocks = <&dummy150m>;
71 };
72
73 timer@20038000 {
74 compatible = "snps,dw-apb-timer-osc";
75 reg = <0x20038000 0x100>;
76 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
77 clocks = <&clk_gates1 0>, <&clk_gates7 7>;
78 clock-names = "timer", "pclk";
79 };
80
81 timer@2003a000 {
82 compatible = "snps,dw-apb-timer-osc";
83 reg = <0x2003a000 0x100>;
84 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
85 clocks = <&clk_gates1 1>, <&clk_gates7 8>;
86 clock-names = "timer", "pclk";
87 };
88
89 timer@2000e000 {
90 compatible = "snps,dw-apb-timer-osc";
91 reg = <0x2000e000 0x100>;
92 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
93 clocks = <&clk_gates1 2>, <&clk_gates7 9>;
94 clock-names = "timer", "pclk";
95 };
96
97 pinctrl@20008000 {
98 compatible = "rockchip,rk3066a-pinctrl";
99 reg = <0x20008000 0x150>;
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103
104 gpio0: gpio0@20034000 {
105 compatible = "rockchip,gpio-bank";
106 reg = <0x20034000 0x100>;
107 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
108 clocks = <&clk_gates8 9>;
109
110 gpio-controller;
111 #gpio-cells = <2>;
112
113 interrupt-controller;
114 #interrupt-cells = <2>;
115 };
116
117 gpio1: gpio1@2003c000 {
118 compatible = "rockchip,gpio-bank";
119 reg = <0x2003c000 0x100>;
120 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
121 clocks = <&clk_gates8 10>;
122
123 gpio-controller;
124 #gpio-cells = <2>;
125
126 interrupt-controller;
127 #interrupt-cells = <2>;
128 };
129
130 gpio2: gpio2@2003e000 {
131 compatible = "rockchip,gpio-bank";
132 reg = <0x2003e000 0x100>;
133 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&clk_gates8 11>;
135
136 gpio-controller;
137 #gpio-cells = <2>;
138
139 interrupt-controller;
140 #interrupt-cells = <2>;
141 };
142
143 gpio3: gpio3@20080000 {
144 compatible = "rockchip,gpio-bank";
145 reg = <0x20080000 0x100>;
146 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&clk_gates8 12>;
148
149 gpio-controller;
150 #gpio-cells = <2>;
151
152 interrupt-controller;
153 #interrupt-cells = <2>;
154 };
155
156 gpio4: gpio4@20084000 {
157 compatible = "rockchip,gpio-bank";
158 reg = <0x20084000 0x100>;
159 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
160 clocks = <&clk_gates8 13>;
161
162 gpio-controller;
163 #gpio-cells = <2>;
164
165 interrupt-controller;
166 #interrupt-cells = <2>;
167 };
168
169 gpio6: gpio6@2000a000 {
170 compatible = "rockchip,gpio-bank";
171 reg = <0x2000a000 0x100>;
172 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&clk_gates8 15>;
174
175 gpio-controller;
176 #gpio-cells = <2>;
177
178 interrupt-controller;
179 #interrupt-cells = <2>;
180 };
181
182 pcfg_pull_default: pcfg_pull_default {
183 bias-pull-pin-default;
184 };
185
186 pcfg_pull_none: pcfg_pull_none {
187 bias-disable;
188 };
189
190 uart0 {
191 uart0_xfer: uart0-xfer {
192 rockchip,pins = <RK_GPIO1 0 RK_FUNC_1 &pcfg_pull_default>,
193 <RK_GPIO1 1 RK_FUNC_1 &pcfg_pull_default>;
194 rockchip,config = <&pcfg_pull_default>;
195 };
196
197 uart0_cts: uart0-cts {
198 rockchip,pins = <RK_GPIO1 2 RK_FUNC_1 &pcfg_pull_default>;
199 rockchip,config = <&pcfg_pull_default>;
200 };
201
202 uart0_rts: uart0-rts {
203 rockchip,pins = <RK_GPIO1 3 RK_FUNC_1 &pcfg_pull_default>;
204 rockchip,config = <&pcfg_pull_default>;
205 };
206 };
207
208 uart1 {
209 uart1_xfer: uart1-xfer {
210 rockchip,pins = <RK_GPIO1 4 RK_FUNC_1 &pcfg_pull_default>,
211 <RK_GPIO1 5 RK_FUNC_1 &pcfg_pull_default>;
212 rockchip,config = <&pcfg_pull_default>;
213 };
214
215 uart1_cts: uart1-cts {
216 rockchip,pins = <RK_GPIO1 6 RK_FUNC_1 &pcfg_pull_default>;
217 rockchip,config = <&pcfg_pull_default>;
218 };
219
220 uart1_rts: uart1-rts {
221 rockchip,pins = <RK_GPIO1 7 RK_FUNC_1 &pcfg_pull_default>;
222 rockchip,config = <&pcfg_pull_default>;
223 };
224 };
225
226 uart2 {
227 uart2_xfer: uart2-xfer {
228 rockchip,pins = <RK_GPIO1 8 RK_FUNC_1 &pcfg_pull_default>,
229 <RK_GPIO1 9 RK_FUNC_1 &pcfg_pull_default>;
230 rockchip,config = <&pcfg_pull_default>;
231 };
232 /* no rts / cts for uart2 */
233 };
234
235 uart3 {
236 uart3_xfer: uart3-xfer {
237 rockchip,pins = <RK_GPIO3 27 RK_FUNC_1 &pcfg_pull_default>,
238 <RK_GPIO3 28 RK_FUNC_1 &pcfg_pull_default>;
239 rockchip,config = <&pcfg_pull_default>;
240 };
241
242 uart3_cts: uart3-cts {
243 rockchip,pins = <RK_GPIO3 29 RK_FUNC_1 &pcfg_pull_default>;
244 rockchip,config = <&pcfg_pull_default>;
245 };
246
247 uart3_rts: uart3-rts {
248 rockchip,pins = <RK_GPIO3 30 RK_FUNC_1 &pcfg_pull_default>;
249 rockchip,config = <&pcfg_pull_default>;
250 };
251 };
252
253 sd0 {
254 sd0_clk: sd0-clk {
255 rockchip,pins = <RK_GPIO3 8 RK_FUNC_1 &pcfg_pull_default>;
256 rockchip,config = <&pcfg_pull_default>;
257 };
258
259 sd0_cmd: sd0-cmd {
260 rockchip,pins = <RK_GPIO3 9 RK_FUNC_1 &pcfg_pull_default>;
261 rockchip,config = <&pcfg_pull_default>;
262 };
263
264 sd0_cd: sd0-cd {
265 rockchip,pins = <RK_GPIO3 14 RK_FUNC_1 &pcfg_pull_default>;
266 rockchip,config = <&pcfg_pull_default>;
267 };
268
269 sd0_wp: sd0-wp {
270 rockchip,pins = <RK_GPIO3 15 RK_FUNC_1 &pcfg_pull_default>;
271 rockchip,config = <&pcfg_pull_default>;
272 };
273
274 sd0_bus1: sd0-bus-width1 {
275 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>;
276 rockchip,config = <&pcfg_pull_default>;
277 };
278
279 sd0_bus4: sd0-bus-width4 {
280 rockchip,pins = <RK_GPIO3 10 RK_FUNC_1 &pcfg_pull_default>,
281 <RK_GPIO3 11 RK_FUNC_1 &pcfg_pull_default>,
282 <RK_GPIO3 12 RK_FUNC_1 &pcfg_pull_default>,
283 <RK_GPIO3 13 RK_FUNC_1 &pcfg_pull_default>;
284 rockchip,config = <&pcfg_pull_default>;
285 };
286 };
287
288 sd1 {
289 sd1_clk: sd1-clk {
290 rockchip,pins = <RK_GPIO3 21 RK_FUNC_1 &pcfg_pull_default>;
291 rockchip,config = <&pcfg_pull_default>;
292 };
293
294 sd1_cmd: sd1-cmd {
295 rockchip,pins = <RK_GPIO3 16 RK_FUNC_1 &pcfg_pull_default>;
296 rockchip,config = <&pcfg_pull_default>;
297 };
298
299 sd1_cd: sd1-cd {
300 rockchip,pins = <RK_GPIO3 22 RK_FUNC_1 &pcfg_pull_default>;
301 rockchip,config = <&pcfg_pull_default>;
302 };
303
304 sd1_wp: sd1-wp {
305 rockchip,pins = <RK_GPIO3 23 RK_FUNC_1 &pcfg_pull_default>;
306 rockchip,config = <&pcfg_pull_default>;
307 };
308
309 sd1_bus1: sd1-bus-width1 {
310 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>;
311 rockchip,config = <&pcfg_pull_default>;
312 };
313
314 sd1_bus4: sd1-bus-width4 {
315 rockchip,pins = <RK_GPIO3 17 RK_FUNC_1 &pcfg_pull_default>,
316 <RK_GPIO3 18 RK_FUNC_1 &pcfg_pull_default>,
317 <RK_GPIO3 19 RK_FUNC_1 &pcfg_pull_default>,
318 <RK_GPIO3 20 RK_FUNC_1 &pcfg_pull_default>;
319 rockchip,config = <&pcfg_pull_default>;
320 };
321 };
322 };
323
324 uart0: serial@10124000 {
325 compatible = "snps,dw-apb-uart";
326 reg = <0x10124000 0x400>;
327 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
328 reg-shift = <2>;
329 reg-io-width = <1>;
330 clocks = <&clk_gates1 8>;
331 status = "disabled";
332 };
333
334 uart1: serial@10126000 {
335 compatible = "snps,dw-apb-uart";
336 reg = <0x10126000 0x400>;
337 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
338 reg-shift = <2>;
339 reg-io-width = <1>;
340 clocks = <&clk_gates1 10>;
341 status = "disabled";
342 };
343
344 uart2: serial@20064000 {
345 compatible = "snps,dw-apb-uart";
346 reg = <0x20064000 0x400>;
347 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
348 reg-shift = <2>;
349 reg-io-width = <1>;
350 clocks = <&clk_gates1 12>;
351 status = "disabled";
352 };
353
354 uart3: serial@20068000 {
355 compatible = "snps,dw-apb-uart";
356 reg = <0x20068000 0x400>;
357 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
358 reg-shift = <2>;
359 reg-io-width = <1>;
360 clocks = <&clk_gates1 14>;
361 status = "disabled";
362 };
363
364 dwmmc@10214000 {
365 compatible = "rockchip,rk2928-dw-mshc";
366 reg = <0x10214000 0x1000>;
367 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
368 #address-cells = <1>;
369 #size-cells = <0>;
370
371 clocks = <&clk_gates5 10>, <&clk_gates2 11>;
372 clock-names = "biu", "ciu";
373
374 status = "disabled";
375 };
376
377 dwmmc@10218000 {
378 compatible = "rockchip,rk2928-dw-mshc";
379 reg = <0x10218000 0x1000>;
380 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
381 #address-cells = <1>;
382 #size-cells = <0>;
383
384 clocks = <&clk_gates5 11>, <&clk_gates2 13>;
385 clock-names = "biu", "ciu";
386
387 status = "disabled";
388 };
389 };
390};
diff --git a/arch/arm/include/debug/rockchip.S b/arch/arm/include/debug/rockchip.S
new file mode 100644
index 000000000000..cfd883e69588
--- /dev/null
+++ b/arch/arm/include/debug/rockchip.S
@@ -0,0 +1,42 @@
1/*
2 * Early serial output macro for Rockchip SoCs
3 *
4 * Copyright (C) 2012 Maxime Ripard
5 *
6 * Maxime Ripard <maxime.ripard@free-electrons.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13#if defined(CONFIG_DEBUG_RK29_UART0)
14#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20060000
15#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed60000
16#elif defined(CONFIG_DEBUG_RK29_UART1)
17#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
18#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
19#elif defined(CONFIG_DEBUG_RK29_UART2)
20#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
21#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
22#elif defined(CONFIG_DEBUG_RK3X_UART0)
23#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10124000
24#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb24000
25#elif defined(CONFIG_DEBUG_RK3X_UART1)
26#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x10126000
27#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfeb26000
28#elif defined(CONFIG_DEBUG_RK3X_UART2)
29#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20064000
30#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed64000
31#elif defined(CONFIG_DEBUG_RK3X_UART3)
32#define ROCKCHIP_UART_DEBUG_PHYS_BASE 0x20068000
33#define ROCKCHIP_UART_DEBUG_VIRT_BASE 0xfed68000
34#endif
35
36 .macro addruart, rp, rv, tmp
37 ldr \rp, =ROCKCHIP_UART_DEBUG_PHYS_BASE
38 ldr \rv, =ROCKCHIP_UART_DEBUG_VIRT_BASE
39 .endm
40
41#define UART_SHIFT 2
42#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-picoxcell/Kconfig b/arch/arm/mach-picoxcell/Kconfig
index 13bae78b215a..b1022f4315f7 100644
--- a/arch/arm/mach-picoxcell/Kconfig
+++ b/arch/arm/mach-picoxcell/Kconfig
@@ -4,7 +4,6 @@ config ARCH_PICOXCELL
4 select ARM_PATCH_PHYS_VIRT 4 select ARM_PATCH_PHYS_VIRT
5 select ARM_VIC 5 select ARM_VIC
6 select CPU_V6K 6 select CPU_V6K
7 select DW_APB_TIMER
8 select DW_APB_TIMER_OF 7 select DW_APB_TIMER_OF
9 select GENERIC_CLOCKEVENTS 8 select GENERIC_CLOCKEVENTS
10 select HAVE_TCM 9 select HAVE_TCM
diff --git a/arch/arm/mach-picoxcell/common.c b/arch/arm/mach-picoxcell/common.c
index 70b441ad1d18..7cde0424d33c 100644
--- a/arch/arm/mach-picoxcell/common.c
+++ b/arch/arm/mach-picoxcell/common.c
@@ -15,7 +15,6 @@
15#include <linux/of_address.h> 15#include <linux/of_address.h>
16#include <linux/of_irq.h> 16#include <linux/of_irq.h>
17#include <linux/of_platform.h> 17#include <linux/of_platform.h>
18#include <linux/dw_apb_timer.h>
19 18
20#include <asm/mach/arch.h> 19#include <asm/mach/arch.h>
21#include <asm/mach/map.h> 20#include <asm/mach/map.h>
@@ -88,7 +87,6 @@ DT_MACHINE_START(PICOXCELL, "Picochip picoXcell")
88 .map_io = picoxcell_map_io, 87 .map_io = picoxcell_map_io,
89 .nr_irqs = NR_IRQS_LEGACY, 88 .nr_irqs = NR_IRQS_LEGACY,
90 .init_irq = irqchip_init, 89 .init_irq = irqchip_init,
91 .init_time = dw_apb_timer_init,
92 .init_machine = picoxcell_init_machine, 90 .init_machine = picoxcell_init_machine,
93 .dt_compat = picoxcell_dt_match, 91 .dt_compat = picoxcell_dt_match,
94 .restart = picoxcell_wdt_restart, 92 .restart = picoxcell_wdt_restart,
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
new file mode 100644
index 000000000000..25ee12b21f01
--- /dev/null
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -0,0 +1,16 @@
1config ARCH_ROCKCHIP
2 bool "Rockchip RK2928 and RK3xxx SOCs" if ARCH_MULTI_V7
3 select PINCTRL
4 select PINCTRL_ROCKCHIP
5 select ARCH_REQUIRE_GPIOLIB
6 select ARM_GIC
7 select CACHE_L2X0
8 select HAVE_ARM_TWD if LOCAL_TIMERS
9 select HAVE_SMP
10 select LOCAL_TIMERS if SMP
11 select COMMON_CLK
12 select GENERIC_CLOCKEVENTS
13 select DW_APB_TIMER_OF
14 help
15 Support for Rockchip's Cortex-A9 Single-to-Quad-Core-SoCs
16 containing the RK2928, RK30xx and RK31xx series.
diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile
new file mode 100644
index 000000000000..1547d4fc920a
--- /dev/null
+++ b/arch/arm/mach-rockchip/Makefile
@@ -0,0 +1 @@
obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip.o
diff --git a/arch/arm/mach-rockchip/rockchip.c b/arch/arm/mach-rockchip/rockchip.c
new file mode 100644
index 000000000000..724d2d81f976
--- /dev/null
+++ b/arch/arm/mach-rockchip/rockchip.c
@@ -0,0 +1,52 @@
1/*
2 * Device Tree support for Rockchip SoCs
3 *
4 * Copyright (c) 2013 MundoReader S.L.
5 * Author: Heiko Stuebner <heiko@sntech.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/kernel.h>
19#include <linux/init.h>
20#include <linux/of_platform.h>
21#include <linux/irqchip.h>
22#include <linux/dw_apb_timer.h>
23#include <linux/clk-provider.h>
24#include <asm/mach/arch.h>
25#include <asm/mach/map.h>
26#include <asm/hardware/cache-l2x0.h>
27
28static void __init rockchip_timer_init(void)
29{
30 of_clk_init(NULL);
31 clocksource_of_init();
32}
33
34static void __init rockchip_dt_init(void)
35{
36 l2x0_of_init(0, ~0UL);
37 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
38}
39
40static const char * const rockchip_board_dt_compat[] = {
41 "rockchip,rk2928",
42 "rockchip,rk3066a",
43 "rockchip,rk3066b",
44 "rockchip,rk3188",
45 NULL,
46};
47
48DT_MACHINE_START(ROCKCHIP_DT, "Rockchip Cortex-A9 (Device Tree)")
49 .init_machine = rockchip_dt_init,
50 .init_time = rockchip_timer_init,
51 .dt_compat = rockchip_board_dt_compat,
52MACHINE_END
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index 07dff6f18417..dd86db467521 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -7,7 +7,6 @@ config ARCH_SOCFPGA
7 select CLKDEV_LOOKUP 7 select CLKDEV_LOOKUP
8 select COMMON_CLK 8 select COMMON_CLK
9 select CPU_V7 9 select CPU_V7
10 select DW_APB_TIMER
11 select DW_APB_TIMER_OF 10 select DW_APB_TIMER_OF
12 select GENERIC_CLOCKEVENTS 11 select GENERIC_CLOCKEVENTS
13 select GPIO_PL061 if GPIOLIB 12 select GPIO_PL061 if GPIOLIB
diff --git a/arch/arm/mach-socfpga/socfpga.c b/arch/arm/mach-socfpga/socfpga.c
index 46a051359f02..8ea11b472b91 100644
--- a/arch/arm/mach-socfpga/socfpga.c
+++ b/arch/arm/mach-socfpga/socfpga.c
@@ -14,7 +14,6 @@
14 * You should have received a copy of the GNU General Public License 14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 */ 16 */
17#include <linux/dw_apb_timer.h>
18#include <linux/clk-provider.h> 17#include <linux/clk-provider.h>
19#include <linux/irqchip.h> 18#include <linux/irqchip.h>
20#include <linux/of_address.h> 19#include <linux/of_address.h>
@@ -120,7 +119,6 @@ DT_MACHINE_START(SOCFPGA, "Altera SOCFPGA")
120 .smp = smp_ops(socfpga_smp_ops), 119 .smp = smp_ops(socfpga_smp_ops),
121 .map_io = socfpga_map_io, 120 .map_io = socfpga_map_io,
122 .init_irq = socfpga_init_irq, 121 .init_irq = socfpga_init_irq,
123 .init_time = dw_apb_timer_init,
124 .init_machine = socfpga_cyclone5_init, 122 .init_machine = socfpga_cyclone5_init,
125 .restart = socfpga_cyclone5_restart, 123 .restart = socfpga_cyclone5_restart,
126 .dt_compat = altera_dt_match, 124 .dt_compat = altera_dt_match,
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index f151c6cf27c3..5871933c4e51 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -21,6 +21,8 @@ config DW_APB_TIMER
21 21
22config DW_APB_TIMER_OF 22config DW_APB_TIMER_OF
23 bool 23 bool
24 select DW_APB_TIMER
25 select CLKSRC_OF
24 26
25config ARMADA_370_XP_TIMER 27config ARMADA_370_XP_TIMER
26 bool 28 bool
diff --git a/drivers/clocksource/dw_apb_timer_of.c b/drivers/clocksource/dw_apb_timer_of.c
index ab09ed3742ee..cef554432a33 100644
--- a/drivers/clocksource/dw_apb_timer_of.c
+++ b/drivers/clocksource/dw_apb_timer_of.c
@@ -20,6 +20,7 @@
20#include <linux/of.h> 20#include <linux/of.h>
21#include <linux/of_address.h> 21#include <linux/of_address.h>
22#include <linux/of_irq.h> 22#include <linux/of_irq.h>
23#include <linux/clk.h>
23 24
24#include <asm/mach/time.h> 25#include <asm/mach/time.h>
25#include <asm/sched_clock.h> 26#include <asm/sched_clock.h>
@@ -27,14 +28,37 @@
27static void timer_get_base_and_rate(struct device_node *np, 28static void timer_get_base_and_rate(struct device_node *np,
28 void __iomem **base, u32 *rate) 29 void __iomem **base, u32 *rate)
29{ 30{
31 struct clk *timer_clk;
32 struct clk *pclk;
33
30 *base = of_iomap(np, 0); 34 *base = of_iomap(np, 0);
31 35
32 if (!*base) 36 if (!*base)
33 panic("Unable to map regs for %s", np->name); 37 panic("Unable to map regs for %s", np->name);
34 38
39 /*
40 * Not all implementations use a periphal clock, so don't panic
41 * if it's not present
42 */
43 pclk = of_clk_get_by_name(np, "pclk");
44 if (!IS_ERR(pclk))
45 if (clk_prepare_enable(pclk))
46 pr_warn("pclk for %s is present, but could not be activated\n",
47 np->name);
48
49 timer_clk = of_clk_get_by_name(np, "timer");
50 if (IS_ERR(timer_clk))
51 goto try_clock_freq;
52
53 if (!clk_prepare_enable(timer_clk)) {
54 *rate = clk_get_rate(timer_clk);
55 return;
56 }
57
58try_clock_freq:
35 if (of_property_read_u32(np, "clock-freq", rate) && 59 if (of_property_read_u32(np, "clock-freq", rate) &&
36 of_property_read_u32(np, "clock-frequency", rate)) 60 of_property_read_u32(np, "clock-frequency", rate))
37 panic("No clock-frequency property for %s", np->name); 61 panic("No clock nor clock-frequency property for %s", np->name);
38} 62}
39 63
40static void add_clockevent(struct device_node *event_timer) 64static void add_clockevent(struct device_node *event_timer)
@@ -57,6 +81,9 @@ static void add_clockevent(struct device_node *event_timer)
57 dw_apb_clockevent_register(ced); 81 dw_apb_clockevent_register(ced);
58} 82}
59 83
84static void __iomem *sched_io_base;
85static u32 sched_rate;
86
60static void add_clocksource(struct device_node *source_timer) 87static void add_clocksource(struct device_node *source_timer)
61{ 88{
62 void __iomem *iobase; 89 void __iomem *iobase;
@@ -71,9 +98,15 @@ static void add_clocksource(struct device_node *source_timer)
71 98
72 dw_apb_clocksource_start(cs); 99 dw_apb_clocksource_start(cs);
73 dw_apb_clocksource_register(cs); 100 dw_apb_clocksource_register(cs);
74}
75 101
76static void __iomem *sched_io_base; 102 /*
103 * Fallback to use the clocksource as sched_clock if no separate
104 * timer is found. sched_io_base then points to the current_value
105 * register of the clocksource timer.
106 */
107 sched_io_base = iobase + 0x04;
108 sched_rate = rate;
109}
77 110
78static u32 read_sched_clock(void) 111static u32 read_sched_clock(void)
79{ 112{
@@ -89,39 +122,37 @@ static const struct of_device_id sptimer_ids[] __initconst = {
89static void init_sched_clock(void) 122static void init_sched_clock(void)
90{ 123{
91 struct device_node *sched_timer; 124 struct device_node *sched_timer;
92 u32 rate;
93 125
94 sched_timer = of_find_matching_node(NULL, sptimer_ids); 126 sched_timer = of_find_matching_node(NULL, sptimer_ids);
95 if (!sched_timer) 127 if (sched_timer) {
96 panic("No RTC for sched clock to use"); 128 timer_get_base_and_rate(sched_timer, &sched_io_base,
129 &sched_rate);
130 of_node_put(sched_timer);
131 }
97 132
98 timer_get_base_and_rate(sched_timer, &sched_io_base, &rate); 133 setup_sched_clock(read_sched_clock, 32, sched_rate);
99 of_node_put(sched_timer);
100
101 setup_sched_clock(read_sched_clock, 32, rate);
102} 134}
103 135
104static const struct of_device_id osctimer_ids[] __initconst = { 136static int num_called;
105 { .compatible = "picochip,pc3x2-timer" }, 137static void __init dw_apb_timer_init(struct device_node *timer)
106 { .compatible = "snps,dw-apb-timer-osc" },
107 {},
108};
109
110void __init dw_apb_timer_init(void)
111{ 138{
112 struct device_node *event_timer, *source_timer; 139 switch (num_called) {
113 140 case 0:
114 event_timer = of_find_matching_node(NULL, osctimer_ids); 141 pr_debug("%s: found clockevent timer\n", __func__);
115 if (!event_timer) 142 add_clockevent(timer);
116 panic("No timer for clockevent"); 143 of_node_put(timer);
117 add_clockevent(event_timer); 144 break;
118 145 case 1:
119 source_timer = of_find_matching_node(event_timer, osctimer_ids); 146 pr_debug("%s: found clocksource timer\n", __func__);
120 if (!source_timer) 147 add_clocksource(timer);
121 panic("No timer for clocksource"); 148 of_node_put(timer);
122 add_clocksource(source_timer); 149 init_sched_clock();
123 150 break;
124 of_node_put(source_timer); 151 default:
125 152 break;
126 init_sched_clock(); 153 }
154
155 num_called++;
127} 156}
157CLOCKSOURCE_OF_DECLARE(pc3x2_timer, "picochip,pc3x2-timer", dw_apb_timer_init);
158CLOCKSOURCE_OF_DECLARE(apb_timer, "snps,dw-apb-timer-osc", dw_apb_timer_init);
diff --git a/include/linux/dw_apb_timer.h b/include/linux/dw_apb_timer.h
index dd755ce2a5eb..07261d52a6df 100644
--- a/include/linux/dw_apb_timer.h
+++ b/include/linux/dw_apb_timer.h
@@ -53,5 +53,4 @@ void dw_apb_clocksource_start(struct dw_apb_clocksource *dw_cs);
53cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs); 53cycle_t dw_apb_clocksource_read(struct dw_apb_clocksource *dw_cs);
54void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs); 54void dw_apb_clocksource_unregister(struct dw_apb_clocksource *dw_cs);
55 55
56extern void dw_apb_timer_init(void);
57#endif /* __DW_APB_TIMER_H__ */ 56#endif /* __DW_APB_TIMER_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 20:14:44 -0400