arm: Add v7_invalidate_l1 to cache-v7.S

mach-socfpga is another platform that needs to use v7_invalidate_l1 to bringup additional cores. There was a comment that the ideal place for v7_invalidate_l1 should be in arm/mm/cache-v7.S Signed-off-by: Dinh Nguyen <dinguyen@altera.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Pavel Machek <pavel@denx.de> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Pavel Machek <pavel@denx.de> Tested-by: Stephen Warren <swarren@nvidia.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Olof Johansson <olof@lixom.net> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: Magnus Damm <magnus.damm@gmail.com> Signed-off-by: Olof Johansson <olof@lixom.net>
author: Dinh Nguyen <dinguyen@altera.com> 2013-02-11 18:30:32 -0500
committer: Olof Johansson <olof@lixom.net> 2013-02-11 22:37:24 -0500
commit: c08e20d246ded319fc77616c64dcbf69456cb4be (patch)
tree: 0858e1ba5ccb0fa76cdd52f039d2fb3e2cb9f333
parent: 90c294557d411100d3557bc2762a98a93f989430 (diff)
4 files changed, 46 insertions, 138 deletions
diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S
index 7e49deb128a4..921fc1555854 100644
--- a/arch/arm/mach-imx/headsmp.S
+++ b/arch/arm/mach-imx/headsmp.S
@@ -17,53 +17,6 @@
        .section ".text.head", "ax"
-/*
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3      @ NumWays - 1
-        add     r2, r2, #1              @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4      @ SetShift
-        clz     r1, r3          @ WayShift
-        add     r4, r3, #1      @ NumWays
-1:      sub     r2, r2, #1      @ NumSets--
-        mov     r3, r4          @ Temp = NumWays
-2:      subs    r3, r3, #1      @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 #ifdef CONFIG_SMP
 ENTRY(v7_secondary_startup)
        bl      v7_invalidate_l1
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index b202c1272526..96001fd49b6c 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,54 +16,6 @@
        __CPUINIT
-/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
- *
- * The secondary kernel init calls v7_flush_dcache_all before it enables
- * the L1; however, the L1 comes out of reset in an undefined state, so
- * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- * of cache lines with uninitialized data and uninitialized tags to get
- * written out to memory, which does really unpleasant things to the main
- * processor.  We fix this by performing an invalidate, rather than a
- * clean + invalidate, before jumping into the kernel.
- *
- * This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
- * to be called for both secondary cores startup and primary core resume
- * procedures.  Ideally, it should be moved into arch/arm/mm/cache-v7.S.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 0, r0, c7, c5, 0   @ invalidate I cache
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3      @ NumWays - 1
-        add     r2, r2, #1              @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4      @ SetShift
-        clz     r1, r3          @ WayShift
-        add     r4, r3, #1      @ NumWays
-1:      sub     r2, r2, #1      @ NumSets--
-        mov     r3, r4          @ Temp = NumWays
-2:      subs    r3, r3, #1      @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 ENTRY(shmobile_invalidate_start)
        bl      v7_invalidate_l1
        b       secondary_startup
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index 4a317fae6860..fb082c492209 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -18,49 +18,6 @@
        .section ".text.head", "ax"
        __CPUINIT
-/*
- * Tegra specific entry point for secondary CPUs.
- *   The secondary kernel init calls v7_flush_dcache_all before it enables
- *   the L1; however, the L1 comes out of reset in an undefined state, so
- *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
- *   of cache lines with uninitialized data and uninitialized tags to get
- *   written out to memory, which does really unpleasant things to the main
- *   processor.  We fix this by performing an invalidate, rather than a
- *   clean + invalidate, before jumping into the kernel.
- */
-ENTRY(v7_invalidate_l1)
-        mov     r0, #0
-        mcr     p15, 2, r0, c0, c0, 0
-        mrc     p15, 1, r0, c0, c0, 0
-        ldr     r1, =0x7fff
-        and     r2, r1, r0, lsr #13
-        ldr     r1, =0x3ff
-        and     r3, r1, r0, lsr #3  @ NumWays - 1
-        add     r2, r2, #1          @ NumSets
-        and     r0, r0, #0x7
-        add     r0, r0, #4          @ SetShift
-        clz     r1, r3              @ WayShift
-        add     r4, r3, #1          @ NumWays
-1:      sub     r2, r2, #1          @ NumSets--
-        mov     r3, r4              @ Temp = NumWays
-2:      subs    r3, r3, #1          @ Temp--
-        mov     r5, r3, lsl r1
-        mov     r6, r2, lsl r0
-        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
-        mcr     p15, 0, r5, c7, c6, 2
-        bgt     2b
-        cmp     r2, #0
-        bgt     1b
-        dsb
-        isb
-        mov     pc, lr
-ENDPROC(v7_invalidate_l1)
 ENTRY(tegra_secondary_startup)
        bl      v7_invalidate_l1
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index 7539ec275065..15451ee4acc8 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -19,6 +19,52 @@
 #include "proc-macros.S"
 /*
+ * The secondary kernel init calls v7_flush_dcache_all before it enables
+ * the L1; however, the L1 comes out of reset in an undefined state, so
+ * the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ * of cache lines with uninitialized data and uninitialized tags to get
+ * written out to memory, which does really unpleasant things to the main
+ * processor.  We fix this by performing an invalidate, rather than a
+ * clean + invalidate, before jumping into the kernel.
+ *
+ * This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
+ * to be called for both secondary cores startup and primary core resume
+ * procedures.
+ */
+ENTRY(v7_invalidate_l1)
+       mov     r0, #0
+       mcr     p15, 2, r0, c0, c0, 0
+       mrc     p15, 1, r0, c0, c0, 0
+       ldr     r1, =0x7fff
+       and     r2, r1, r0, lsr #13
+       ldr     r1, =0x3ff
+       and     r3, r1, r0, lsr #3      @ NumWays - 1
+       add     r2, r2, #1              @ NumSets
+       and     r0, r0, #0x7
+       add     r0, r0, #4      @ SetShift
+       clz     r1, r3          @ WayShift
+       add     r4, r3, #1      @ NumWays
+1:     sub     r2, r2, #1      @ NumSets--
+       mov     r3, r4          @ Temp = NumWays
+2:     subs    r3, r3, #1      @ Temp--
+       mov     r5, r3, lsl r1
+       mov     r6, r2, lsl r0
+       orr     r5, r5, r6      @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+       mcr     p15, 0, r5, c7, c6, 2
+       bgt     2b
+       cmp     r2, #0
+       bgt     1b
+       dsb
+       isb
+       mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+/*
 *      v7_flush_icache_all()
 *
 *      Flush the whole I-cache.
author	Dinh Nguyen <dinguyen@altera.com>	2013-02-11 18:30:32 -0500
committer	Olof Johansson <olof@lixom.net>	2013-02-11 22:37:24 -0500
commit	c08e20d246ded319fc77616c64dcbf69456cb4be (patch)
tree	0858e1ba5ccb0fa76cdd52f039d2fb3e2cb9f333
parent	90c294557d411100d3557bc2762a98a93f989430 (diff)

diff --git a/arch/arm/mach-imx/headsmp.S b/arch/arm/mach-imx/headsmp.S index 7e49deb128a4..921fc1555854 100644 --- a/arch/arm/mach-imx/headsmp.S +++ b/arch/arm/mach-imx/headsmp.S
@@ -17,53 +17,6 @@
17		17
18	.section ".text.head", "ax"	18	.section ".text.head", "ax"
19		19
20	/*
21	* The secondary kernel init calls v7_flush_dcache_all before it enables
22	* the L1; however, the L1 comes out of reset in an undefined state, so
23	* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
24	* of cache lines with uninitialized data and uninitialized tags to get
25	* written out to memory, which does really unpleasant things to the main
26	* processor. We fix this by performing an invalidate, rather than a
27	* clean + invalidate, before jumping into the kernel.
28	*
29	* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
30	* to be called for both secondary cores startup and primary core resume
31	* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
32	*/
33	ENTRY(v7_invalidate_l1)
34	mov r0, #0
35	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
36	mcr p15, 2, r0, c0, c0, 0
37	mrc p15, 1, r0, c0, c0, 0
38
39	ldr r1, =0x7fff
40	and r2, r1, r0, lsr #13
41
42	ldr r1, =0x3ff
43
44	and r3, r1, r0, lsr #3 @ NumWays - 1
45	add r2, r2, #1 @ NumSets
46
47	and r0, r0, #0x7
48	add r0, r0, #4 @ SetShift
49
50	clz r1, r3 @ WayShift
51	add r4, r3, #1 @ NumWays
52	1: sub r2, r2, #1 @ NumSets--
53	mov r3, r4 @ Temp = NumWays
54	2: subs r3, r3, #1 @ Temp--
55	mov r5, r3, lsl r1
56	mov r6, r2, lsl r0
57	orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
58	mcr p15, 0, r5, c7, c6, 2
59	bgt 2b
60	cmp r2, #0
61	bgt 1b
62	dsb
63	isb
64	mov pc, lr
65	ENDPROC(v7_invalidate_l1)
66
67	#ifdef CONFIG_SMP	20	#ifdef CONFIG_SMP
68	ENTRY(v7_secondary_startup)	21	ENTRY(v7_secondary_startup)
69	bl v7_invalidate_l1	22	bl v7_invalidate_l1


diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S index b202c1272526..96001fd49b6c 100644 --- a/arch/arm/mach-shmobile/headsmp.S +++ b/arch/arm/mach-shmobile/headsmp.S
@@ -16,54 +16,6 @@
16		16
17	__CPUINIT	17	__CPUINIT
18		18
19	/* Cache invalidation nicked from arch/arm/mach-imx/head-v7.S, thanks!
20	*
21	* The secondary kernel init calls v7_flush_dcache_all before it enables
22	* the L1; however, the L1 comes out of reset in an undefined state, so
23	* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
24	* of cache lines with uninitialized data and uninitialized tags to get
25	* written out to memory, which does really unpleasant things to the main
26	* processor. We fix this by performing an invalidate, rather than a
27	* clean + invalidate, before jumping into the kernel.
28	*
29	* This funciton is cloned from arch/arm/mach-tegra/headsmp.S, and needs
30	* to be called for both secondary cores startup and primary core resume
31	* procedures. Ideally, it should be moved into arch/arm/mm/cache-v7.S.
32	*/
33	ENTRY(v7_invalidate_l1)
34	mov r0, #0
35	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
36	mcr p15, 2, r0, c0, c0, 0
37	mrc p15, 1, r0, c0, c0, 0
38
39	ldr r1, =0x7fff
40	and r2, r1, r0, lsr #13
41
42	ldr r1, =0x3ff
43
44	and r3, r1, r0, lsr #3 @ NumWays - 1
45	add r2, r2, #1 @ NumSets
46
47	and r0, r0, #0x7
48	add r0, r0, #4 @ SetShift
49
50	clz r1, r3 @ WayShift
51	add r4, r3, #1 @ NumWays
52	1: sub r2, r2, #1 @ NumSets--
53	mov r3, r4 @ Temp = NumWays
54	2: subs r3, r3, #1 @ Temp--
55	mov r5, r3, lsl r1
56	mov r6, r2, lsl r0
57	orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
58	mcr p15, 0, r5, c7, c6, 2
59	bgt 2b
60	cmp r2, #0
61	bgt 1b
62	dsb
63	isb
64	mov pc, lr
65	ENDPROC(v7_invalidate_l1)
66
67	ENTRY(shmobile_invalidate_start)	19	ENTRY(shmobile_invalidate_start)
68	bl v7_invalidate_l1	20	bl v7_invalidate_l1
69	b secondary_startup	21	b secondary_startup


diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S index 4a317fae6860..fb082c492209 100644 --- a/arch/arm/mach-tegra/headsmp.S +++ b/arch/arm/mach-tegra/headsmp.S
@@ -18,49 +18,6 @@
18	.section ".text.head", "ax"	18	.section ".text.head", "ax"
19	__CPUINIT	19	__CPUINIT
20		20
21	/*
22	* Tegra specific entry point for secondary CPUs.
23	* The secondary kernel init calls v7_flush_dcache_all before it enables
24	* the L1; however, the L1 comes out of reset in an undefined state, so
25	* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
26	* of cache lines with uninitialized data and uninitialized tags to get
27	* written out to memory, which does really unpleasant things to the main
28	* processor. We fix this by performing an invalidate, rather than a
29	* clean + invalidate, before jumping into the kernel.
30	*/
31	ENTRY(v7_invalidate_l1)
32	mov r0, #0
33	mcr p15, 2, r0, c0, c0, 0
34	mrc p15, 1, r0, c0, c0, 0
35
36	ldr r1, =0x7fff
37	and r2, r1, r0, lsr #13
38
39	ldr r1, =0x3ff
40
41	and r3, r1, r0, lsr #3 @ NumWays - 1
42	add r2, r2, #1 @ NumSets
43
44	and r0, r0, #0x7
45	add r0, r0, #4 @ SetShift
46
47	clz r1, r3 @ WayShift
48	add r4, r3, #1 @ NumWays
49	1: sub r2, r2, #1 @ NumSets--
50	mov r3, r4 @ Temp = NumWays
51	2: subs r3, r3, #1 @ Temp--
52	mov r5, r3, lsl r1
53	mov r6, r2, lsl r0
54	orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
55	mcr p15, 0, r5, c7, c6, 2
56	bgt 2b
57	cmp r2, #0
58	bgt 1b
59	dsb
60	isb
61	mov pc, lr
62	ENDPROC(v7_invalidate_l1)
63
64		21
65	ENTRY(tegra_secondary_startup)	22	ENTRY(tegra_secondary_startup)
66	bl v7_invalidate_l1	23	bl v7_invalidate_l1


diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S index 7539ec275065..15451ee4acc8 100644 --- a/arch/arm/mm/cache-v7.S +++ b/arch/arm/mm/cache-v7.S
@@ -19,6 +19,52 @@
19	#include "proc-macros.S"	19	#include "proc-macros.S"
20		20
21	/*	21	/*
		22	* The secondary kernel init calls v7_flush_dcache_all before it enables
		23	* the L1; however, the L1 comes out of reset in an undefined state, so
		24	* the clean + invalidate performed by v7_flush_dcache_all causes a bunch
		25	* of cache lines with uninitialized data and uninitialized tags to get
		26	* written out to memory, which does really unpleasant things to the main
		27	* processor. We fix this by performing an invalidate, rather than a
		28	* clean + invalidate, before jumping into the kernel.
		29	*
		30	* This function is cloned from arch/arm/mach-tegra/headsmp.S, and needs
		31	* to be called for both secondary cores startup and primary core resume
		32	* procedures.
		33	*/
		34	ENTRY(v7_invalidate_l1)
		35	mov r0, #0
		36	mcr p15, 2, r0, c0, c0, 0
		37	mrc p15, 1, r0, c0, c0, 0
		38
		39	ldr r1, =0x7fff
		40	and r2, r1, r0, lsr #13
		41
		42	ldr r1, =0x3ff
		43
		44	and r3, r1, r0, lsr #3 @ NumWays - 1
		45	add r2, r2, #1 @ NumSets
		46
		47	and r0, r0, #0x7
		48	add r0, r0, #4 @ SetShift
		49
		50	clz r1, r3 @ WayShift
		51	add r4, r3, #1 @ NumWays
		52	1: sub r2, r2, #1 @ NumSets--
		53	mov r3, r4 @ Temp = NumWays
		54	2: subs r3, r3, #1 @ Temp--
		55	mov r5, r3, lsl r1
		56	mov r6, r2, lsl r0
		57	orr r5, r5, r6 @ Reg = (Temp<<WayShift)\|(NumSets<<SetShift)
		58	mcr p15, 0, r5, c7, c6, 2
		59	bgt 2b
		60	cmp r2, #0
		61	bgt 1b
		62	dsb
		63	isb
		64	mov pc, lr
		65	ENDPROC(v7_invalidate_l1)
		66
		67	/*
22	* v7_flush_icache_all()	68	* v7_flush_icache_all()
23	*	69	*
24	* Flush the whole I-cache.	70	* Flush the whole I-cache.