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authorRob Clark <robdclark@gmail.com>2014-09-05 13:06:37 -0400
committerRob Clark <robdclark@gmail.com>2014-09-10 11:19:08 -0400
commitbfd28b136298f37ef2e10494d3a0bfb4dcbaa7b9 (patch)
tree2b0b933397b7abd2d39f270b29db972282934f1f
parentdac746e04e2ed90bdf9b7f808ec1be0e5f1298c6 (diff)
drm/msm/adreno: split adreno device out into it's own file
We'd rather not duplicate these parts as support for additional gpu generations is added. Signed-off-by: Rob Clark <robdclark@gmail.com>
Diffstat
-rw-r--r--drivers/gpu/drm/msm/Makefile1
-rw-r--r--drivers/gpu/drm/msm/adreno/a3xx_gpu.c155
-rw-r--r--drivers/gpu/drm/msm/adreno/adreno_device.c169
-rw-r--r--drivers/gpu/drm/msm/msm_drv.c4
-rw-r--r--drivers/gpu/drm/msm/msm_gpu.h4
5 files changed, 174 insertions, 159 deletions
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 48f796056887..6283dcb96af5 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -4,6 +4,7 @@ ifeq (, $(findstring -W,$(EXTRA_CFLAGS)))
4endif 4endif
5 5
6msm-y := \ 6msm-y := \
7 adreno/adreno_device.o \
7 adreno/adreno_gpu.o \ 8 adreno/adreno_gpu.o \
8 adreno/a3xx_gpu.o \ 9 adreno/a3xx_gpu.o \
9 hdmi/hdmi.o \ 10 hdmi/hdmi.o \
diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 2773600c9488..42bdcf72a771 100644
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -549,158 +549,3 @@ fail:
549 549
550 return ERR_PTR(ret); 550 return ERR_PTR(ret);
551} 551}
552
553/*
554 * The a3xx device:
555 */
556
557#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
558# include <mach/kgsl.h>
559#endif
560
561static void set_gpu_pdev(struct drm_device *dev,
562 struct platform_device *pdev)
563{
564 struct msm_drm_private *priv = dev->dev_private;
565 priv->gpu_pdev = pdev;
566}
567
568static int a3xx_bind(struct device *dev, struct device *master, void *data)
569{
570 static struct adreno_platform_config config = {};
571#ifdef CONFIG_OF
572 struct device_node *child, *node = dev->of_node;
573 u32 val;
574 int ret;
575
576 ret = of_property_read_u32(node, "qcom,chipid", &val);
577 if (ret) {
578 dev_err(dev, "could not find chipid: %d\n", ret);
579 return ret;
580 }
581
582 config.rev = ADRENO_REV((val >> 24) & 0xff,
583 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
584
585 /* find clock rates: */
586 config.fast_rate = 0;
587 config.slow_rate = ~0;
588 for_each_child_of_node(node, child) {
589 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
590 struct device_node *pwrlvl;
591 for_each_child_of_node(child, pwrlvl) {
592 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
593 if (ret) {
594 dev_err(dev, "could not find gpu-freq: %d\n", ret);
595 return ret;
596 }
597 config.fast_rate = max(config.fast_rate, val);
598 config.slow_rate = min(config.slow_rate, val);
599 }
600 }
601 }
602
603 if (!config.fast_rate) {
604 dev_err(dev, "could not find clk rates\n");
605 return -ENXIO;
606 }
607
608#else
609 struct kgsl_device_platform_data *pdata = dev->platform_data;
610 uint32_t version = socinfo_get_version();
611 if (cpu_is_apq8064ab()) {
612 config.fast_rate = 450000000;
613 config.slow_rate = 27000000;
614 config.bus_freq = 4;
615 config.rev = ADRENO_REV(3, 2, 1, 0);
616 } else if (cpu_is_apq8064()) {
617 config.fast_rate = 400000000;
618 config.slow_rate = 27000000;
619 config.bus_freq = 4;
620
621 if (SOCINFO_VERSION_MAJOR(version) == 2)
622 config.rev = ADRENO_REV(3, 2, 0, 2);
623 else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
624 (SOCINFO_VERSION_MINOR(version) == 1))
625 config.rev = ADRENO_REV(3, 2, 0, 1);
626 else
627 config.rev = ADRENO_REV(3, 2, 0, 0);
628
629 } else if (cpu_is_msm8960ab()) {
630 config.fast_rate = 400000000;
631 config.slow_rate = 320000000;
632 config.bus_freq = 4;
633
634 if (SOCINFO_VERSION_MINOR(version) == 0)
635 config.rev = ADRENO_REV(3, 2, 1, 0);
636 else
637 config.rev = ADRENO_REV(3, 2, 1, 1);
638
639 } else if (cpu_is_msm8930()) {
640 config.fast_rate = 400000000;
641 config.slow_rate = 27000000;
642 config.bus_freq = 3;
643
644 if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
645 (SOCINFO_VERSION_MINOR(version) == 2))
646 config.rev = ADRENO_REV(3, 0, 5, 2);
647 else
648 config.rev = ADRENO_REV(3, 0, 5, 0);
649
650 }
651# ifdef CONFIG_MSM_BUS_SCALING
652 config.bus_scale_table = pdata->bus_scale_table;
653# endif
654#endif
655 dev->platform_data = &config;
656 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
657 return 0;
658}
659
660static void a3xx_unbind(struct device *dev, struct device *master,
661 void *data)
662{
663 set_gpu_pdev(dev_get_drvdata(master), NULL);
664}
665
666static const struct component_ops a3xx_ops = {
667 .bind = a3xx_bind,
668 .unbind = a3xx_unbind,
669};
670
671static int a3xx_probe(struct platform_device *pdev)
672{
673 return component_add(&pdev->dev, &a3xx_ops);
674}
675
676static int a3xx_remove(struct platform_device *pdev)
677{
678 component_del(&pdev->dev, &a3xx_ops);
679 return 0;
680}
681
682static const struct of_device_id dt_match[] = {
683 { .compatible = "qcom,adreno-3xx" },
684 /* for backwards compat w/ downstream kgsl DT files: */
685 { .compatible = "qcom,kgsl-3d0" },
686 {}
687};
688
689static struct platform_driver a3xx_driver = {
690 .probe = a3xx_probe,
691 .remove = a3xx_remove,
692 .driver = {
693 .name = "kgsl-3d0",
694 .of_match_table = dt_match,
695 },
696};
697
698void __init a3xx_register(void)
699{
700 platform_driver_register(&a3xx_driver);
701}
702
703void __exit a3xx_unregister(void)
704{
705 platform_driver_unregister(&a3xx_driver);
706}
diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c
new file mode 100644
index 000000000000..124e23d63018
--- /dev/null
+++ b/drivers/gpu/drm/msm/adreno/adreno_device.c
@@ -0,0 +1,169 @@
1/*
2 * Copyright (C) 2013-2014 Red Hat
3 * Author: Rob Clark <robdclark@gmail.com>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
16 */
17
18#include "adreno_gpu.h"
19
20#if defined(CONFIG_MSM_BUS_SCALING) && !defined(CONFIG_OF)
21# include <mach/kgsl.h>
22#endif
23
24static void set_gpu_pdev(struct drm_device *dev,
25 struct platform_device *pdev)
26{
27 struct msm_drm_private *priv = dev->dev_private;
28 priv->gpu_pdev = pdev;
29}
30
31static int adreno_bind(struct device *dev, struct device *master, void *data)
32{
33 static struct adreno_platform_config config = {};
34#ifdef CONFIG_OF
35 struct device_node *child, *node = dev->of_node;
36 u32 val;
37 int ret;
38
39 ret = of_property_read_u32(node, "qcom,chipid", &val);
40 if (ret) {
41 dev_err(dev, "could not find chipid: %d\n", ret);
42 return ret;
43 }
44
45 config.rev = ADRENO_REV((val >> 24) & 0xff,
46 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
47
48 /* find clock rates: */
49 config.fast_rate = 0;
50 config.slow_rate = ~0;
51 for_each_child_of_node(node, child) {
52 if (of_device_is_compatible(child, "qcom,gpu-pwrlevels")) {
53 struct device_node *pwrlvl;
54 for_each_child_of_node(child, pwrlvl) {
55 ret = of_property_read_u32(pwrlvl, "qcom,gpu-freq", &val);
56 if (ret) {
57 dev_err(dev, "could not find gpu-freq: %d\n", ret);
58 return ret;
59 }
60 config.fast_rate = max(config.fast_rate, val);
61 config.slow_rate = min(config.slow_rate, val);
62 }
63 }
64 }
65
66 if (!config.fast_rate) {
67 dev_err(dev, "could not find clk rates\n");
68 return -ENXIO;
69 }
70
71#else
72 struct kgsl_device_platform_data *pdata = dev->platform_data;
73 uint32_t version = socinfo_get_version();
74 if (cpu_is_apq8064ab()) {
75 config.fast_rate = 450000000;
76 config.slow_rate = 27000000;
77 config.bus_freq = 4;
78 config.rev = ADRENO_REV(3, 2, 1, 0);
79 } else if (cpu_is_apq8064()) {
80 config.fast_rate = 400000000;
81 config.slow_rate = 27000000;
82 config.bus_freq = 4;
83
84 if (SOCINFO_VERSION_MAJOR(version) == 2)
85 config.rev = ADRENO_REV(3, 2, 0, 2);
86 else if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
87 (SOCINFO_VERSION_MINOR(version) == 1))
88 config.rev = ADRENO_REV(3, 2, 0, 1);
89 else
90 config.rev = ADRENO_REV(3, 2, 0, 0);
91
92 } else if (cpu_is_msm8960ab()) {
93 config.fast_rate = 400000000;
94 config.slow_rate = 320000000;
95 config.bus_freq = 4;
96
97 if (SOCINFO_VERSION_MINOR(version) == 0)
98 config.rev = ADRENO_REV(3, 2, 1, 0);
99 else
100 config.rev = ADRENO_REV(3, 2, 1, 1);
101
102 } else if (cpu_is_msm8930()) {
103 config.fast_rate = 400000000;
104 config.slow_rate = 27000000;
105 config.bus_freq = 3;
106
107 if ((SOCINFO_VERSION_MAJOR(version) == 1) &&
108 (SOCINFO_VERSION_MINOR(version) == 2))
109 config.rev = ADRENO_REV(3, 0, 5, 2);
110 else
111 config.rev = ADRENO_REV(3, 0, 5, 0);
112
113 }
114# ifdef CONFIG_MSM_BUS_SCALING
115 config.bus_scale_table = pdata->bus_scale_table;
116# endif
117#endif
118 dev->platform_data = &config;
119 set_gpu_pdev(dev_get_drvdata(master), to_platform_device(dev));
120 return 0;
121}
122
123static void adreno_unbind(struct device *dev, struct device *master,
124 void *data)
125{
126 set_gpu_pdev(dev_get_drvdata(master), NULL);
127}
128
129static const struct component_ops a3xx_ops = {
130 .bind = adreno_bind,
131 .unbind = adreno_unbind,
132};
133
134static int adreno_probe(struct platform_device *pdev)
135{
136 return component_add(&pdev->dev, &a3xx_ops);
137}
138
139static int adreno_remove(struct platform_device *pdev)
140{
141 component_del(&pdev->dev, &a3xx_ops);
142 return 0;
143}
144
145static const struct of_device_id dt_match[] = {
146 { .compatible = "qcom,adreno-3xx" },
147 /* for backwards compat w/ downstream kgsl DT files: */
148 { .compatible = "qcom,kgsl-3d0" },
149 {}
150};
151
152static struct platform_driver adreno_driver = {
153 .probe = adreno_probe,
154 .remove = adreno_remove,
155 .driver = {
156 .name = "adreno",
157 .of_match_table = dt_match,
158 },
159};
160
161void __init adreno_register(void)
162{
163 platform_driver_register(&adreno_driver);
164}
165
166void __exit adreno_unregister(void)
167{
168 platform_driver_unregister(&adreno_driver);
169}
diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c
index 3b05fb4e3d66..7008900e6b29 100644
--- a/drivers/gpu/drm/msm/msm_drv.c
+++ b/drivers/gpu/drm/msm/msm_drv.c
@@ -1027,7 +1027,7 @@ static int __init msm_drm_register(void)
1027{ 1027{
1028 DBG("init"); 1028 DBG("init");
1029 hdmi_register(); 1029 hdmi_register();
1030 a3xx_register(); 1030 adreno_register();
1031 return platform_driver_register(&msm_platform_driver); 1031 return platform_driver_register(&msm_platform_driver);
1032} 1032}
1033 1033
@@ -1036,7 +1036,7 @@ static void __exit msm_drm_unregister(void)
1036 DBG("fini"); 1036 DBG("fini");
1037 platform_driver_unregister(&msm_platform_driver); 1037 platform_driver_unregister(&msm_platform_driver);
1038 hdmi_unregister(); 1038 hdmi_unregister();
1039 a3xx_unregister(); 1039 adreno_unregister();
1040} 1040}
1041 1041
1042module_init(msm_drm_register); 1042module_init(msm_drm_register);
diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h
index 9b579b792840..38ef033c81f3 100644
--- a/drivers/gpu/drm/msm/msm_gpu.h
+++ b/drivers/gpu/drm/msm/msm_gpu.h
@@ -167,7 +167,7 @@ int msm_gpu_init(struct drm_device *drm, struct platform_device *pdev,
167void msm_gpu_cleanup(struct msm_gpu *gpu); 167void msm_gpu_cleanup(struct msm_gpu *gpu);
168 168
169struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); 169struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
170void __init a3xx_register(void); 170void __init adreno_register(void);
171void __exit a3xx_unregister(void); 171void __exit adreno_unregister(void);
172 172
173#endif /* __MSM_GPU_H__ */ 173#endif /* __MSM_GPU_H__ */
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-22 10:11:16 -0400