aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorArnd Bergmann <arnd@arndb.de>2012-05-11 10:34:55 -0400
committerArnd Bergmann <arnd@arndb.de>2012-05-11 10:34:55 -0400
commitbef945965884365cdc49985169977a51390253f1 (patch)
tree9343cecfdb735b4b9c327edea65e71801b5c3efe
parent66f75a5d028beaf67c931435fdc3e7823125730c (diff)
parentf0948f59dbc8e725a96ba16da666e8f5cdd43ba8 (diff)
Merge branch 'depends/clk/clk-next' into next/clock
Mike Turquette <mturquette@ti.com> has asked me to take the clock changes through the arm-soc tree while there are still so many inderdependencies, so this is the entire branch. * depends/clk/clk-next: (30 commits) clk: add a fixed factor clock clk: mux: assign init data clk: remove COMMON_CLK_DISABLE_UNUSED clk: prevent spurious parent rate propagation MAINTAINERS: add entry for common clk framework clk: clk_set_rate() must fail if CLK_SET_RATE_GATE is set and clk is enabled clk: Use a separate struct for holding init data. clk: constify parent name arrays in macros clk: remove trailing whitespace from clk.h clk: select CLKDEV_LOOKUP for COMMON_CLK clk: Don't set clk->new_rate twice clk: clk-private: Add DEFINE_CLK macro clk: clk-gate: Create clk_gate_endisable() clk: Fix typo in comment clk: propagate round_rate for CLK_SET_RATE_PARENT case clk: pass parent_rate into .set_rate clk: always pass parent_rate into .round_rate clk: basic: improve parent_names & return errors clk: core: copy parent_names & return error codes clk: Constify parent name arrays ... Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat
-rw-r--r--MAINTAINERS10
-rw-r--r--drivers/clk/Kconfig12
-rw-r--r--drivers/clk/Makefile2
-rw-r--r--drivers/clk/clk-divider.c68
-rw-r--r--drivers/clk/clk-fixed-factor.c95
-rw-r--r--drivers/clk/clk-fixed-rate.c49
-rw-r--r--drivers/clk/clk-gate.c104
-rw-r--r--drivers/clk/clk-mux.c27
-rw-r--r--drivers/clk/clk.c270
-rw-r--r--include/linux/clk-private.h99
-rw-r--r--include/linux/clk-provider.h118
-rw-r--r--include/linux/clk.h6
12 files changed, 537 insertions, 323 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 1a2f8f5823e0..164e9a1df0f6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1882,6 +1882,16 @@ F: Documentation/filesystems/coda.txt
1882F: fs/coda/ 1882F: fs/coda/
1883F: include/linux/coda*.h 1883F: include/linux/coda*.h
1884 1884
1885COMMON CLK FRAMEWORK
1886M: Mike Turquette <mturquette@ti.com>
1887M: Mike Turquette <mturquette@linaro.org>
1888L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
1889T: git git://git.linaro.org/people/mturquette/linux.git
1890S: Maintained
1891F: drivers/clk/clk.c
1892F: drivers/clk/clk-*
1893F: include/linux/clk-pr*
1894
1885COMMON INTERNET FILE SYSTEM (CIFS) 1895COMMON INTERNET FILE SYSTEM (CIFS)
1886M: Steve French <sfrench@samba.org> 1896M: Steve French <sfrench@samba.org>
1887L: linux-cifs@vger.kernel.org 1897L: linux-cifs@vger.kernel.org
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 165e1febae53..4864407e3fc4 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -12,6 +12,7 @@ config HAVE_MACH_CLKDEV
12config COMMON_CLK 12config COMMON_CLK
13 bool 13 bool
14 select HAVE_CLK_PREPARE 14 select HAVE_CLK_PREPARE
15 select CLKDEV_LOOKUP
15 ---help--- 16 ---help---
16 The common clock framework is a single definition of struct 17 The common clock framework is a single definition of struct
17 clk, useful across many platforms, as well as an 18 clk, useful across many platforms, as well as an
@@ -22,17 +23,6 @@ config COMMON_CLK
22menu "Common Clock Framework" 23menu "Common Clock Framework"
23 depends on COMMON_CLK 24 depends on COMMON_CLK
24 25
25config COMMON_CLK_DISABLE_UNUSED
26 bool "Disabled unused clocks at boot"
27 depends on COMMON_CLK
28 ---help---
29 Traverses the entire clock tree and disables any clocks that are
30 enabled in hardware but have not been enabled by any device drivers.
31 This saves power and keeps the software model of the clock in line
32 with reality.
33
34 If in doubt, say "N".
35
36config COMMON_CLK_DEBUG 26config COMMON_CLK_DEBUG
37 bool "DebugFS representation of clock tree" 27 bool "DebugFS representation of clock tree"
38 depends on COMMON_CLK 28 depends on COMMON_CLK
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 1f736bc11c4b..24aa7144811b 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -1,4 +1,4 @@
1 1
2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o 2obj-$(CONFIG_CLKDEV_LOOKUP) += clkdev.o
3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \ 3obj-$(CONFIG_COMMON_CLK) += clk.o clk-fixed-rate.o clk-gate.o \
4 clk-mux.o clk-divider.o 4 clk-mux.o clk-divider.o clk-fixed-factor.o
diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index d5ac6a75ea57..8ea11b444528 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -45,7 +45,6 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
45 45
46 return parent_rate / div; 46 return parent_rate / div;
47} 47}
48EXPORT_SYMBOL_GPL(clk_divider_recalc_rate);
49 48
50/* 49/*
51 * The reverse of DIV_ROUND_UP: The maximum number which 50 * The reverse of DIV_ROUND_UP: The maximum number which
@@ -68,8 +67,8 @@ static int clk_divider_bestdiv(struct clk_hw *hw, unsigned long rate,
68 if (divider->flags & CLK_DIVIDER_ONE_BASED) 67 if (divider->flags & CLK_DIVIDER_ONE_BASED)
69 maxdiv--; 68 maxdiv--;
70 69
71 if (!best_parent_rate) { 70 if (!(__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT)) {
72 parent_rate = __clk_get_rate(__clk_get_parent(hw->clk)); 71 parent_rate = *best_parent_rate;
73 bestdiv = DIV_ROUND_UP(parent_rate, rate); 72 bestdiv = DIV_ROUND_UP(parent_rate, rate);
74 bestdiv = bestdiv == 0 ? 1 : bestdiv; 73 bestdiv = bestdiv == 0 ? 1 : bestdiv;
75 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv; 74 bestdiv = bestdiv > maxdiv ? maxdiv : bestdiv;
@@ -109,24 +108,18 @@ static long clk_divider_round_rate(struct clk_hw *hw, unsigned long rate,
109 int div; 108 int div;
110 div = clk_divider_bestdiv(hw, rate, prate); 109 div = clk_divider_bestdiv(hw, rate, prate);
111 110
112 if (prate) 111 return *prate / div;
113 return *prate / div;
114 else {
115 unsigned long r;
116 r = __clk_get_rate(__clk_get_parent(hw->clk));
117 return r / div;
118 }
119} 112}
120EXPORT_SYMBOL_GPL(clk_divider_round_rate);
121 113
122static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate) 114static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
115 unsigned long parent_rate)
123{ 116{
124 struct clk_divider *divider = to_clk_divider(hw); 117 struct clk_divider *divider = to_clk_divider(hw);
125 unsigned int div; 118 unsigned int div;
126 unsigned long flags = 0; 119 unsigned long flags = 0;
127 u32 val; 120 u32 val;
128 121
129 div = __clk_get_rate(__clk_get_parent(hw->clk)) / rate; 122 div = parent_rate / rate;
130 123
131 if (!(divider->flags & CLK_DIVIDER_ONE_BASED)) 124 if (!(divider->flags & CLK_DIVIDER_ONE_BASED))
132 div--; 125 div--;
@@ -147,15 +140,26 @@ static int clk_divider_set_rate(struct clk_hw *hw, unsigned long rate)
147 140
148 return 0; 141 return 0;
149} 142}
150EXPORT_SYMBOL_GPL(clk_divider_set_rate);
151 143
152struct clk_ops clk_divider_ops = { 144const struct clk_ops clk_divider_ops = {
153 .recalc_rate = clk_divider_recalc_rate, 145 .recalc_rate = clk_divider_recalc_rate,
154 .round_rate = clk_divider_round_rate, 146 .round_rate = clk_divider_round_rate,
155 .set_rate = clk_divider_set_rate, 147 .set_rate = clk_divider_set_rate,
156}; 148};
157EXPORT_SYMBOL_GPL(clk_divider_ops); 149EXPORT_SYMBOL_GPL(clk_divider_ops);
158 150
151/**
152 * clk_register_divider - register a divider clock with the clock framework
153 * @dev: device registering this clock
154 * @name: name of this clock
155 * @parent_name: name of clock's parent
156 * @flags: framework-specific flags
157 * @reg: register address to adjust divider
158 * @shift: number of bits to shift the bitfield
159 * @width: width of the bitfield
160 * @clk_divider_flags: divider-specific flags for this clock
161 * @lock: shared register lock for this clock
162 */
159struct clk *clk_register_divider(struct device *dev, const char *name, 163struct clk *clk_register_divider(struct device *dev, const char *name,
160 const char *parent_name, unsigned long flags, 164 const char *parent_name, unsigned long flags,
161 void __iomem *reg, u8 shift, u8 width, 165 void __iomem *reg, u8 shift, u8 width,
@@ -163,38 +167,34 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
163{ 167{
164 struct clk_divider *div; 168 struct clk_divider *div;
165 struct clk *clk; 169 struct clk *clk;
170 struct clk_init_data init;
166 171
172 /* allocate the divider */
167 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL); 173 div = kzalloc(sizeof(struct clk_divider), GFP_KERNEL);
168
169 if (!div) { 174 if (!div) {
170 pr_err("%s: could not allocate divider clk\n", __func__); 175 pr_err("%s: could not allocate divider clk\n", __func__);
171 return NULL; 176 return ERR_PTR(-ENOMEM);
172 } 177 }
173 178
179 init.name = name;
180 init.ops = &clk_divider_ops;
181 init.flags = flags;
182 init.parent_names = (parent_name ? &parent_name: NULL);
183 init.num_parents = (parent_name ? 1 : 0);
184
174 /* struct clk_divider assignments */ 185 /* struct clk_divider assignments */
175 div->reg = reg; 186 div->reg = reg;
176 div->shift = shift; 187 div->shift = shift;
177 div->width = width; 188 div->width = width;
178 div->flags = clk_divider_flags; 189 div->flags = clk_divider_flags;
179 div->lock = lock; 190 div->lock = lock;
191 div->hw.init = &init;
180 192
181 if (parent_name) { 193 /* register the clock */
182 div->parent[0] = kstrdup(parent_name, GFP_KERNEL); 194 clk = clk_register(dev, &div->hw);
183 if (!div->parent[0])
184 goto out;
185 }
186
187 clk = clk_register(dev, name,
188 &clk_divider_ops, &div->hw,
189 div->parent,
190 (parent_name ? 1 : 0),
191 flags);
192 if (clk)
193 return clk;
194 195
195out: 196 if (IS_ERR(clk))
196 kfree(div->parent[0]); 197 kfree(div);
197 kfree(div);
198 198
199 return NULL; 199 return clk;
200} 200}
diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
new file mode 100644
index 000000000000..c8c003e217ad
--- /dev/null
+++ b/drivers/clk/clk-fixed-factor.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright (C) 2011 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * Standard functionality for the common clock API.
9 */
10#include <linux/module.h>
11#include <linux/clk-provider.h>
12#include <linux/slab.h>
13#include <linux/err.h>
14
15/*
16 * DOC: basic fixed multiplier and divider clock that cannot gate
17 *
18 * Traits of this clock:
19 * prepare - clk_prepare only ensures that parents are prepared
20 * enable - clk_enable only ensures that parents are enabled
21 * rate - rate is fixed. clk->rate = parent->rate / div * mult
22 * parent - fixed parent. No clk_set_parent support
23 */
24
25#define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw)
26
27static unsigned long clk_factor_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
31
32 return parent_rate * fix->mult / fix->div;
33}
34
35static long clk_factor_round_rate(struct clk_hw *hw, unsigned long rate,
36 unsigned long *prate)
37{
38 struct clk_fixed_factor *fix = to_clk_fixed_factor(hw);
39
40 if (__clk_get_flags(hw->clk) & CLK_SET_RATE_PARENT) {
41 unsigned long best_parent;
42
43 best_parent = (rate / fix->mult) * fix->div;
44 *prate = __clk_round_rate(__clk_get_parent(hw->clk),
45 best_parent);
46 }
47
48 return (*prate / fix->div) * fix->mult;
49}
50
51static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate,
52 unsigned long parent_rate)
53{
54 return 0;
55}
56
57struct clk_ops clk_fixed_factor_ops = {
58 .round_rate = clk_factor_round_rate,
59 .set_rate = clk_factor_set_rate,
60 .recalc_rate = clk_factor_recalc_rate,
61};
62EXPORT_SYMBOL_GPL(clk_fixed_factor_ops);
63
64struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
65 const char *parent_name, unsigned long flags,
66 unsigned int mult, unsigned int div)
67{
68 struct clk_fixed_factor *fix;
69 struct clk_init_data init;
70 struct clk *clk;
71
72 fix = kmalloc(sizeof(*fix), GFP_KERNEL);
73 if (!fix) {
74 pr_err("%s: could not allocate fixed factor clk\n", __func__);
75 return ERR_PTR(-ENOMEM);
76 }
77
78 /* struct clk_fixed_factor assignments */
79 fix->mult = mult;
80 fix->div = div;
81 fix->hw.init = &init;
82
83 init.name = name;
84 init.ops = &clk_fixed_factor_ops;
85 init.flags = flags;
86 init.parent_names = &parent_name;
87 init.num_parents = 1;
88
89 clk = clk_register(dev, &fix->hw);
90
91 if (IS_ERR(clk))
92 kfree(fix);
93
94 return clk;
95}
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index 90c79fb5d1bd..cbd246229786 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -32,51 +32,50 @@ static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
32{ 32{
33 return to_clk_fixed_rate(hw)->fixed_rate; 33 return to_clk_fixed_rate(hw)->fixed_rate;
34} 34}
35EXPORT_SYMBOL_GPL(clk_fixed_rate_recalc_rate);
36 35
37struct clk_ops clk_fixed_rate_ops = { 36const struct clk_ops clk_fixed_rate_ops = {
38 .recalc_rate = clk_fixed_rate_recalc_rate, 37 .recalc_rate = clk_fixed_rate_recalc_rate,
39}; 38};
40EXPORT_SYMBOL_GPL(clk_fixed_rate_ops); 39EXPORT_SYMBOL_GPL(clk_fixed_rate_ops);
41 40
41/**
42 * clk_register_fixed_rate - register fixed-rate clock with the clock framework
43 * @dev: device that is registering this clock
44 * @name: name of this clock
45 * @parent_name: name of clock's parent
46 * @flags: framework-specific flags
47 * @fixed_rate: non-adjustable clock rate
48 */
42struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 49struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
43 const char *parent_name, unsigned long flags, 50 const char *parent_name, unsigned long flags,
44 unsigned long fixed_rate) 51 unsigned long fixed_rate)
45{ 52{
46 struct clk_fixed_rate *fixed; 53 struct clk_fixed_rate *fixed;
47 char **parent_names = NULL; 54 struct clk *clk;
48 u8 len; 55 struct clk_init_data init;
49 56
57 /* allocate fixed-rate clock */
50 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL); 58 fixed = kzalloc(sizeof(struct clk_fixed_rate), GFP_KERNEL);
51
52 if (!fixed) { 59 if (!fixed) {
53 pr_err("%s: could not allocate fixed clk\n", __func__); 60 pr_err("%s: could not allocate fixed clk\n", __func__);
54 return ERR_PTR(-ENOMEM); 61 return ERR_PTR(-ENOMEM);
55 } 62 }
56 63
64 init.name = name;
65 init.ops = &clk_fixed_rate_ops;
66 init.flags = flags;
67 init.parent_names = (parent_name ? &parent_name: NULL);
68 init.num_parents = (parent_name ? 1 : 0);
69
57 /* struct clk_fixed_rate assignments */ 70 /* struct clk_fixed_rate assignments */
58 fixed->fixed_rate = fixed_rate; 71 fixed->fixed_rate = fixed_rate;
72 fixed->hw.init = &init;
59 73
60 if (parent_name) { 74 /* register the clock */
61 parent_names = kmalloc(sizeof(char *), GFP_KERNEL); 75 clk = clk_register(dev, &fixed->hw);
62
63 if (! parent_names)
64 goto out;
65 76
66 len = sizeof(char) * strlen(parent_name); 77 if (IS_ERR(clk))
67 78 kfree(fixed);
68 parent_names[0] = kmalloc(len, GFP_KERNEL);
69
70 if (!parent_names[0])
71 goto out;
72
73 strncpy(parent_names[0], parent_name, len);
74 }
75 79
76out: 80 return clk;
77 return clk_register(dev, name,
78 &clk_fixed_rate_ops, &fixed->hw,
79 parent_names,
80 (parent_name ? 1 : 0),
81 flags);
82} 81}
diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index b5902e2ef2fd..578465e04be6 100644
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,32 +28,38 @@
28 28
29#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw) 29#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
30 30
31static void clk_gate_set_bit(struct clk_gate *gate) 31/*
32 * It works on following logic:
33 *
34 * For enabling clock, enable = 1
35 * set2dis = 1 -> clear bit -> set = 0
36 * set2dis = 0 -> set bit -> set = 1
37 *
38 * For disabling clock, enable = 0
39 * set2dis = 1 -> set bit -> set = 1
40 * set2dis = 0 -> clear bit -> set = 0
41 *
42 * So, result is always: enable xor set2dis.
43 */
44static void clk_gate_endisable(struct clk_hw *hw, int enable)
32{ 45{
33 u32 reg; 46 struct clk_gate *gate = to_clk_gate(hw);
47 int set = gate->flags & CLK_GATE_SET_TO_DISABLE ? 1 : 0;
34 unsigned long flags = 0; 48 unsigned long flags = 0;
49 u32 reg;
50
51 set ^= enable;
35 52
36 if (gate->lock) 53 if (gate->lock)
37 spin_lock_irqsave(gate->lock, flags); 54 spin_lock_irqsave(gate->lock, flags);
38 55
39 reg = readl(gate->reg); 56 reg = readl(gate->reg);
40 reg |= BIT(gate->bit_idx);
41 writel(reg, gate->reg);
42
43 if (gate->lock)
44 spin_unlock_irqrestore(gate->lock, flags);
45}
46
47static void clk_gate_clear_bit(struct clk_gate *gate)
48{
49 u32 reg;
50 unsigned long flags = 0;
51 57
52 if (gate->lock) 58 if (set)
53 spin_lock_irqsave(gate->lock, flags); 59 reg |= BIT(gate->bit_idx);
60 else
61 reg &= ~BIT(gate->bit_idx);
54 62
55 reg = readl(gate->reg);
56 reg &= ~BIT(gate->bit_idx);
57 writel(reg, gate->reg); 63 writel(reg, gate->reg);
58 64
59 if (gate->lock) 65 if (gate->lock)
@@ -62,27 +68,15 @@ static void clk_gate_clear_bit(struct clk_gate *gate)
62 68
63static int clk_gate_enable(struct clk_hw *hw) 69static int clk_gate_enable(struct clk_hw *hw)
64{ 70{
65 struct clk_gate *gate = to_clk_gate(hw); 71 clk_gate_endisable(hw, 1);
66
67 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
68 clk_gate_clear_bit(gate);
69 else
70 clk_gate_set_bit(gate);
71 72
72 return 0; 73 return 0;
73} 74}
74EXPORT_SYMBOL_GPL(clk_gate_enable);
75 75
76static void clk_gate_disable(struct clk_hw *hw) 76static void clk_gate_disable(struct clk_hw *hw)
77{ 77{
78 struct clk_gate *gate = to_clk_gate(hw); 78 clk_gate_endisable(hw, 0);
79
80 if (gate->flags & CLK_GATE_SET_TO_DISABLE)
81 clk_gate_set_bit(gate);
82 else
83 clk_gate_clear_bit(gate);
84} 79}
85EXPORT_SYMBOL_GPL(clk_gate_disable);
86 80
87static int clk_gate_is_enabled(struct clk_hw *hw) 81static int clk_gate_is_enabled(struct clk_hw *hw)
88{ 82{
@@ -99,15 +93,25 @@ static int clk_gate_is_enabled(struct clk_hw *hw)
99 93
100 return reg ? 1 : 0; 94 return reg ? 1 : 0;
101} 95}
102EXPORT_SYMBOL_GPL(clk_gate_is_enabled);
103 96
104struct clk_ops clk_gate_ops = { 97const struct clk_ops clk_gate_ops = {
105 .enable = clk_gate_enable, 98 .enable = clk_gate_enable,
106 .disable = clk_gate_disable, 99 .disable = clk_gate_disable,
107 .is_enabled = clk_gate_is_enabled, 100 .is_enabled = clk_gate_is_enabled,
108}; 101};
109EXPORT_SYMBOL_GPL(clk_gate_ops); 102EXPORT_SYMBOL_GPL(clk_gate_ops);
110 103
104/**
105 * clk_register_gate - register a gate clock with the clock framework
106 * @dev: device that is registering this clock
107 * @name: name of this clock
108 * @parent_name: name of this clock's parent
109 * @flags: framework-specific flags for this clock
110 * @reg: register address to control gating of this clock
111 * @bit_idx: which bit in the register controls gating of this clock
112 * @clk_gate_flags: gate-specific flags for this clock
113 * @lock: shared register lock for this clock
114 */
111struct clk *clk_register_gate(struct device *dev, const char *name, 115struct clk *clk_register_gate(struct device *dev, const char *name,
112 const char *parent_name, unsigned long flags, 116 const char *parent_name, unsigned long flags,
113 void __iomem *reg, u8 bit_idx, 117 void __iomem *reg, u8 bit_idx,
@@ -115,36 +119,32 @@ struct clk *clk_register_gate(struct device *dev, const char *name,
115{ 119{
116 struct clk_gate *gate; 120 struct clk_gate *gate;
117 struct clk *clk; 121 struct clk *clk;
122 struct clk_init_data init;
118 123
124 /* allocate the gate */
119 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL); 125 gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
120
121 if (!gate) { 126 if (!gate) {
122 pr_err("%s: could not allocate gated clk\n", __func__); 127 pr_err("%s: could not allocate gated clk\n", __func__);
123 return NULL; 128 return ERR_PTR(-ENOMEM);
124 } 129 }
125 130
131 init.name = name;
132 init.ops = &clk_gate_ops;
133 init.flags = flags;
134 init.parent_names = (parent_name ? &parent_name: NULL);
135 init.num_parents = (parent_name ? 1 : 0);
136
126 /* struct clk_gate assignments */ 137 /* struct clk_gate assignments */
127 gate->reg = reg; 138 gate->reg = reg;
128 gate->bit_idx = bit_idx; 139 gate->bit_idx = bit_idx;
129 gate->flags = clk_gate_flags; 140 gate->flags = clk_gate_flags;
130 gate->lock = lock; 141 gate->lock = lock;
142 gate->hw.init = &init;
131 143
132 if (parent_name) { 144 clk = clk_register(dev, &gate->hw);
133 gate->parent[0] = kstrdup(parent_name, GFP_KERNEL); 145
134 if (!gate->parent[0]) 146 if (IS_ERR(clk))
135 goto out; 147 kfree(gate);
136 }
137 148
138 clk = clk_register(dev, name, 149 return clk;
139 &clk_gate_ops, &gate->hw,
140 gate->parent,
141 (parent_name ? 1 : 0),
142 flags);
143 if (clk)
144 return clk;
145out:
146 kfree(gate->parent[0]);
147 kfree(gate);
148
149 return NULL;
150} 150}
diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index c71ad1f41a97..fd36a8ea73d9 100644
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -55,7 +55,6 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
55 55
56 return val; 56 return val;
57} 57}
58EXPORT_SYMBOL_GPL(clk_mux_get_parent);
59 58
60static int clk_mux_set_parent(struct clk_hw *hw, u8 index) 59static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
61{ 60{
@@ -82,35 +81,47 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
82 81
83 return 0; 82 return 0;
84} 83}
85EXPORT_SYMBOL_GPL(clk_mux_set_parent);
86 84
87struct clk_ops clk_mux_ops = { 85const struct clk_ops clk_mux_ops = {
88 .get_parent = clk_mux_get_parent, 86 .get_parent = clk_mux_get_parent,
89 .set_parent = clk_mux_set_parent, 87 .set_parent = clk_mux_set_parent,
90}; 88};
91EXPORT_SYMBOL_GPL(clk_mux_ops); 89EXPORT_SYMBOL_GPL(clk_mux_ops);
92 90
93struct clk *clk_register_mux(struct device *dev, const char *name, 91struct clk *clk_register_mux(struct device *dev, const char *name,
94 char **parent_names, u8 num_parents, unsigned long flags, 92 const char **parent_names, u8 num_parents, unsigned long flags,
95 void __iomem *reg, u8 shift, u8 width, 93 void __iomem *reg, u8 shift, u8 width,
96 u8 clk_mux_flags, spinlock_t *lock) 94 u8 clk_mux_flags, spinlock_t *lock)
97{ 95{
98 struct clk_mux *mux; 96 struct clk_mux *mux;
97 struct clk *clk;
98 struct clk_init_data init;
99 99
100 mux = kmalloc(sizeof(struct clk_mux), GFP_KERNEL); 100 /* allocate the mux */
101 101 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
102 if (!mux) { 102 if (!mux) {
103 pr_err("%s: could not allocate mux clk\n", __func__); 103 pr_err("%s: could not allocate mux clk\n", __func__);
104 return ERR_PTR(-ENOMEM); 104 return ERR_PTR(-ENOMEM);
105 } 105 }
106 106
107 init.name = name;
108 init.ops = &clk_mux_ops;
109 init.flags = flags;
110 init.parent_names = parent_names;
111 init.num_parents = num_parents;
112
107 /* struct clk_mux assignments */ 113 /* struct clk_mux assignments */
108 mux->reg = reg; 114 mux->reg = reg;
109 mux->shift = shift; 115 mux->shift = shift;
110 mux->width = width; 116 mux->width = width;
111 mux->flags = clk_mux_flags; 117 mux->flags = clk_mux_flags;
112 mux->lock = lock; 118 mux->lock = lock;
119 mux->hw.init = &init;
120
121 clk = clk_register(dev, &mux->hw);
122
123 if (IS_ERR(clk))
124 kfree(mux);
113 125
114 return clk_register(dev, name, &clk_mux_ops, &mux->hw, 126 return clk;
115 parent_names, num_parents, flags);
116} 127}
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 9cf6f59e3e19..e5d5dc13bcfd 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -194,9 +194,8 @@ static int __init clk_debug_init(void)
194late_initcall(clk_debug_init); 194late_initcall(clk_debug_init);
195#else 195#else
196static inline int clk_debug_register(struct clk *clk) { return 0; } 196static inline int clk_debug_register(struct clk *clk) { return 0; }
197#endif /* CONFIG_COMMON_CLK_DEBUG */ 197#endif
198 198
199#ifdef CONFIG_COMMON_CLK_DISABLE_UNUSED
200/* caller must hold prepare_lock */ 199/* caller must hold prepare_lock */
201static void clk_disable_unused_subtree(struct clk *clk) 200static void clk_disable_unused_subtree(struct clk *clk)
202{ 201{
@@ -246,9 +245,6 @@ static int clk_disable_unused(void)
246 return 0; 245 return 0;
247} 246}
248late_initcall(clk_disable_unused); 247late_initcall(clk_disable_unused);
249#else
250static inline int clk_disable_unused(struct clk *clk) { return 0; }
251#endif /* CONFIG_COMMON_CLK_DISABLE_UNUSED */
252 248
253/*** helper functions ***/ 249/*** helper functions ***/
254 250
@@ -287,7 +283,7 @@ unsigned long __clk_get_rate(struct clk *clk)
287 unsigned long ret; 283 unsigned long ret;
288 284
289 if (!clk) { 285 if (!clk) {
290 ret = -EINVAL; 286 ret = 0;
291 goto out; 287 goto out;
292 } 288 }
293 289
@@ -297,7 +293,7 @@ unsigned long __clk_get_rate(struct clk *clk)
297 goto out; 293 goto out;
298 294
299 if (!clk->parent) 295 if (!clk->parent)
300 ret = -ENODEV; 296 ret = 0;
301 297
302out: 298out:
303 return ret; 299 return ret;
@@ -562,7 +558,7 @@ EXPORT_SYMBOL_GPL(clk_enable);
562 * @clk: the clk whose rate is being returned 558 * @clk: the clk whose rate is being returned
563 * 559 *
564 * Simply returns the cached rate of the clk. Does not query the hardware. If 560 * Simply returns the cached rate of the clk. Does not query the hardware. If
565 * clk is NULL then returns -EINVAL. 561 * clk is NULL then returns 0.
566 */ 562 */
567unsigned long clk_get_rate(struct clk *clk) 563unsigned long clk_get_rate(struct clk *clk)
568{ 564{
@@ -584,18 +580,22 @@ EXPORT_SYMBOL_GPL(clk_get_rate);
584 */ 580 */
585unsigned long __clk_round_rate(struct clk *clk, unsigned long rate) 581unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
586{ 582{
587 unsigned long unused; 583 unsigned long parent_rate = 0;
588 584
589 if (!clk) 585 if (!clk)
590 return -EINVAL; 586 return -EINVAL;
591 587
592 if (!clk->ops->round_rate) 588 if (!clk->ops->round_rate) {
593 return clk->rate; 589 if (clk->flags & CLK_SET_RATE_PARENT)
590 return __clk_round_rate(clk->parent, rate);
591 else
592 return clk->rate;
593 }
594 594
595 if (clk->flags & CLK_SET_RATE_PARENT) 595 if (clk->parent)
596 return clk->ops->round_rate(clk->hw, rate, &unused); 596 parent_rate = clk->parent->rate;
597 else 597
598 return clk->ops->round_rate(clk->hw, rate, NULL); 598 return clk->ops->round_rate(clk->hw, rate, &parent_rate);
599} 599}
600 600
601/** 601/**
@@ -765,25 +765,41 @@ static void clk_calc_subtree(struct clk *clk, unsigned long new_rate)
765static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate) 765static struct clk *clk_calc_new_rates(struct clk *clk, unsigned long rate)
766{ 766{
767 struct clk *top = clk; 767 struct clk *top = clk;
768 unsigned long best_parent_rate = clk->parent->rate; 768 unsigned long best_parent_rate = 0;
769 unsigned long new_rate; 769 unsigned long new_rate;
770 770
771 if (!clk->ops->round_rate && !(clk->flags & CLK_SET_RATE_PARENT)) { 771 /* sanity */
772 clk->new_rate = clk->rate; 772 if (IS_ERR_OR_NULL(clk))
773 return NULL; 773 return NULL;
774
775 /* save parent rate, if it exists */
776 if (clk->parent)
777 best_parent_rate = clk->parent->rate;
778
779 /* never propagate up to the parent */
780 if (!(clk->flags & CLK_SET_RATE_PARENT)) {
781 if (!clk->ops->round_rate) {
782 clk->new_rate = clk->rate;
783 return NULL;
784 }
785 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
786 goto out;
774 } 787 }
775 788
776 if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) { 789 /* need clk->parent from here on out */
790 if (!clk->parent) {
791 pr_debug("%s: %s has NULL parent\n", __func__, clk->name);
792 return NULL;
793 }
794
795 if (!clk->ops->round_rate) {
777 top = clk_calc_new_rates(clk->parent, rate); 796 top = clk_calc_new_rates(clk->parent, rate);
778 new_rate = clk->new_rate = clk->parent->new_rate; 797 new_rate = clk->parent->new_rate;
779 798
780 goto out; 799 goto out;
781 } 800 }
782 801
783 if (clk->flags & CLK_SET_RATE_PARENT) 802 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
784 new_rate = clk->ops->round_rate(clk->hw, rate, &best_parent_rate);
785 else
786 new_rate = clk->ops->round_rate(clk->hw, rate, NULL);
787 803
788 if (best_parent_rate != clk->parent->rate) { 804 if (best_parent_rate != clk->parent->rate) {
789 top = clk_calc_new_rates(clk->parent, best_parent_rate); 805 top = clk_calc_new_rates(clk->parent, best_parent_rate);
@@ -839,7 +855,7 @@ static void clk_change_rate(struct clk *clk)
839 old_rate = clk->rate; 855 old_rate = clk->rate;
840 856
841 if (clk->ops->set_rate) 857 if (clk->ops->set_rate)
842 clk->ops->set_rate(clk->hw, clk->new_rate); 858 clk->ops->set_rate(clk->hw, clk->new_rate, clk->parent->rate);
843 859
844 if (clk->ops->recalc_rate) 860 if (clk->ops->recalc_rate)
845 clk->rate = clk->ops->recalc_rate(clk->hw, 861 clk->rate = clk->ops->recalc_rate(clk->hw,
@@ -859,38 +875,19 @@ static void clk_change_rate(struct clk *clk)
859 * @clk: the clk whose rate is being changed 875 * @clk: the clk whose rate is being changed
860 * @rate: the new rate for clk 876 * @rate: the new rate for clk
861 * 877 *
862 * In the simplest case clk_set_rate will only change the rate of clk. 878 * In the simplest case clk_set_rate will only adjust the rate of clk.
863 * 879 *
864 * If clk has the CLK_SET_RATE_GATE flag set and it is enabled this call 880 * Setting the CLK_SET_RATE_PARENT flag allows the rate change operation to
865 * will fail; only when the clk is disabled will it be able to change 881 * propagate up to clk's parent; whether or not this happens depends on the
866 * its rate. 882 * outcome of clk's .round_rate implementation. If *parent_rate is unchanged
883 * after calling .round_rate then upstream parent propagation is ignored. If
884 * *parent_rate comes back with a new rate for clk's parent then we propagate
885 * up to clk's parent and set it's rate. Upward propagation will continue
886 * until either a clk does not support the CLK_SET_RATE_PARENT flag or
887 * .round_rate stops requesting changes to clk's parent_rate.
867 * 888 *
868 * Setting the CLK_SET_RATE_PARENT flag allows clk_set_rate to 889 * Rate changes are accomplished via tree traversal that also recalculates the
869 * recursively propagate up to clk's parent; whether or not this happens 890 * rates for the clocks and fires off POST_RATE_CHANGE notifiers.
870 * depends on the outcome of clk's .round_rate implementation. If
871 * *parent_rate is 0 after calling .round_rate then upstream parent
872 * propagation is ignored. If *parent_rate comes back with a new rate
873 * for clk's parent then we propagate up to clk's parent and set it's
874 * rate. Upward propagation will continue until either a clk does not
875 * support the CLK_SET_RATE_PARENT flag or .round_rate stops requesting
876 * changes to clk's parent_rate. If there is a failure during upstream
877 * propagation then clk_set_rate will unwind and restore each clk's rate
878 * that had been successfully changed. Afterwards a rate change abort
879 * notification will be propagated downstream, starting from the clk
880 * that failed.
881 *
882 * At the end of all of the rate setting, clk_set_rate internally calls
883 * __clk_recalc_rates and propagates the rate changes downstream,
884 * starting from the highest clk whose rate was changed. This has the
885 * added benefit of propagating post-rate change notifiers.
886 *
887 * Note that while post-rate change and rate change abort notifications
888 * are guaranteed to be sent to a clk only once per call to
889 * clk_set_rate, pre-change notifications will be sent for every clk
890 * whose rate is changed. Stacking pre-change notifications is noisy
891 * for the drivers subscribed to them, but this allows drivers to react
892 * to intermediate clk rate changes up until the point where the final
893 * rate is achieved at the end of upstream propagation.
894 * 891 *
895 * Returns 0 on success, -EERROR otherwise. 892 * Returns 0 on success, -EERROR otherwise.
896 */ 893 */
@@ -906,6 +903,11 @@ int clk_set_rate(struct clk *clk, unsigned long rate)
906 if (rate == clk->rate) 903 if (rate == clk->rate)
907 goto out; 904 goto out;
908 905
906 if ((clk->flags & CLK_SET_RATE_GATE) && __clk_is_enabled(clk)) {
907 ret = -EBUSY;
908 goto out;
909 }
910
909 /* calculate new rates and get the topmost changed clock */ 911 /* calculate new rates and get the topmost changed clock */
910 top = clk_calc_new_rates(clk, rate); 912 top = clk_calc_new_rates(clk, rate);
911 if (!top) { 913 if (!top) {
@@ -1175,40 +1177,41 @@ EXPORT_SYMBOL_GPL(clk_set_parent);
1175 * 1177 *
1176 * Initializes the lists in struct clk, queries the hardware for the 1178 * Initializes the lists in struct clk, queries the hardware for the
1177 * parent and rate and sets them both. 1179 * parent and rate and sets them both.
1178 *
1179 * Any struct clk passed into __clk_init must have the following members
1180 * populated:
1181 * .name
1182 * .ops
1183 * .hw
1184 * .parent_names
1185 * .num_parents
1186 * .flags
1187 *
1188 * Essentially, everything that would normally be passed into clk_register is
1189 * assumed to be initialized already in __clk_init. The other members may be
1190 * populated, but are optional.
1191 *
1192 * __clk_init is only exposed via clk-private.h and is intended for use with
1193 * very large numbers of clocks that need to be statically initialized. It is
1194 * a layering violation to include clk-private.h from any code which implements
1195 * a clock's .ops; as such any statically initialized clock data MUST be in a
1196 * separate C file from the logic that implements it's operations.
1197 */ 1180 */
1198void __clk_init(struct device *dev, struct clk *clk) 1181int __clk_init(struct device *dev, struct clk *clk)
1199{ 1182{
1200 int i; 1183 int i, ret = 0;
1201 struct clk *orphan; 1184 struct clk *orphan;
1202 struct hlist_node *tmp, *tmp2; 1185 struct hlist_node *tmp, *tmp2;
1203 1186
1204 if (!clk) 1187 if (!clk)
1205 return; 1188 return -EINVAL;
1206 1189
1207 mutex_lock(&prepare_lock); 1190 mutex_lock(&prepare_lock);
1208 1191
1209 /* check to see if a clock with this name is already registered */ 1192 /* check to see if a clock with this name is already registered */
1210 if (__clk_lookup(clk->name)) 1193 if (__clk_lookup(clk->name)) {
1194 pr_debug("%s: clk %s already initialized\n",
1195 __func__, clk->name);
1196 ret = -EEXIST;
1197 goto out;
1198 }
1199
1200 /* check that clk_ops are sane. See Documentation/clk.txt */
1201 if (clk->ops->set_rate &&
1202 !(clk->ops->round_rate && clk->ops->recalc_rate)) {
1203 pr_warning("%s: %s must implement .round_rate & .recalc_rate\n",
1204 __func__, clk->name);
1205 ret = -EINVAL;
1211 goto out; 1206 goto out;
1207 }
1208
1209 if (clk->ops->set_parent && !clk->ops->get_parent) {
1210 pr_warning("%s: %s must implement .get_parent & .set_parent\n",
1211 __func__, clk->name);
1212 ret = -EINVAL;
1213 goto out;
1214 }
1212 1215
1213 /* throw a WARN if any entries in parent_names are NULL */ 1216 /* throw a WARN if any entries in parent_names are NULL */
1214 for (i = 0; i < clk->num_parents; i++) 1217 for (i = 0; i < clk->num_parents; i++)
@@ -1302,45 +1305,118 @@ void __clk_init(struct device *dev, struct clk *clk)
1302out: 1305out:
1303 mutex_unlock(&prepare_lock); 1306 mutex_unlock(&prepare_lock);
1304 1307
1305 return; 1308 return ret;
1306} 1309}
1307 1310
1308/** 1311/**
1312 * __clk_register - register a clock and return a cookie.
1313 *
1314 * Same as clk_register, except that the .clk field inside hw shall point to a
1315 * preallocated (generally statically allocated) struct clk. None of the fields
1316 * of the struct clk need to be initialized.
1317 *
1318 * The data pointed to by .init and .clk field shall NOT be marked as init
1319 * data.
1320 *
1321 * __clk_register is only exposed via clk-private.h and is intended for use with
1322 * very large numbers of clocks that need to be statically initialized. It is
1323 * a layering violation to include clk-private.h from any code which implements
1324 * a clock's .ops; as such any statically initialized clock data MUST be in a
1325 * separate C file from the logic that implements it's operations. Returns 0
1326 * on success, otherwise an error code.
1327 */
1328struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
1329{
1330 int ret;
1331 struct clk *clk;
1332
1333 clk = hw->clk;
1334 clk->name = hw->init->name;
1335 clk->ops = hw->init->ops;
1336 clk->hw = hw;
1337 clk->flags = hw->init->flags;
1338 clk->parent_names = hw->init->parent_names;
1339 clk->num_parents = hw->init->num_parents;
1340
1341 ret = __clk_init(dev, clk);
1342 if (ret)
1343 return ERR_PTR(ret);
1344
1345 return clk;
1346}
1347EXPORT_SYMBOL_GPL(__clk_register);
1348
1349/**
1309 * clk_register - allocate a new clock, register it and return an opaque cookie 1350 * clk_register - allocate a new clock, register it and return an opaque cookie
1310 * @dev: device that is registering this clock 1351 * @dev: device that is registering this clock
1311 * @name: clock name
1312 * @ops: operations this clock supports
1313 * @hw: link to hardware-specific clock data 1352 * @hw: link to hardware-specific clock data
1314 * @parent_names: array of string names for all possible parents
1315 * @num_parents: number of possible parents
1316 * @flags: framework-level hints and quirks
1317 * 1353 *
1318 * clk_register is the primary interface for populating the clock tree with new 1354 * clk_register is the primary interface for populating the clock tree with new
1319 * clock nodes. It returns a pointer to the newly allocated struct clk which 1355 * clock nodes. It returns a pointer to the newly allocated struct clk which
1320 * cannot be dereferenced by driver code but may be used in conjuction with the 1356 * cannot be dereferenced by driver code but may be used in conjuction with the
1321 * rest of the clock API. 1357 * rest of the clock API. In the event of an error clk_register will return an
1358 * error code; drivers must test for an error code after calling clk_register.
1322 */ 1359 */
1323struct clk *clk_register(struct device *dev, const char *name, 1360struct clk *clk_register(struct device *dev, struct clk_hw *hw)
1324 const struct clk_ops *ops, struct clk_hw *hw,
1325 char **parent_names, u8 num_parents, unsigned long flags)
1326{ 1361{
1362 int i, ret;
1327 struct clk *clk; 1363 struct clk *clk;
1328 1364
1329 clk = kzalloc(sizeof(*clk), GFP_KERNEL); 1365 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
1330 if (!clk) 1366 if (!clk) {
1331 return NULL; 1367 pr_err("%s: could not allocate clk\n", __func__);
1368 ret = -ENOMEM;
1369 goto fail_out;
1370 }
1332 1371
1333 clk->name = name; 1372 clk->name = kstrdup(hw->init->name, GFP_KERNEL);
1334 clk->ops = ops; 1373 if (!clk->name) {
1374 pr_err("%s: could not allocate clk->name\n", __func__);
1375 ret = -ENOMEM;
1376 goto fail_name;
1377 }
1378 clk->ops = hw->init->ops;
1335 clk->hw = hw; 1379 clk->hw = hw;
1336 clk->flags = flags; 1380 clk->flags = hw->init->flags;
1337 clk->parent_names = parent_names; 1381 clk->num_parents = hw->init->num_parents;
1338 clk->num_parents = num_parents;
1339 hw->clk = clk; 1382 hw->clk = clk;
1340 1383
1341 __clk_init(dev, clk); 1384 /* allocate local copy in case parent_names is __initdata */
1385 clk->parent_names = kzalloc((sizeof(char*) * clk->num_parents),
1386 GFP_KERNEL);
1342 1387
1343 return clk; 1388 if (!clk->parent_names) {
1389 pr_err("%s: could not allocate clk->parent_names\n", __func__);
1390 ret = -ENOMEM;
1391 goto fail_parent_names;
1392 }
1393
1394
1395 /* copy each string name in case parent_names is __initdata */
1396 for (i = 0; i < clk->num_parents; i++) {
1397 clk->parent_names[i] = kstrdup(hw->init->parent_names[i],
1398 GFP_KERNEL);
1399 if (!clk->parent_names[i]) {
1400 pr_err("%s: could not copy parent_names\n", __func__);
1401 ret = -ENOMEM;
1402 goto fail_parent_names_copy;
1403 }
1404 }
1405
1406 ret = __clk_init(dev, clk);
1407 if (!ret)
1408 return clk;
1409
1410fail_parent_names_copy:
1411 while (--i >= 0)
1412 kfree(clk->parent_names[i]);
1413 kfree(clk->parent_names);
1414fail_parent_names:
1415 kfree(clk->name);
1416fail_name:
1417 kfree(clk);
1418fail_out:
1419 return ERR_PTR(ret);
1344} 1420}
1345EXPORT_SYMBOL_GPL(clk_register); 1421EXPORT_SYMBOL_GPL(clk_register);
1346 1422
diff --git a/include/linux/clk-private.h b/include/linux/clk-private.h
index 5e4312b6f5cc..eb3f84bc5325 100644
--- a/include/linux/clk-private.h
+++ b/include/linux/clk-private.h
@@ -30,7 +30,7 @@ struct clk {
30 const struct clk_ops *ops; 30 const struct clk_ops *ops;
31 struct clk_hw *hw; 31 struct clk_hw *hw;
32 struct clk *parent; 32 struct clk *parent;
33 char **parent_names; 33 const char **parent_names;
34 struct clk **parents; 34 struct clk **parents;
35 u8 num_parents; 35 u8 num_parents;
36 unsigned long rate; 36 unsigned long rate;
@@ -55,12 +55,22 @@ struct clk {
55 * alternative macro for static initialization 55 * alternative macro for static initialization
56 */ 56 */
57 57
58extern struct clk_ops clk_fixed_rate_ops; 58#define DEFINE_CLK(_name, _ops, _flags, _parent_names, \
59 _parents) \
60 static struct clk _name = { \
61 .name = #_name, \
62 .ops = &_ops, \
63 .hw = &_name##_hw.hw, \
64 .parent_names = _parent_names, \
65 .num_parents = ARRAY_SIZE(_parent_names), \
66 .parents = _parents, \
67 .flags = _flags, \
68 }
59 69
60#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \ 70#define DEFINE_CLK_FIXED_RATE(_name, _flags, _rate, \
61 _fixed_rate_flags) \ 71 _fixed_rate_flags) \
62 static struct clk _name; \ 72 static struct clk _name; \
63 static char *_name##_parent_names[] = {}; \ 73 static const char *_name##_parent_names[] = {}; \
64 static struct clk_fixed_rate _name##_hw = { \ 74 static struct clk_fixed_rate _name##_hw = { \
65 .hw = { \ 75 .hw = { \
66 .clk = &_name, \ 76 .clk = &_name, \
@@ -68,23 +78,14 @@ extern struct clk_ops clk_fixed_rate_ops;
68 .fixed_rate = _rate, \ 78 .fixed_rate = _rate, \
69 .flags = _fixed_rate_flags, \ 79 .flags = _fixed_rate_flags, \
70 }; \ 80 }; \
71 static struct clk _name = { \ 81 DEFINE_CLK(_name, clk_fixed_rate_ops, _flags, \
72 .name = #_name, \ 82 _name##_parent_names, NULL);
73 .ops = &clk_fixed_rate_ops, \
74 .hw = &_name##_hw.hw, \
75 .parent_names = _name##_parent_names, \
76 .num_parents = \
77 ARRAY_SIZE(_name##_parent_names), \
78 .flags = _flags, \
79 };
80
81extern struct clk_ops clk_gate_ops;
82 83
83#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \ 84#define DEFINE_CLK_GATE(_name, _parent_name, _parent_ptr, \
84 _flags, _reg, _bit_idx, \ 85 _flags, _reg, _bit_idx, \
85 _gate_flags, _lock) \ 86 _gate_flags, _lock) \
86 static struct clk _name; \ 87 static struct clk _name; \
87 static char *_name##_parent_names[] = { \ 88 static const char *_name##_parent_names[] = { \
88 _parent_name, \ 89 _parent_name, \
89 }; \ 90 }; \
90 static struct clk *_name##_parents[] = { \ 91 static struct clk *_name##_parents[] = { \
@@ -99,24 +100,14 @@ extern struct clk_ops clk_gate_ops;
99 .flags = _gate_flags, \ 100 .flags = _gate_flags, \
100 .lock = _lock, \ 101 .lock = _lock, \
101 }; \ 102 }; \
102 static struct clk _name = { \ 103 DEFINE_CLK(_name, clk_gate_ops, _flags, \
103 .name = #_name, \ 104 _name##_parent_names, _name##_parents);
104 .ops = &clk_gate_ops, \
105 .hw = &_name##_hw.hw, \
106 .parent_names = _name##_parent_names, \
107 .num_parents = \
108 ARRAY_SIZE(_name##_parent_names), \
109 .parents = _name##_parents, \
110 .flags = _flags, \
111 };
112
113extern struct clk_ops clk_divider_ops;
114 105
115#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \ 106#define DEFINE_CLK_DIVIDER(_name, _parent_name, _parent_ptr, \
116 _flags, _reg, _shift, _width, \ 107 _flags, _reg, _shift, _width, \
117 _divider_flags, _lock) \ 108 _divider_flags, _lock) \
118 static struct clk _name; \ 109 static struct clk _name; \
119 static char *_name##_parent_names[] = { \ 110 static const char *_name##_parent_names[] = { \
120 _parent_name, \ 111 _parent_name, \
121 }; \ 112 }; \
122 static struct clk *_name##_parents[] = { \ 113 static struct clk *_name##_parents[] = { \
@@ -132,18 +123,8 @@ extern struct clk_ops clk_divider_ops;
132 .flags = _divider_flags, \ 123 .flags = _divider_flags, \
133 .lock = _lock, \ 124 .lock = _lock, \
134 }; \ 125 }; \
135 static struct clk _name = { \ 126 DEFINE_CLK(_name, clk_divider_ops, _flags, \
136 .name = #_name, \ 127 _name##_parent_names, _name##_parents);
137 .ops = &clk_divider_ops, \
138 .hw = &_name##_hw.hw, \
139 .parent_names = _name##_parent_names, \
140 .num_parents = \
141 ARRAY_SIZE(_name##_parent_names), \
142 .parents = _name##_parents, \
143 .flags = _flags, \
144 };
145
146extern struct clk_ops clk_mux_ops;
147 128
148#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \ 129#define DEFINE_CLK_MUX(_name, _parent_names, _parents, _flags, \
149 _reg, _shift, _width, \ 130 _reg, _shift, _width, \
@@ -159,16 +140,28 @@ extern struct clk_ops clk_mux_ops;
159 .flags = _mux_flags, \ 140 .flags = _mux_flags, \
160 .lock = _lock, \ 141 .lock = _lock, \
161 }; \ 142 }; \
162 static struct clk _name = { \ 143 DEFINE_CLK(_name, clk_mux_ops, _flags, _parent_names, \
163 .name = #_name, \ 144 _parents);
164 .ops = &clk_mux_ops, \ 145
165 .hw = &_name##_hw.hw, \ 146#define DEFINE_CLK_FIXED_FACTOR(_name, _parent_name, \
166 .parent_names = _parent_names, \ 147 _parent_ptr, _flags, \
167 .num_parents = \ 148 _mult, _div) \
168 ARRAY_SIZE(_parent_names), \ 149 static struct clk _name; \
169 .parents = _parents, \ 150 static const char *_name##_parent_names[] = { \
170 .flags = _flags, \ 151 _parent_name, \
171 }; 152 }; \
153 static struct clk *_name##_parents[] = { \
154 _parent_ptr, \
155 }; \
156 static struct clk_fixed_factor _name##_hw = { \
157 .hw = { \
158 .clk = &_name, \
159 }, \
160 .mult = _mult, \
161 .div = _div, \
162 }; \
163 DEFINE_CLK(_name, clk_fixed_factor_ops, _flags, \
164 _name##_parent_names, _name##_parents);
172 165
173/** 166/**
174 * __clk_init - initialize the data structures in a struct clk 167 * __clk_init - initialize the data structures in a struct clk
@@ -189,8 +182,12 @@ extern struct clk_ops clk_mux_ops;
189 * 182 *
190 * It is not necessary to call clk_register if __clk_init is used directly with 183 * It is not necessary to call clk_register if __clk_init is used directly with
191 * statically initialized clock data. 184 * statically initialized clock data.
185 *
186 * Returns 0 on success, otherwise an error code.
192 */ 187 */
193void __clk_init(struct device *dev, struct clk *clk); 188int __clk_init(struct device *dev, struct clk *clk);
189
190struct clk *__clk_register(struct device *dev, struct clk_hw *hw);
194 191
195#endif /* CONFIG_COMMON_CLK */ 192#endif /* CONFIG_COMMON_CLK */
196#endif /* CLK_PRIVATE_H */ 193#endif /* CLK_PRIVATE_H */
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 5508897ad376..c1c23b9ec368 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -15,19 +15,6 @@
15 15
16#ifdef CONFIG_COMMON_CLK 16#ifdef CONFIG_COMMON_CLK
17 17
18/**
19 * struct clk_hw - handle for traversing from a struct clk to its corresponding
20 * hardware-specific structure. struct clk_hw should be declared within struct
21 * clk_foo and then referenced by the struct clk instance that uses struct
22 * clk_foo's clk_ops
23 *
24 * clk: pointer to the struct clk instance that points back to this struct
25 * clk_hw instance
26 */
27struct clk_hw {
28 struct clk *clk;
29};
30
31/* 18/*
32 * flags used across common struct clk. these flags should only affect the 19 * flags used across common struct clk. these flags should only affect the
33 * top-level framework. custom flags for dealing with hardware specifics 20 * top-level framework. custom flags for dealing with hardware specifics
@@ -39,6 +26,8 @@ struct clk_hw {
39#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */ 26#define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
40#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */ 27#define CLK_IS_ROOT BIT(4) /* root clk, has no parent */
41 28
29struct clk_hw;
30
42/** 31/**
43 * struct clk_ops - Callback operations for hardware clocks; these are to 32 * struct clk_ops - Callback operations for hardware clocks; these are to
44 * be provided by the clock implementation, and will be called by drivers 33 * be provided by the clock implementation, and will be called by drivers
@@ -88,19 +77,11 @@ struct clk_hw {
88 * array index into the value programmed into the hardware. 77 * array index into the value programmed into the hardware.
89 * Returns 0 on success, -EERROR otherwise. 78 * Returns 0 on success, -EERROR otherwise.
90 * 79 *
91 * @set_rate: Change the rate of this clock. If this callback returns 80 * @set_rate: Change the rate of this clock. The requested rate is specified
92 * CLK_SET_RATE_PARENT, the rate change will be propagated to the 81 * by the second argument, which should typically be the return
93 * parent clock (which may propagate again if the parent clock 82 * of .round_rate call. The third argument gives the parent rate
94 * also sets this flag). The requested rate of the parent is 83 * which is likely helpful for most .set_rate implementation.
95 * passed back from the callback in the second 'unsigned long *' 84 * Returns 0 on success, -EERROR otherwise.
96 * argument. Note that it is up to the hardware clock's set_rate
97 * implementation to insure that clocks do not run out of spec
98 * when propgating the call to set_rate up to the parent. One way
99 * to do this is to gate the clock (via clk_disable and/or
100 * clk_unprepare) before calling clk_set_rate, then ungating it
101 * afterward. If your clock also has the CLK_GATE_SET_RATE flag
102 * set then this will insure safety. Returns 0 on success,
103 * -EERROR otherwise.
104 * 85 *
105 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow 86 * The clk_enable/clk_disable and clk_prepare/clk_unprepare pairs allow
106 * implementations to split any work between atomic (enable) and sleepable 87 * implementations to split any work between atomic (enable) and sleepable
@@ -125,10 +106,46 @@ struct clk_ops {
125 unsigned long *); 106 unsigned long *);
126 int (*set_parent)(struct clk_hw *hw, u8 index); 107 int (*set_parent)(struct clk_hw *hw, u8 index);
127 u8 (*get_parent)(struct clk_hw *hw); 108 u8 (*get_parent)(struct clk_hw *hw);
128 int (*set_rate)(struct clk_hw *hw, unsigned long); 109 int (*set_rate)(struct clk_hw *hw, unsigned long,
110 unsigned long);
129 void (*init)(struct clk_hw *hw); 111 void (*init)(struct clk_hw *hw);
130}; 112};
131 113
114/**
115 * struct clk_init_data - holds init data that's common to all clocks and is
116 * shared between the clock provider and the common clock framework.
117 *
118 * @name: clock name
119 * @ops: operations this clock supports
120 * @parent_names: array of string names for all possible parents
121 * @num_parents: number of possible parents
122 * @flags: framework-level hints and quirks
123 */
124struct clk_init_data {
125 const char *name;
126 const struct clk_ops *ops;
127 const char **parent_names;
128 u8 num_parents;
129 unsigned long flags;
130};
131
132/**
133 * struct clk_hw - handle for traversing from a struct clk to its corresponding
134 * hardware-specific structure. struct clk_hw should be declared within struct
135 * clk_foo and then referenced by the struct clk instance that uses struct
136 * clk_foo's clk_ops
137 *
138 * @clk: pointer to the struct clk instance that points back to this struct
139 * clk_hw instance
140 *
141 * @init: pointer to struct clk_init_data that contains the init data shared
142 * with the common clock framework.
143 */
144struct clk_hw {
145 struct clk *clk;
146 struct clk_init_data *init;
147};
148
132/* 149/*
133 * DOC: Basic clock implementations common to many platforms 150 * DOC: Basic clock implementations common to many platforms
134 * 151 *
@@ -149,6 +166,7 @@ struct clk_fixed_rate {
149 u8 flags; 166 u8 flags;
150}; 167};
151 168
169extern const struct clk_ops clk_fixed_rate_ops;
152struct clk *clk_register_fixed_rate(struct device *dev, const char *name, 170struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
153 const char *parent_name, unsigned long flags, 171 const char *parent_name, unsigned long flags,
154 unsigned long fixed_rate); 172 unsigned long fixed_rate);
@@ -165,7 +183,7 @@ struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
165 * Clock which can gate its output. Implements .enable & .disable 183 * Clock which can gate its output. Implements .enable & .disable
166 * 184 *
167 * Flags: 185 * Flags:
168 * CLK_GATE_SET_DISABLE - by default this clock sets the bit at bit_idx to 186 * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
169 * enable the clock. Setting this flag does the opposite: setting the bit 187 * enable the clock. Setting this flag does the opposite: setting the bit
170 * disable the clock and clearing it enables the clock 188 * disable the clock and clearing it enables the clock
171 */ 189 */
@@ -175,11 +193,11 @@ struct clk_gate {
175 u8 bit_idx; 193 u8 bit_idx;
176 u8 flags; 194 u8 flags;
177 spinlock_t *lock; 195 spinlock_t *lock;
178 char *parent[1];
179}; 196};
180 197
181#define CLK_GATE_SET_TO_DISABLE BIT(0) 198#define CLK_GATE_SET_TO_DISABLE BIT(0)
182 199
200extern const struct clk_ops clk_gate_ops;
183struct clk *clk_register_gate(struct device *dev, const char *name, 201struct clk *clk_register_gate(struct device *dev, const char *name,
184 const char *parent_name, unsigned long flags, 202 const char *parent_name, unsigned long flags,
185 void __iomem *reg, u8 bit_idx, 203 void __iomem *reg, u8 bit_idx,
@@ -212,12 +230,12 @@ struct clk_divider {
212 u8 width; 230 u8 width;
213 u8 flags; 231 u8 flags;
214 spinlock_t *lock; 232 spinlock_t *lock;
215 char *parent[1];
216}; 233};
217 234
218#define CLK_DIVIDER_ONE_BASED BIT(0) 235#define CLK_DIVIDER_ONE_BASED BIT(0)
219#define CLK_DIVIDER_POWER_OF_TWO BIT(1) 236#define CLK_DIVIDER_POWER_OF_TWO BIT(1)
220 237
238extern const struct clk_ops clk_divider_ops;
221struct clk *clk_register_divider(struct device *dev, const char *name, 239struct clk *clk_register_divider(struct device *dev, const char *name,
222 const char *parent_name, unsigned long flags, 240 const char *parent_name, unsigned long flags,
223 void __iomem *reg, u8 shift, u8 width, 241 void __iomem *reg, u8 shift, u8 width,
@@ -238,7 +256,7 @@ struct clk *clk_register_divider(struct device *dev, const char *name,
238 * 256 *
239 * Flags: 257 * Flags:
240 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0 258 * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
241 * CLK_MUX_INDEX_BITWISE - register index is a single bit (power of two) 259 * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
242 */ 260 */
243struct clk_mux { 261struct clk_mux {
244 struct clk_hw hw; 262 struct clk_hw hw;
@@ -252,29 +270,47 @@ struct clk_mux {
252#define CLK_MUX_INDEX_ONE BIT(0) 270#define CLK_MUX_INDEX_ONE BIT(0)
253#define CLK_MUX_INDEX_BIT BIT(1) 271#define CLK_MUX_INDEX_BIT BIT(1)
254 272
273extern const struct clk_ops clk_mux_ops;
255struct clk *clk_register_mux(struct device *dev, const char *name, 274struct clk *clk_register_mux(struct device *dev, const char *name,
256 char **parent_names, u8 num_parents, unsigned long flags, 275 const char **parent_names, u8 num_parents, unsigned long flags,
257 void __iomem *reg, u8 shift, u8 width, 276 void __iomem *reg, u8 shift, u8 width,
258 u8 clk_mux_flags, spinlock_t *lock); 277 u8 clk_mux_flags, spinlock_t *lock);
259 278
260/** 279/**
280 * struct clk_fixed_factor - fixed multiplier and divider clock
281 *
282 * @hw: handle between common and hardware-specific interfaces
283 * @mult: multiplier
284 * @div: divider
285 *
286 * Clock with a fixed multiplier and divider. The output frequency is the
287 * parent clock rate divided by div and multiplied by mult.
288 * Implements .recalc_rate, .set_rate and .round_rate
289 */
290
291struct clk_fixed_factor {
292 struct clk_hw hw;
293 unsigned int mult;
294 unsigned int div;
295};
296
297extern struct clk_ops clk_fixed_factor_ops;
298struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
299 const char *parent_name, unsigned long flags,
300 unsigned int mult, unsigned int div);
301
302/**
261 * clk_register - allocate a new clock, register it and return an opaque cookie 303 * clk_register - allocate a new clock, register it and return an opaque cookie
262 * @dev: device that is registering this clock 304 * @dev: device that is registering this clock
263 * @name: clock name
264 * @ops: operations this clock supports
265 * @hw: link to hardware-specific clock data 305 * @hw: link to hardware-specific clock data
266 * @parent_names: array of string names for all possible parents
267 * @num_parents: number of possible parents
268 * @flags: framework-level hints and quirks
269 * 306 *
270 * clk_register is the primary interface for populating the clock tree with new 307 * clk_register is the primary interface for populating the clock tree with new
271 * clock nodes. It returns a pointer to the newly allocated struct clk which 308 * clock nodes. It returns a pointer to the newly allocated struct clk which
272 * cannot be dereferenced by driver code but may be used in conjuction with the 309 * cannot be dereferenced by driver code but may be used in conjuction with the
273 * rest of the clock API. 310 * rest of the clock API. In the event of an error clk_register will return an
311 * error code; drivers must test for an error code after calling clk_register.
274 */ 312 */
275struct clk *clk_register(struct device *dev, const char *name, 313struct clk *clk_register(struct device *dev, struct clk_hw *hw);
276 const struct clk_ops *ops, struct clk_hw *hw,
277 char **parent_names, u8 num_parents, unsigned long flags);
278 314
279/* helper functions */ 315/* helper functions */
280const char *__clk_get_name(struct clk *clk); 316const char *__clk_get_name(struct clk *clk);
diff --git a/include/linux/clk.h b/include/linux/clk.h
index b0252726df61..0e078bdec09f 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -81,7 +81,7 @@ int clk_notifier_register(struct clk *clk, struct notifier_block *nb);
81 81
82int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb); 82int clk_notifier_unregister(struct clk *clk, struct notifier_block *nb);
83 83
84#endif /* !CONFIG_COMMON_CLK */ 84#endif
85 85
86/** 86/**
87 * clk_get - lookup and obtain a reference to a clock producer. 87 * clk_get - lookup and obtain a reference to a clock producer.
@@ -220,7 +220,7 @@ void clk_put(struct clk *clk);
220 * Returns rounded clock rate in Hz, or negative errno. 220 * Returns rounded clock rate in Hz, or negative errno.
221 */ 221 */
222long clk_round_rate(struct clk *clk, unsigned long rate); 222long clk_round_rate(struct clk *clk, unsigned long rate);
223 223
224/** 224/**
225 * clk_set_rate - set the clock rate for a clock source 225 * clk_set_rate - set the clock rate for a clock source
226 * @clk: clock source 226 * @clk: clock source
@@ -229,7 +229,7 @@ long clk_round_rate(struct clk *clk, unsigned long rate);
229 * Returns success (0) or negative errno. 229 * Returns success (0) or negative errno.
230 */ 230 */
231int clk_set_rate(struct clk *clk, unsigned long rate); 231int clk_set_rate(struct clk *clk, unsigned long rate);
232 232
233/** 233/**
234 * clk_set_parent - set the parent clock source for this clock 234 * clk_set_parent - set the parent clock source for this clock
235 * @clk: clock source 235 * @clk: clock source
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 21:07:29 -0400