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authorGeert Uytterhoeven <geert+renesas@glider.be>2015-02-17 10:31:38 -0500
committerSimon Horman <horms+renesas@verge.net.au>2015-02-23 18:22:49 -0500
commitbee7a18e85421ed3ec0131574378de10b5762d54 (patch)
treee5e75a6072fa729234b474189b76c6a2d6701a57
parent05813a8112cd0e38f14b53ecc2b381824cb2aeb4 (diff)
ARM: shmobile: sh73a0 dtsi: Add PM domain support
Add a device node for the System Controller, with subnodes that represent the hardware power area hierarchy. Hook up all devices to their respective PM domains. Note that unlike on R-Mobile A1 (r8a7740), PM domain D4 can be powered down without ill effects on s2ram behavior, just like on SH-Mobile AP4 (sh7372). Hence we can postpone adding a (minimal) device node for the Coresight-ETM hardware block. The System Controller is also used by the R-Mobile Reset driver, which can now restart the system. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi144
1 files changed, 142 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 0b933e254d19..45b539ce4d35 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -27,12 +27,14 @@
27 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
28 reg = <0>; 28 reg = <0>;
29 clock-frequency = <1196000000>; 29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
30 }; 31 };
31 cpu@1 { 32 cpu@1 {
32 device_type = "cpu"; 33 device_type = "cpu";
33 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
34 reg = <1>; 35 reg = <1>;
35 clock-frequency = <1196000000>; 36 clock-frequency = <1196000000>;
37 power-domains = <&pd_a2sl>;
36 }; 38 };
37 }; 39 };
38 40
@@ -57,6 +59,7 @@
57 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, 59 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
58 <0 38 IRQ_TYPE_LEVEL_HIGH>; 60 <0 38 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "sec", "temp"; 61 interrupt-names = "sec", "temp";
62 power-domains = <&pd_a4bc1>;
60 }; 63 };
61 64
62 sbsc1: memory-controller@fe400000 { 65 sbsc1: memory-controller@fe400000 {
@@ -65,6 +68,7 @@
65 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
66 <0 36 IRQ_TYPE_LEVEL_HIGH>; 69 <0 36 IRQ_TYPE_LEVEL_HIGH>;
67 interrupt-names = "sec", "temp"; 70 interrupt-names = "sec", "temp";
71 power-domains = <&pd_a4bc0>;
68 }; 72 };
69 73
70 pmu { 74 pmu {
@@ -77,11 +81,12 @@
77 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; 81 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
78 reg = <0xe6138000 0x200>; 82 reg = <0xe6138000 0x200>;
79 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; 83 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
85 clock-names = "fck";
86 power-domains = <&pd_c5>;
80 87
81 renesas,channels-mask = <0x3f>; 88 renesas,channels-mask = <0x3f>;
82 89
83 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
84 clock-names = "fck";
85 status = "disabled"; 90 status = "disabled";
86 }; 91 };
87 92
@@ -103,6 +108,7 @@
103 0 7 IRQ_TYPE_LEVEL_HIGH 108 0 7 IRQ_TYPE_LEVEL_HIGH
104 0 8 IRQ_TYPE_LEVEL_HIGH>; 109 0 8 IRQ_TYPE_LEVEL_HIGH>;
105 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
111 power-domains = <&pd_a4s>;
106 control-parent; 112 control-parent;
107 }; 113 };
108 114
@@ -124,6 +130,7 @@
124 0 15 IRQ_TYPE_LEVEL_HIGH 130 0 15 IRQ_TYPE_LEVEL_HIGH
125 0 16 IRQ_TYPE_LEVEL_HIGH>; 131 0 16 IRQ_TYPE_LEVEL_HIGH>;
126 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
133 power-domains = <&pd_a4s>;
127 control-parent; 134 control-parent;
128 }; 135 };
129 136
@@ -145,6 +152,7 @@
145 0 23 IRQ_TYPE_LEVEL_HIGH 152 0 23 IRQ_TYPE_LEVEL_HIGH
146 0 24 IRQ_TYPE_LEVEL_HIGH>; 153 0 24 IRQ_TYPE_LEVEL_HIGH>;
147 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
155 power-domains = <&pd_a4s>;
148 control-parent; 156 control-parent;
149 }; 157 };
150 158
@@ -166,6 +174,7 @@
166 0 31 IRQ_TYPE_LEVEL_HIGH 174 0 31 IRQ_TYPE_LEVEL_HIGH
167 0 32 IRQ_TYPE_LEVEL_HIGH>; 175 0 32 IRQ_TYPE_LEVEL_HIGH>;
168 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>; 176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
177 power-domains = <&pd_a4s>;
169 control-parent; 178 control-parent;
170 }; 179 };
171 180
@@ -179,6 +188,7 @@
179 0 169 IRQ_TYPE_LEVEL_HIGH 188 0 169 IRQ_TYPE_LEVEL_HIGH
180 0 170 IRQ_TYPE_LEVEL_HIGH>; 189 0 170 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&mstp1_clks SH73A0_CLK_IIC0>; 190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
191 power-domains = <&pd_a3sp>;
182 status = "disabled"; 192 status = "disabled";
183 }; 193 };
184 194
@@ -192,6 +202,7 @@
192 0 53 IRQ_TYPE_LEVEL_HIGH 202 0 53 IRQ_TYPE_LEVEL_HIGH
193 0 54 IRQ_TYPE_LEVEL_HIGH>; 203 0 54 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp3_clks SH73A0_CLK_IIC1>; 204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
205 power-domains = <&pd_a3sp>;
195 status = "disabled"; 206 status = "disabled";
196 }; 207 };
197 208
@@ -205,6 +216,7 @@
205 0 173 IRQ_TYPE_LEVEL_HIGH 216 0 173 IRQ_TYPE_LEVEL_HIGH
206 0 174 IRQ_TYPE_LEVEL_HIGH>; 217 0 174 IRQ_TYPE_LEVEL_HIGH>;
207 clocks = <&mstp0_clks SH73A0_CLK_IIC2>; 218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
219 power-domains = <&pd_a3sp>;
208 status = "disabled"; 220 status = "disabled";
209 }; 221 };
210 222
@@ -218,6 +230,7 @@
218 0 185 IRQ_TYPE_LEVEL_HIGH 230 0 185 IRQ_TYPE_LEVEL_HIGH
219 0 186 IRQ_TYPE_LEVEL_HIGH>; 231 0 186 IRQ_TYPE_LEVEL_HIGH>;
220 clocks = <&mstp4_clks SH73A0_CLK_IIC3>; 232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
233 power-domains = <&pd_a3sp>;
221 status = "disabled"; 234 status = "disabled";
222 }; 235 };
223 236
@@ -231,6 +244,7 @@
231 0 189 IRQ_TYPE_LEVEL_HIGH 244 0 189 IRQ_TYPE_LEVEL_HIGH
232 0 190 IRQ_TYPE_LEVEL_HIGH>; 245 0 190 IRQ_TYPE_LEVEL_HIGH>;
233 clocks = <&mstp4_clks SH73A0_CLK_IIC4>; 246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
247 power-domains = <&pd_c5>;
234 status = "disabled"; 248 status = "disabled";
235 }; 249 };
236 250
@@ -240,6 +254,7 @@
240 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 254 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
241 0 141 IRQ_TYPE_LEVEL_HIGH>; 255 0 141 IRQ_TYPE_LEVEL_HIGH>;
242 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; 256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
257 power-domains = <&pd_a3sp>;
243 reg-io-width = <4>; 258 reg-io-width = <4>;
244 status = "disabled"; 259 status = "disabled";
245 }; 260 };
@@ -251,6 +266,7 @@
251 0 84 IRQ_TYPE_LEVEL_HIGH 266 0 84 IRQ_TYPE_LEVEL_HIGH
252 0 85 IRQ_TYPE_LEVEL_HIGH>; 267 0 85 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; 268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
269 power-domains = <&pd_a3sp>;
254 cap-sd-highspeed; 270 cap-sd-highspeed;
255 status = "disabled"; 271 status = "disabled";
256 }; 272 };
@@ -262,6 +278,7 @@
262 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 278 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
263 0 89 IRQ_TYPE_LEVEL_HIGH>; 279 0 89 IRQ_TYPE_LEVEL_HIGH>;
264 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
281 power-domains = <&pd_a3sp>;
265 toshiba,mmc-wrprotect-disable; 282 toshiba,mmc-wrprotect-disable;
266 cap-sd-highspeed; 283 cap-sd-highspeed;
267 status = "disabled"; 284 status = "disabled";
@@ -273,6 +290,7 @@
273 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 290 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
274 0 105 IRQ_TYPE_LEVEL_HIGH>; 291 0 105 IRQ_TYPE_LEVEL_HIGH>;
275 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
293 power-domains = <&pd_a3sp>;
276 toshiba,mmc-wrprotect-disable; 294 toshiba,mmc-wrprotect-disable;
277 cap-sd-highspeed; 295 cap-sd-highspeed;
278 status = "disabled"; 296 status = "disabled";
@@ -284,6 +302,7 @@
284 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 302 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
285 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; 303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
286 clock-names = "sci_ick"; 304 clock-names = "sci_ick";
305 power-domains = <&pd_a3sp>;
287 status = "disabled"; 306 status = "disabled";
288 }; 307 };
289 308
@@ -293,6 +312,7 @@
293 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 312 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
294 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; 313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
295 clock-names = "sci_ick"; 314 clock-names = "sci_ick";
315 power-domains = <&pd_a3sp>;
296 status = "disabled"; 316 status = "disabled";
297 }; 317 };
298 318
@@ -302,6 +322,7 @@
302 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; 323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
304 clock-names = "sci_ick"; 324 clock-names = "sci_ick";
325 power-domains = <&pd_a3sp>;
305 status = "disabled"; 326 status = "disabled";
306 }; 327 };
307 328
@@ -311,6 +332,7 @@
311 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; 333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
313 clock-names = "sci_ick"; 334 clock-names = "sci_ick";
335 power-domains = <&pd_a3sp>;
314 status = "disabled"; 336 status = "disabled";
315 }; 337 };
316 338
@@ -320,6 +342,7 @@
320 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
321 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; 343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
322 clock-names = "sci_ick"; 344 clock-names = "sci_ick";
345 power-domains = <&pd_a3sp>;
323 status = "disabled"; 346 status = "disabled";
324 }; 347 };
325 348
@@ -329,6 +352,7 @@
329 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
330 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; 353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
331 clock-names = "sci_ick"; 354 clock-names = "sci_ick";
355 power-domains = <&pd_a3sp>;
332 status = "disabled"; 356 status = "disabled";
333 }; 357 };
334 358
@@ -338,6 +362,7 @@
338 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 362 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
339 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; 363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
340 clock-names = "sci_ick"; 364 clock-names = "sci_ick";
365 power-domains = <&pd_a3sp>;
341 status = "disabled"; 366 status = "disabled";
342 }; 367 };
343 368
@@ -347,6 +372,7 @@
347 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 372 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
348 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; 373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
349 clock-names = "sci_ick"; 374 clock-names = "sci_ick";
375 power-domains = <&pd_a3sp>;
350 status = "disabled"; 376 status = "disabled";
351 }; 377 };
352 378
@@ -356,6 +382,7 @@
356 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
357 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; 383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
358 clock-names = "sci_ick"; 384 clock-names = "sci_ick";
385 power-domains = <&pd_a3sp>;
359 status = "disabled"; 386 status = "disabled";
360 }; 387 };
361 388
@@ -374,6 +401,117 @@
374 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 401 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
375 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 402 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
376 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 403 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
404 power-domains = <&pd_c5>;
405 };
406
407 sysc: system-controller@e6180000 {
408 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
409 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
410
411 pm-domains {
412 pd_c5: c5 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 #power-domain-cells = <0>;
416
417 pd_c4: c4@0 {
418 reg = <0>;
419 #power-domain-cells = <0>;
420 };
421
422 pd_d4: d4@1 {
423 reg = <1>;
424 #power-domain-cells = <0>;
425 };
426
427 pd_a4bc0: a4bc0@4 {
428 reg = <4>;
429 #power-domain-cells = <0>;
430 };
431
432 pd_a4bc1: a4bc1@5 {
433 reg = <5>;
434 #power-domain-cells = <0>;
435 };
436
437 pd_a4lc0: a4lc0@6 {
438 reg = <6>;
439 #power-domain-cells = <0>;
440 };
441
442 pd_a4lc1: a4lc1@7 {
443 reg = <7>;
444 #power-domain-cells = <0>;
445 };
446
447 pd_a4mp: a4mp@8 {
448 reg = <8>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 #power-domain-cells = <0>;
452
453 pd_a3mp: a3mp@9 {
454 reg = <9>;
455 #power-domain-cells = <0>;
456 };
457
458 pd_a3vc: a3vc@10 {
459 reg = <10>;
460 #power-domain-cells = <0>;
461 };
462 };
463
464 pd_a4rm: a4rm@12 {
465 reg = <12>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 #power-domain-cells = <0>;
469
470 pd_a3r: a3r@13 {
471 reg = <13>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 #power-domain-cells = <0>;
475
476 pd_a2rv: a2rv@14 {
477 reg = <14>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
481 };
482 };
483 };
484
485 pd_a4s: a4s@16 {
486 reg = <16>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 #power-domain-cells = <0>;
490
491 pd_a3sp: a3sp@17 {
492 reg = <17>;
493 #power-domain-cells = <0>;
494 };
495
496 pd_a3sg: a3sg@18 {
497 reg = <18>;
498 #power-domain-cells = <0>;
499 };
500
501 pd_a3sm: a3sm@19 {
502 reg = <19>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 #power-domain-cells = <0>;
506
507 pd_a2sl: a2sl@20 {
508 reg = <20>;
509 #power-domain-cells = <0>;
510 };
511 };
512 };
513 };
514 };
377 }; 515 };
378 516
379 sh_fsi2: sound@ec230000 { 517 sh_fsi2: sound@ec230000 {
@@ -381,6 +519,7 @@
381 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; 519 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
382 reg = <0xec230000 0x400>; 520 reg = <0xec230000 0x400>;
383 interrupts = <0 146 0x4>; 521 interrupts = <0 146 0x4>;
522 power-domains = <&pd_a4mp>;
384 status = "disabled"; 523 status = "disabled";
385 }; 524 };
386 525
@@ -393,6 +532,7 @@
393 reg = <0xfec10000 0x400>; 532 reg = <0xfec10000 0x400>;
394 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 533 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&zb_clk>; 534 clocks = <&zb_clk>;
535 power-domains = <&pd_a4s>;
396 }; 536 };
397 537
398 clocks { 538 clocks {
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-30 03:16:49 -0400