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authorRafał Miłecki <zajec5@gmail.com>2014-05-31 14:49:40 -0400
committerJohn W. Linville <linville@tuxdriver.com>2014-06-19 15:49:13 -0400
commitbee6d4b272ba6e668f0c12d8bb66d76e1826f406 (patch)
tree6c58b4193fc93dc388cc446c1dc41e85ec0d298e
parent39e971ef1b0ced72b6504429296551bbf14ac965 (diff)
b43: PHY: drop is_40mhz (get width info from chandef)
Signed-off-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
-rw-r--r--drivers/net/wireless/b43/main.c5
-rw-r--r--drivers/net/wireless/b43/phy_common.c5
-rw-r--r--drivers/net/wireless/b43/phy_common.h5
-rw-r--r--drivers/net/wireless/b43/phy_n.c53
4 files changed, 33 insertions, 35 deletions
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 2b99ed31ab08..4b662d0abdd2 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -3810,11 +3810,6 @@ static int b43_op_config(struct ieee80211_hw *hw, u32 changed)
3810 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { 3810 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
3811 phy->chandef = &conf->chandef; 3811 phy->chandef = &conf->chandef;
3812 phy->channel = conf->chandef.chan->hw_value; 3812 phy->channel = conf->chandef.chan->hw_value;
3813 if (conf_is_ht(conf))
3814 phy->is_40mhz = conf_is_ht40_minus(conf) ||
3815 conf_is_ht40_plus(conf);
3816 else
3817 phy->is_40mhz = false;
3818 3813
3819 /* Switch the band (if necessary). */ 3814 /* Switch the band (if necessary). */
3820 err = b43_switch_band(dev, conf->chandef.chan); 3815 err = b43_switch_band(dev, conf->chandef.chan);
diff --git a/drivers/net/wireless/b43/phy_common.c b/drivers/net/wireless/b43/phy_common.c
index 9aa6c9c57393..e7e83835f725 100644
--- a/drivers/net/wireless/b43/phy_common.c
+++ b/drivers/net/wireless/b43/phy_common.c
@@ -553,6 +553,11 @@ bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type)
553 channel_type == NL80211_CHAN_HT40PLUS); 553 channel_type == NL80211_CHAN_HT40PLUS);
554} 554}
555 555
556bool b43_is_40mhz(struct b43_wldev *dev)
557{
558 return dev->phy.chandef->width == NL80211_CHAN_WIDTH_40;
559}
560
556/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 561/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
557void b43_phy_force_clock(struct b43_wldev *dev, bool force) 562void b43_phy_force_clock(struct b43_wldev *dev, bool force)
558{ 563{
diff --git a/drivers/net/wireless/b43/phy_common.h b/drivers/net/wireless/b43/phy_common.h
index 399082026b03..674422fd22e6 100644
--- a/drivers/net/wireless/b43/phy_common.h
+++ b/drivers/net/wireless/b43/phy_common.h
@@ -228,9 +228,6 @@ struct b43_phy {
228 bool supports_2ghz; 228 bool supports_2ghz;
229 bool supports_5ghz; 229 bool supports_5ghz;
230 230
231 /* HT info */
232 bool is_40mhz;
233
234 /* Is GMODE (2 GHz mode) bit enabled? */ 231 /* Is GMODE (2 GHz mode) bit enabled? */
235 bool gmode; 232 bool gmode;
236 233
@@ -452,6 +449,8 @@ void b43_phyop_switch_analog_generic(struct b43_wldev *dev, bool on);
452 449
453bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type); 450bool b43_channel_type_is_40mhz(enum nl80211_channel_type channel_type);
454 451
452bool b43_is_40mhz(struct b43_wldev *dev);
453
455void b43_phy_force_clock(struct b43_wldev *dev, bool force); 454void b43_phy_force_clock(struct b43_wldev *dev, bool force);
456 455
457struct b43_c32 b43_cordic(int theta); 456struct b43_c32 b43_cordic(int theta);
diff --git a/drivers/net/wireless/b43/phy_n.c b/drivers/net/wireless/b43/phy_n.c
index dc62f024f776..dc1249381275 100644
--- a/drivers/net/wireless/b43/phy_n.c
+++ b/drivers/net/wireless/b43/phy_n.c
@@ -896,7 +896,7 @@ static void b43_radio_2056_setup(struct b43_wldev *dev,
896 offset | B2056_TX_MIXG_BOOST_TUNE, 896 offset | B2056_TX_MIXG_BOOST_TUNE,
897 mixg_boost); 897 mixg_boost);
898 } else { 898 } else {
899 bias = dev->phy.is_40mhz ? 0x40 : 0x20; 899 bias = b43_is_40mhz(dev) ? 0x40 : 0x20;
900 b43_radio_write(dev, 900 b43_radio_write(dev,
901 offset | B2056_TX_INTPAG_IMAIN_STAT, 901 offset | B2056_TX_INTPAG_IMAIN_STAT,
902 bias); 902 bias);
@@ -1211,8 +1211,7 @@ static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1211 u16 bw, len, rot, angle; 1211 u16 bw, len, rot, angle;
1212 struct b43_c32 *samples; 1212 struct b43_c32 *samples;
1213 1213
1214 1214 bw = b43_is_40mhz(dev) ? 40 : 20;
1215 bw = (dev->phy.is_40mhz) ? 40 : 20;
1216 len = bw << 3; 1215 len = bw << 3;
1217 1216
1218 if (test) { 1217 if (test) {
@@ -1221,7 +1220,7 @@ static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1221 else 1220 else
1222 bw = 80; 1221 bw = 80;
1223 1222
1224 if (dev->phy.is_40mhz) 1223 if (b43_is_40mhz(dev))
1225 bw <<= 1; 1224 bw <<= 1;
1226 1225
1227 len = bw << 1; 1226 len = bw << 1;
@@ -1264,7 +1263,7 @@ static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1264 } 1263 }
1265 1264
1266 /* TODO: add modify_bbmult argument */ 1265 /* TODO: add modify_bbmult argument */
1267 if (!dev->phy.is_40mhz) 1266 if (!b43_is_40mhz(dev))
1268 tmp = 0x6464; 1267 tmp = 0x6464;
1269 else 1268 else
1270 tmp = 0x4747; 1269 tmp = 0x4747;
@@ -2194,7 +2193,7 @@ static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2194 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84); 2193 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
2195 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84); 2194 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
2196 2195
2197 if (!dev->phy.is_40mhz) { 2196 if (!b43_is_40mhz(dev)) {
2198 /* Set dwell lengths */ 2197 /* Set dwell lengths */
2199 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B); 2198 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
2200 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B); 2199 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
@@ -2208,7 +2207,7 @@ static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2208 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES, 2207 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
2209 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21); 2208 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2, 21);
2210 2209
2211 if (!dev->phy.is_40mhz) { 2210 if (!b43_is_40mhz(dev)) {
2212 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI, 2211 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
2213 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1); 2212 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
2214 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI, 2213 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
@@ -2223,12 +2222,12 @@ static void b43_nphy_gain_ctl_workarounds_rev1_2(struct b43_wldev *dev)
2223 2222
2224 if (nphy->gain_boost) { 2223 if (nphy->gain_boost) {
2225 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ && 2224 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
2226 dev->phy.is_40mhz) 2225 b43_is_40mhz(dev))
2227 code = 4; 2226 code = 4;
2228 else 2227 else
2229 code = 5; 2228 code = 5;
2230 } else { 2229 } else {
2231 code = dev->phy.is_40mhz ? 6 : 7; 2230 code = b43_is_40mhz(dev) ? 6 : 7;
2232 } 2231 }
2233 2232
2234 /* Set HPVGA2 index */ 2233 /* Set HPVGA2 index */
@@ -2300,7 +2299,7 @@ static void b43_nphy_gain_ctl_workarounds(struct b43_wldev *dev)
2300static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset) 2299static u16 b43_nphy_read_lpf_ctl(struct b43_wldev *dev, u16 offset)
2301{ 2300{
2302 if (!offset) 2301 if (!offset)
2303 offset = (dev->phy.is_40mhz) ? 0x159 : 0x154; 2302 offset = b43_is_40mhz(dev) ? 0x159 : 0x154;
2304 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7; 2303 return b43_ntab_read(dev, B43_NTAB16(7, offset)) & 0x7;
2305} 2304}
2306 2305
@@ -2373,13 +2372,13 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2373 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159); 2372 lpf_40 = b43_nphy_read_lpf_ctl(dev, 0x159);
2374 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152); 2373 lpf_11b = b43_nphy_read_lpf_ctl(dev, 0x152);
2375 if (b43_nphy_ipa(dev)) { 2374 if (b43_nphy_ipa(dev)) {
2376 if ((phy->radio_rev == 5 && phy->is_40mhz) || 2375 if ((phy->radio_rev == 5 && b43_is_40mhz(dev)) ||
2377 phy->radio_rev == 7 || phy->radio_rev == 8) { 2376 phy->radio_rev == 7 || phy->radio_rev == 8) {
2378 bcap_val = b43_radio_read(dev, 0x16b); 2377 bcap_val = b43_radio_read(dev, 0x16b);
2379 scap_val = b43_radio_read(dev, 0x16a); 2378 scap_val = b43_radio_read(dev, 0x16a);
2380 scap_val_11b = scap_val; 2379 scap_val_11b = scap_val;
2381 bcap_val_11b = bcap_val; 2380 bcap_val_11b = bcap_val;
2382 if (phy->radio_rev == 5 && phy->is_40mhz) { 2381 if (phy->radio_rev == 5 && b43_is_40mhz(dev)) {
2383 scap_val_11n_20 = scap_val; 2382 scap_val_11n_20 = scap_val;
2384 bcap_val_11n_20 = bcap_val; 2383 bcap_val_11n_20 = bcap_val;
2385 scap_val_11n_40 = bcap_val_11n_40 = 0xc; 2384 scap_val_11n_40 = bcap_val_11n_40 = 0xc;
@@ -2521,7 +2520,7 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2521 } 2520 }
2522 } 2521 }
2523 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) { 2522 } else if (phy->radio_rev == 7 || phy->radio_rev == 8) {
2524 if (!phy->is_40mhz) { 2523 if (!b43_is_40mhz(dev)) {
2525 b43_radio_write(dev, 0x5F, 0x14); 2524 b43_radio_write(dev, 0x5F, 0x14);
2526 b43_radio_write(dev, 0xE8, 0x12); 2525 b43_radio_write(dev, 0xE8, 0x12);
2527 } else { 2526 } else {
@@ -2594,7 +2593,7 @@ static void b43_nphy_workarounds_rev7plus(struct b43_wldev *dev)
2594 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77); 2593 b43_ntab_write(dev, B43_NTAB16(7, 0x123), 0x77);
2595 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77); 2594 b43_ntab_write(dev, B43_NTAB16(7, 0x12A), 0x77);
2596 2595
2597 if (!phy->is_40mhz) { 2596 if (!b43_is_40mhz(dev)) {
2598 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D); 2597 b43_ntab_write(dev, B43_NTAB32(16, 0x03), 0x18D);
2599 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D); 2598 b43_ntab_write(dev, B43_NTAB32(16, 0x7F), 0x18D);
2600 } else { 2599 } else {
@@ -2693,7 +2692,7 @@ static void b43_nphy_workarounds_rev3plus(struct b43_wldev *dev)
2693 2692
2694 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700); 2693 b43_phy_maskset(dev, B43_NPHY_SGILTRNOFFSET, 0xF0FF, 0x0700);
2695 2694
2696 if (!dev->phy.is_40mhz) { 2695 if (!b43_is_40mhz(dev)) {
2697 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D); 2696 b43_ntab_write(dev, B43_NTAB32(16, 3), 0x18D);
2698 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D); 2697 b43_ntab_write(dev, B43_NTAB32(16, 127), 0x18D);
2699 } else { 2698 } else {
@@ -3116,7 +3115,7 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3116 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, 3115 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3117 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A); 3116 ~B43_NPHY_BPHY_CTL3_SCALE, 0x5A);
3118 3117
3119 if (dev->phy.rev < 2 && dev->phy.is_40mhz) 3118 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3120 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW); 3119 b43_hf_write(dev, b43_hf_read(dev) | B43_HF_TSSIRPSMW);
3121 } else { 3120 } else {
3122 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84, 3121 b43_ntab_write_bulk(dev, B43_NTAB16(26, 64), 84,
@@ -3170,7 +3169,7 @@ static void b43_nphy_tx_power_ctrl(struct b43_wldev *dev, bool enable)
3170 else if (dev->phy.rev < 2) 3169 else if (dev->phy.rev < 2)
3171 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40); 3170 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3, ~0xFF, 0x40);
3172 3171
3173 if (dev->phy.rev < 2 && dev->phy.is_40mhz) 3172 if (dev->phy.rev < 2 && b43_is_40mhz(dev))
3174 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW); 3173 b43_hf_write(dev, b43_hf_read(dev) & ~B43_HF_TSSIRPSMW);
3175 3174
3176 if (b43_nphy_ipa(dev)) { 3175 if (b43_nphy_ipa(dev)) {
@@ -3442,21 +3441,21 @@ static void b43_nphy_tx_prepare_adjusted_power_table(struct b43_wldev *dev)
3442 delta = 0; 3441 delta = 0;
3443 switch (stf_mode) { 3442 switch (stf_mode) {
3444 case 0: 3443 case 0:
3445 if (dev->phy.is_40mhz && dev->phy.rev >= 5) { 3444 if (b43_is_40mhz(dev) && dev->phy.rev >= 5) {
3446 idx = 68; 3445 idx = 68;
3447 } else { 3446 } else {
3448 delta = 1; 3447 delta = 1;
3449 idx = dev->phy.is_40mhz ? 52 : 4; 3448 idx = b43_is_40mhz(dev) ? 52 : 4;
3450 } 3449 }
3451 break; 3450 break;
3452 case 1: 3451 case 1:
3453 idx = dev->phy.is_40mhz ? 76 : 28; 3452 idx = b43_is_40mhz(dev) ? 76 : 28;
3454 break; 3453 break;
3455 case 2: 3454 case 2:
3456 idx = dev->phy.is_40mhz ? 84 : 36; 3455 idx = b43_is_40mhz(dev) ? 84 : 36;
3457 break; 3456 break;
3458 case 3: 3457 case 3:
3459 idx = dev->phy.is_40mhz ? 92 : 44; 3458 idx = b43_is_40mhz(dev) ? 92 : 44;
3460 break; 3459 break;
3461 } 3460 }
3462 3461
@@ -3996,7 +3995,7 @@ static void b43_nphy_spur_workaround(struct b43_wldev *dev)
3996 3995
3997 if (nphy->gband_spurwar_en) { 3996 if (nphy->gband_spurwar_en) {
3998 /* TODO: N PHY Adjust Analog Pfbw (7) */ 3997 /* TODO: N PHY Adjust Analog Pfbw (7) */
3999 if (channel == 11 && dev->phy.is_40mhz) 3998 if (channel == 11 && b43_is_40mhz(dev))
4000 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/ 3999 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
4001 else 4000 else
4002 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/ 4001 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
@@ -4290,7 +4289,7 @@ static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
4290 b43_phy_write(dev, B43_PHY_N(offset[i] + j), 4289 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
4291 tbl_tx_filter_coef_rev4[i][j]); 4290 tbl_tx_filter_coef_rev4[i][j]);
4292 4291
4293 if (dev->phy.is_40mhz) { 4292 if (b43_is_40mhz(dev)) {
4294 for (j = 0; j < 15; j++) 4293 for (j = 0; j < 15; j++)
4295 b43_phy_write(dev, B43_PHY_N(offset[0] + j), 4294 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
4296 tbl_tx_filter_coef_rev4[3][j]); 4295 tbl_tx_filter_coef_rev4[3][j]);
@@ -4626,7 +4625,7 @@ static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4626 (dev->phy.rev == 5 && nphy->ipa2g_on && 4625 (dev->phy.rev == 5 && nphy->ipa2g_on &&
4627 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ); 4626 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
4628 if (phy6or5x) { 4627 if (phy6or5x) {
4629 if (dev->phy.is_40mhz) { 4628 if (b43_is_40mhz(dev)) {
4630 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18, 4629 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
4631 tbl_tx_iqlo_cal_loft_ladder_40); 4630 tbl_tx_iqlo_cal_loft_ladder_40);
4632 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18, 4631 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
@@ -4641,13 +4640,13 @@ static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
4641 4640
4642 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9); 4641 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
4643 4642
4644 if (!dev->phy.is_40mhz) 4643 if (!b43_is_40mhz(dev))
4645 freq = 2500; 4644 freq = 2500;
4646 else 4645 else
4647 freq = 5000; 4646 freq = 5000;
4648 4647
4649 if (nphy->mphase_cal_phase_id > 2) 4648 if (nphy->mphase_cal_phase_id > 2)
4650 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8, 4649 b43_nphy_run_samples(dev, (b43_is_40mhz(dev) ? 40 : 20) * 8,
4651 0xFFFF, 0, true, false); 4650 0xFFFF, 0, true, false);
4652 else 4651 else
4653 error = b43_nphy_tx_tone(dev, freq, 250, true, false); 4652 error = b43_nphy_tx_tone(dev, freq, 250, true, false);