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authorMugunthan V N <mugunthanvnm@ti.com>2013-06-07 07:32:52 -0400
committerBenoit Cousson <benoit.cousson@linaro.org>2013-06-19 05:49:13 -0400
commitbe814fda0fedd524ff0758bd3bc9fc148c045805 (patch)
treec69a969f64bb05f81655d7ea5e3e98f789195731
parentc08f6e74243ffb3908daa4661e2b58e4a2ab41c1 (diff)
ARM: dts: AM33XX: Add pinmux configuration for CPSW to beaglebone
Add pinmux configurations for MII based CPSW ethernet to am335x-bone. Default mode is nothing but the values required for the module during active state. With this configurations module is functional as expected. Sleep mode is nothing but the values required for the module during inactive state. The pins are configured to its reset state to optimize energy usage for the pins for the suspend/resume cycle Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Benoit Cousson <benoit.cousson@linaro.org>
-rw-r--r--arch/arm/boot/dts/am335x-bone.dts67
1 files changed, 67 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-bone.dts b/arch/arm/boot/dts/am335x-bone.dts
index fd48173dae09..04feaf8f1420 100644
--- a/arch/arm/boot/dts/am335x-bone.dts
+++ b/arch/arm/boot/dts/am335x-bone.dts
@@ -56,6 +56,60 @@
56 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 56 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
57 >; 57 >;
58 }; 58 };
59
60 cpsw_default: cpsw_default {
61 pinctrl-single,pins = <
62 /* Slave 1 */
63 0x110 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxerr.mii1_rxerr */
64 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txen.mii1_txen */
65 0x118 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxdv.mii1_rxdv */
66 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd3.mii1_txd3 */
67 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd2.mii1_txd2 */
68 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd1.mii1_txd1 */
69 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* mii1_txd0.mii1_txd0 */
70 0x12c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_txclk.mii1_txclk */
71 0x130 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxclk.mii1_rxclk */
72 0x134 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd3.mii1_rxd3 */
73 0x138 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd2.mii1_rxd2 */
74 0x13c (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd1.mii1_rxd1 */
75 0x140 (PIN_INPUT_PULLUP | MUX_MODE0) /* mii1_rxd0.mii1_rxd0 */
76 >;
77 };
78
79 cpsw_sleep: cpsw_sleep {
80 pinctrl-single,pins = <
81 /* Slave 1 reset value */
82 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7)
83 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7)
84 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7)
85 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7)
86 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7)
87 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7)
88 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7)
89 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7)
90 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7)
91 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7)
92 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7)
93 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7)
94 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7)
95 >;
96 };
97
98 davinci_mdio_default: davinci_mdio_default {
99 pinctrl-single,pins = <
100 /* MDIO */
101 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */
102 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */
103 >;
104 };
105
106 davinci_mdio_sleep: davinci_mdio_sleep {
107 pinctrl-single,pins = <
108 /* MDIO reset value */
109 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7)
110 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7)
111 >;
112 };
59 }; 113 };
60 114
61 ocp { 115 ocp {
@@ -165,3 +219,16 @@
165&cpsw_emac1 { 219&cpsw_emac1 {
166 phy_id = <&davinci_mdio>, <1>; 220 phy_id = <&davinci_mdio>, <1>;
167}; 221};
222
223&mac {
224 pinctrl-names = "default", "sleep";
225 pinctrl-0 = <&cpsw_default>;
226 pinctrl-1 = <&cpsw_sleep>;
227
228};
229
230&davinci_mdio {
231 pinctrl-names = "default", "sleep";
232 pinctrl-0 = <&davinci_mdio_default>;
233 pinctrl-1 = <&davinci_mdio_sleep>;
234};