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authorAndi Kleen <andi@firstfloor.org>2009-02-12 07:49:38 -0500
committerH. Peter Anvin <hpa@zytor.com>2009-02-24 16:41:01 -0500
commitbe71b8553d0522aba535a815baaebb1f0bb9a9ec (patch)
treebbf5093333405249fa360a1dbf5dcc42be514a98
parent5ca8681ca10f671427710f4954644359856581a3 (diff)
x86, mce, cmci: recheck CMCI banks after APIC has been enabled on CPU #0
Impact: Fix marginal race condition One the first CPU the machine checks are enabled early before the local APIC is enabled. This could in theory lead to some lost CMCI events very early during boot because CMCIs cannot be delivered with disabled LAPIC. The poller also doesn't recover from this because it doesn't check CMCI banks. Add an explicit CMCI banks check after the LAPIC is enabled. This is only done for CPU #0, the other CPUs only initialize machine checks after the LAPIC is on. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
-rw-r--r--arch/x86/kernel/apic.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/x86/kernel/apic.c b/arch/x86/kernel/apic.c
index 648676f0b50a..57b53774d986 100644
--- a/arch/x86/kernel/apic.c
+++ b/arch/x86/kernel/apic.c
@@ -48,6 +48,7 @@
48#include <asm/apic.h> 48#include <asm/apic.h>
49#include <asm/i8259.h> 49#include <asm/i8259.h>
50#include <asm/smp.h> 50#include <asm/smp.h>
51#include <asm/mce.h>
51 52
52#include <mach_apic.h> 53#include <mach_apic.h>
53#include <mach_apicdef.h> 54#include <mach_apicdef.h>
@@ -1270,6 +1271,12 @@ void __cpuinit setup_local_APIC(void)
1270 apic_write(APIC_LVT1, value); 1271 apic_write(APIC_LVT1, value);
1271 1272
1272 preempt_enable(); 1273 preempt_enable();
1274
1275#ifdef CONFIG_X86_MCE_INTEL
1276 /* Recheck CMCI information after local APIC is up on CPU #0 */
1277 if (smp_processor_id() == 0)
1278 cmci_recheck();
1279#endif
1273} 1280}
1274 1281
1275void __cpuinit end_local_APIC_setup(void) 1282void __cpuinit end_local_APIC_setup(void)