aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorRussell King <rmk+kernel@arm.linux.org.uk>2011-06-26 08:42:01 -0400
committerRussell King <rmk+kernel@arm.linux.org.uk>2011-06-29 05:06:36 -0400
commitbe020f8618caa0670a2a5b5a5df79549520f7867 (patch)
tree5b85ecbab42342e2ddc6de5b9ea7b4e9fb2f1cef
parent0402becef94c43bb2bb483653a5cee2fb5049764 (diff)
ARM: entry: abort-macro: specify registers to be used for macros
Require all callers of abort macros to specify the registers to be used. This improves the documentation at the callsites as to which registers are being used by this assembly code. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat
-rw-r--r--arch/arm/mm/abort-ev4t.S2
-rw-r--r--arch/arm/mm/abort-ev5t.S4
-rw-r--r--arch/arm/mm/abort-ev5tj.S4
-rw-r--r--arch/arm/mm/abort-ev6.S4
-rw-r--r--arch/arm/mm/abort-macro.S30
5 files changed, 22 insertions, 22 deletions
diff --git a/arch/arm/mm/abort-ev4t.S b/arch/arm/mm/abort-ev4t.S
index b6282548f922..9910123079ce 100644
--- a/arch/arm/mm/abort-ev4t.S
+++ b/arch/arm/mm/abort-ev4t.S
@@ -22,7 +22,7 @@
22ENTRY(v4t_early_abort) 22ENTRY(v4t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort 25 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r2] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 27 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
28 tst r3, #1 << 20 @ check write 28 tst r3, #1 << 20 @ check write
diff --git a/arch/arm/mm/abort-ev5t.S b/arch/arm/mm/abort-ev5t.S
index 02251b526c0d..800e8d42d39e 100644
--- a/arch/arm/mm/abort-ev5t.S
+++ b/arch/arm/mm/abort-ev5t.S
@@ -22,10 +22,10 @@
22ENTRY(v5t_early_abort) 22ENTRY(v5t_early_abort)
23 mrc p15, 0, r1, c5, c0, 0 @ get FSR 23 mrc p15, 0, r1, c5, c0, 0 @ get FSR
24 mrc p15, 0, r0, c6, c0, 0 @ get FAR 24 mrc p15, 0, r0, c6, c0, 0 @ get FAR
25 do_thumb_abort 25 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
26 ldreq r3, [r2] @ read aborted ARM instruction 26 ldreq r3, [r2] @ read aborted ARM instruction
27 bic r1, r1, #1 << 11 @ clear bits 11 of FSR 27 bic r1, r1, #1 << 11 @ clear bits 11 of FSR
28 do_ldrd_abort 28 do_ldrd_abort tmp=r2, insn=r3
29 tst r3, #1 << 20 @ check write 29 tst r3, #1 << 20 @ check write
30 orreq r1, r1, #1 << 11 30 orreq r1, r1, #1 << 11
31 mov pc, lr 31 mov pc, lr
diff --git a/arch/arm/mm/abort-ev5tj.S b/arch/arm/mm/abort-ev5tj.S
index bce68d601c8b..bcb58d2fc11a 100644
--- a/arch/arm/mm/abort-ev5tj.S
+++ b/arch/arm/mm/abort-ev5tj.S
@@ -25,9 +25,9 @@ ENTRY(v5tj_early_abort)
25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR 25 bic r1, r1, #1 << 11 | 1 << 10 @ clear bits 11 and 10 of FSR
26 tst r3, #PSR_J_BIT @ Java? 26 tst r3, #PSR_J_BIT @ Java?
27 movne pc, lr 27 movne pc, lr
28 do_thumb_abort 28 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
29 ldreq r3, [r2] @ read aborted ARM instruction 29 ldreq r3, [r2] @ read aborted ARM instruction
30 do_ldrd_abort 30 do_ldrd_abort tmp=r2, insn=r3
31 tst r3, #1 << 20 @ L = 0 -> write 31 tst r3, #1 << 20 @ L = 0 -> write
32 orreq r1, r1, #1 << 11 @ yes. 32 orreq r1, r1, #1 << 11 @ yes.
33 mov pc, lr 33 mov pc, lr
diff --git a/arch/arm/mm/abort-ev6.S b/arch/arm/mm/abort-ev6.S
index 1478aa522144..ef526e702a5c 100644
--- a/arch/arm/mm/abort-ev6.S
+++ b/arch/arm/mm/abort-ev6.S
@@ -35,12 +35,12 @@ ENTRY(v6_early_abort)
35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR 35 bic r1, r1, #1 << 11 @ clear bit 11 of FSR
36 tst r3, #PSR_J_BIT @ Java? 36 tst r3, #PSR_J_BIT @ Java?
37 movne pc, lr 37 movne pc, lr
38 do_thumb_abort 38 do_thumb_abort fsr=r1, pc=r2, psr=r3, tmp=r3
39 ldreq r3, [r2] @ read aborted ARM instruction 39 ldreq r3, [r2] @ read aborted ARM instruction
40#ifdef CONFIG_CPU_ENDIAN_BE8 40#ifdef CONFIG_CPU_ENDIAN_BE8
41 reveq r3, r3 41 reveq r3, r3
42#endif 42#endif
43 do_ldrd_abort 43 do_ldrd_abort tmp=r2, insn=r3
44 tst r3, #1 << 20 @ L = 0 -> write 44 tst r3, #1 << 20 @ L = 0 -> write
45 orreq r1, r1, #1 << 11 @ yes. 45 orreq r1, r1, #1 << 11 @ yes.
46 mov pc, lr 46 mov pc, lr
diff --git a/arch/arm/mm/abort-macro.S b/arch/arm/mm/abort-macro.S
index d7cb1bfa51a4..8d3b9f999d1e 100644
--- a/arch/arm/mm/abort-macro.S
+++ b/arch/arm/mm/abort-macro.S
@@ -9,33 +9,33 @@
9 * 9 *
10 */ 10 */
11 11
12 .macro do_thumb_abort 12 .macro do_thumb_abort, fsr, pc, psr, tmp
13 tst r3, #PSR_T_BIT 13 tst \psr, #PSR_T_BIT
14 beq not_thumb 14 beq not_thumb
15 ldrh r3, [r2] @ Read aborted Thumb instruction 15 ldrh \tmp, [\pc] @ Read aborted Thumb instruction
16 and r3, r3, # 0xfe00 @ Mask opcode field 16 and \tmp, \tmp, # 0xfe00 @ Mask opcode field
17 cmp r3, # 0x5600 @ Is it ldrsb? 17 cmp \tmp, # 0x5600 @ Is it ldrsb?
18 orreq r3, r3, #1 << 11 @ Set L-bit if yes 18 orreq \tmp, \tmp, #1 << 11 @ Set L-bit if yes
19 tst r3, #1 << 11 @ L = 0 -> write 19 tst \tmp, #1 << 11 @ L = 0 -> write
20 orreq r1, r1, #1 << 11 @ yes. 20 orreq \psr, \psr, #1 << 11 @ yes.
21 mov pc, lr 21 mov pc, lr
22not_thumb: 22not_thumb:
23 .endm 23 .endm
24 24
25/* 25/*
26 * We check for the following insturction encoding for LDRD. 26 * We check for the following instruction encoding for LDRD.
27 * 27 *
28 * [27:25] == 0 28 * [27:25] == 000
29 * [7:4] == 1101 29 * [7:4] == 1101
30 * [20] == 0 30 * [20] == 0
31 */ 31 */
32 .macro do_ldrd_abort 32 .macro do_ldrd_abort, tmp, insn
33 tst r3, #0x0e000000 @ [27:25] == 0 33 tst \insn, #0x0e000000 @ [27:25] == 0
34 bne not_ldrd 34 bne not_ldrd
35 and r2, r3, #0x000000f0 @ [7:4] == 1101 35 and \tmp, \insn, #0x000000f0 @ [7:4] == 1101
36 cmp r2, #0x000000d0 36 cmp \tmp, #0x000000d0
37 bne not_ldrd 37 bne not_ldrd
38 tst r3, #1 << 20 @ [20] == 0 38 tst \insn, #1 << 20 @ [20] == 0
39 moveq pc, lr 39 moveq pc, lr
40not_ldrd: 40not_ldrd:
41 .endm 41 .endm
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-19 07:04:37 -0400