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authorAndy Shevchenko <andriy.shevchenko@linux.intel.com>2014-11-05 11:34:48 -0500
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-11-11 17:44:19 -0500
commitbb32baf76e56cdb348633f4d789a93e81b975c47 (patch)
tree130155378cd033a9c1ea1f17578a56af0af23a26
parent6c17ee44d5240a247daef3cdc51a0c62d2b77d75 (diff)
dmaengine: dw: enable runtime PM
On runtime PM aware platforms the DMA have to manage its own power state. This patch enables runtime PM support and applies necessary calls wherever it's needed. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Vinod Koul <vinod.koul@intel.com> Tested-by: Scott Ashcroft <scott.ashcroft@talk21.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
-rw-r--r--drivers/dma/dw/core.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/drivers/dma/dw/core.c b/drivers/dma/dw/core.c
index 244722170410..380478562b7d 100644
--- a/drivers/dma/dw/core.c
+++ b/drivers/dma/dw/core.c
@@ -22,6 +22,7 @@
22#include <linux/mm.h> 22#include <linux/mm.h>
23#include <linux/module.h> 23#include <linux/module.h>
24#include <linux/slab.h> 24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
25 26
26#include "../dmaengine.h" 27#include "../dmaengine.h"
27#include "internal.h" 28#include "internal.h"
@@ -1504,6 +1505,9 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1504 dw->regs = chip->regs; 1505 dw->regs = chip->regs;
1505 chip->dw = dw; 1506 chip->dw = dw;
1506 1507
1508 pm_runtime_enable(chip->dev);
1509 pm_runtime_get_sync(chip->dev);
1510
1507 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS); 1511 dw_params = dma_read_byaddr(chip->regs, DW_PARAMS);
1508 autocfg = dw_params >> DW_PARAMS_EN & 0x1; 1512 autocfg = dw_params >> DW_PARAMS_EN & 0x1;
1509 1513
@@ -1667,11 +1671,14 @@ int dw_dma_probe(struct dw_dma_chip *chip, struct dw_dma_platform_data *pdata)
1667 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n", 1671 dev_info(chip->dev, "DesignWare DMA Controller, %d channels\n",
1668 nr_channels); 1672 nr_channels);
1669 1673
1674 pm_runtime_put_sync_suspend(chip->dev);
1675
1670 return 0; 1676 return 0;
1671 1677
1672err_dma_register: 1678err_dma_register:
1673 free_irq(chip->irq, dw); 1679 free_irq(chip->irq, dw);
1674err_pdata: 1680err_pdata:
1681 pm_runtime_put_sync_suspend(chip->dev);
1675 return err; 1682 return err;
1676} 1683}
1677EXPORT_SYMBOL_GPL(dw_dma_probe); 1684EXPORT_SYMBOL_GPL(dw_dma_probe);
@@ -1681,6 +1688,8 @@ int dw_dma_remove(struct dw_dma_chip *chip)
1681 struct dw_dma *dw = chip->dw; 1688 struct dw_dma *dw = chip->dw;
1682 struct dw_dma_chan *dwc, *_dwc; 1689 struct dw_dma_chan *dwc, *_dwc;
1683 1690
1691 pm_runtime_get_sync(chip->dev);
1692
1684 dw_dma_off(dw); 1693 dw_dma_off(dw);
1685 dma_async_device_unregister(&dw->dma); 1694 dma_async_device_unregister(&dw->dma);
1686 1695
@@ -1693,6 +1702,8 @@ int dw_dma_remove(struct dw_dma_chip *chip)
1693 channel_clear_bit(dw, CH_EN, dwc->mask); 1702 channel_clear_bit(dw, CH_EN, dwc->mask);
1694 } 1703 }
1695 1704
1705 pm_runtime_put_sync_suspend(chip->dev);
1706 pm_runtime_disable(chip->dev);
1696 return 0; 1707 return 0;
1697} 1708}
1698EXPORT_SYMBOL_GPL(dw_dma_remove); 1709EXPORT_SYMBOL_GPL(dw_dma_remove);