aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorJonas Gorski <jonas.gorski@gmail.com>2012-10-28 08:17:55 -0400
committerJohn Crispin <blogic@openwrt.org>2012-11-09 05:37:18 -0500
commitba00e2e5c24f447fb09437a99df697787103f0cd (patch)
tree89188f75eb09cca6daea06d327fa3689b1151fda
parent799faa626c71fbd92396abea28f7e3586de3c7f5 (diff)
MIPS: BCM63XX: use the new reset helper
Use the new reset helper where appropriate. Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Patchwork: http://patchwork.linux-mips.org/patch/4453 Signed-off-by: John Crispin <blogic@openwrt.org>
-rw-r--r--arch/mips/bcm63xx/clk.c19
-rw-r--r--arch/mips/pci/pci-bcm63xx.c19
2 files changed, 11 insertions, 27 deletions
diff --git a/arch/mips/bcm63xx/clk.c b/arch/mips/bcm63xx/clk.c
index 89a5fb077862..b9e948d59430 100644
--- a/arch/mips/bcm63xx/clk.c
+++ b/arch/mips/bcm63xx/clk.c
@@ -14,6 +14,7 @@
14#include <bcm63xx_cpu.h> 14#include <bcm63xx_cpu.h>
15#include <bcm63xx_io.h> 15#include <bcm63xx_io.h>
16#include <bcm63xx_regs.h> 16#include <bcm63xx_regs.h>
17#include <bcm63xx_reset.h>
17#include <bcm63xx_clk.h> 18#include <bcm63xx_clk.h>
18 19
19static DEFINE_MUTEX(clocks_mutex); 20static DEFINE_MUTEX(clocks_mutex);
@@ -124,15 +125,10 @@ static void enetsw_set(struct clk *clk, int enable)
124 CKCTL_6368_SWPKT_USB_EN | 125 CKCTL_6368_SWPKT_USB_EN |
125 CKCTL_6368_SWPKT_SAR_EN, enable); 126 CKCTL_6368_SWPKT_SAR_EN, enable);
126 if (enable) { 127 if (enable) {
127 u32 val;
128
129 /* reset switch core afer clock change */ 128 /* reset switch core afer clock change */
130 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); 129 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 1);
131 val &= ~SOFTRESET_6368_ENETSW_MASK;
132 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
133 msleep(10); 130 msleep(10);
134 val |= SOFTRESET_6368_ENETSW_MASK; 131 bcm63xx_core_set_reset(BCM63XX_RESET_ENETSW, 0);
135 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
136 msleep(10); 132 msleep(10);
137 } 133 }
138} 134}
@@ -222,15 +218,10 @@ static void xtm_set(struct clk *clk, int enable)
222 CKCTL_6368_SWPKT_SAR_EN, enable); 218 CKCTL_6368_SWPKT_SAR_EN, enable);
223 219
224 if (enable) { 220 if (enable) {
225 u32 val;
226
227 /* reset sar core afer clock change */ 221 /* reset sar core afer clock change */
228 val = bcm_perf_readl(PERF_SOFTRESET_6368_REG); 222 bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 1);
229 val &= ~SOFTRESET_6368_SAR_MASK;
230 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
231 mdelay(1); 223 mdelay(1);
232 val |= SOFTRESET_6368_SAR_MASK; 224 bcm63xx_core_set_reset(BCM63XX_RESET_SAR, 0);
233 bcm_perf_writel(val, PERF_SOFTRESET_6368_REG);
234 mdelay(1); 225 mdelay(1);
235 } 226 }
236} 227}
diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
index fa8c320936fe..ca179b6ff39b 100644
--- a/arch/mips/pci/pci-bcm63xx.c
+++ b/arch/mips/pci/pci-bcm63xx.c
@@ -14,6 +14,8 @@
14#include <linux/clk.h> 14#include <linux/clk.h>
15#include <asm/bootinfo.h> 15#include <asm/bootinfo.h>
16 16
17#include <bcm63xx_reset.h>
18
17#include "pci-bcm63xx.h" 19#include "pci-bcm63xx.h"
18 20
19/* 21/*
@@ -126,23 +128,14 @@ static void __init bcm63xx_reset_pcie(void)
126 bcm_misc_writel(val, MISC_SERDES_CTRL_REG); 128 bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
127 129
128 /* reset the PCIe core */ 130 /* reset the PCIe core */
129 val = bcm_perf_readl(PERF_SOFTRESET_6328_REG); 131 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
130 132 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 1);
131 val &= ~SOFTRESET_6328_PCIE_MASK;
132 val &= ~SOFTRESET_6328_PCIE_CORE_MASK;
133 val &= ~SOFTRESET_6328_PCIE_HARD_MASK;
134 val &= ~SOFTRESET_6328_PCIE_EXT_MASK;
135 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
136 mdelay(10); 133 mdelay(10);
137 134
138 val |= SOFTRESET_6328_PCIE_MASK; 135 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 0);
139 val |= SOFTRESET_6328_PCIE_CORE_MASK;
140 val |= SOFTRESET_6328_PCIE_HARD_MASK;
141 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
142 mdelay(10); 136 mdelay(10);
143 137
144 val |= SOFTRESET_6328_PCIE_EXT_MASK; 138 bcm63xx_core_set_reset(BCM63XX_RESET_PCIE_EXT, 0);
145 bcm_perf_writel(val, PERF_SOFTRESET_6328_REG);
146 mdelay(200); 139 mdelay(200);
147} 140}
148 141