aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
authorDaniel Lezcano <daniel.lezcano@linaro.org>2014-11-12 10:03:50 -0500
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>2014-11-12 15:17:27 -0500
commitb82b6cca488074da3852e8a54fde1d9f74bf1557 (patch)
tree20db4b6c0d6a0180610fa392f32db7aeea515321
parent206c5f60a3d902bc4b56dab2de3e88de5eb06108 (diff)
cpuidle: Invert CPUIDLE_FLAG_TIME_VALID logic
The only place where the time is invalid is when the ACPI_CSTATE_FFH entry method is not set. Otherwise for all the drivers, the time can be correctly measured. Instead of duplicating the CPUIDLE_FLAG_TIME_VALID flag in all the drivers for all the states, just invert the logic by replacing it by the flag CPUIDLE_FLAG_TIME_INVALID, hence we can set this flag only for the acpi idle driver, remove the former flag from all the drivers and invert the logic with this flag in the different governor. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Diffstat
-rw-r--r--arch/arm/include/asm/cpuidle.h1
-rw-r--r--arch/arm/mach-davinci/cpuidle.c1
-rw-r--r--arch/arm/mach-imx/cpuidle-imx5.c1
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6q.c3
-rw-r--r--arch/arm/mach-imx/cpuidle-imx6sl.c3
-rw-r--r--arch/arm/mach-omap2/cpuidle34xx.c7
-rw-r--r--arch/arm/mach-omap2/cpuidle44xx.c5
-rw-r--r--arch/arm/mach-s3c64xx/cpuidle.c1
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c4
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra114.c1
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra20.c3
-rw-r--r--arch/arm/mach-tegra/cpuidle-tegra30.c1
-rw-r--r--arch/mips/include/asm/idle.h1
-rw-r--r--arch/sh/kernel/cpu/shmobile/cpuidle.c3
-rw-r--r--arch/x86/kernel/apm_32.c1
-rw-r--r--drivers/acpi/processor_idle.c6
-rw-r--r--drivers/cpuidle/cpuidle-arm64.c1
-rw-r--r--drivers/cpuidle/cpuidle-at91.c1
-rw-r--r--drivers/cpuidle/cpuidle-big_little.c6
-rw-r--r--drivers/cpuidle/cpuidle-calxeda.c1
-rw-r--r--drivers/cpuidle/cpuidle-cps.c7
-rw-r--r--drivers/cpuidle/cpuidle-exynos.c1
-rw-r--r--drivers/cpuidle/cpuidle-kirkwood.c1
-rw-r--r--drivers/cpuidle/cpuidle-mvebu-v7.c8
-rw-r--r--drivers/cpuidle/cpuidle-powernv.c6
-rw-r--r--drivers/cpuidle/cpuidle-pseries.c3
-rw-r--r--drivers/cpuidle/cpuidle-ux500.c3
-rw-r--r--drivers/cpuidle/cpuidle-zynq.c1
-rw-r--r--drivers/cpuidle/driver.c1
-rw-r--r--drivers/cpuidle/dt_idle_states.c2
-rw-r--r--drivers/cpuidle/governors/ladder.c2
-rw-r--r--drivers/cpuidle/governors/menu.c2
-rw-r--r--drivers/idle/intel_idle.c108
-rw-r--r--include/linux/cpuidle.h4
34 files changed, 75 insertions, 125 deletions
diff --git a/arch/arm/include/asm/cpuidle.h b/arch/arm/include/asm/cpuidle.h
index 2fca60ab513a..af319ac4960c 100644
--- a/arch/arm/include/asm/cpuidle.h
+++ b/arch/arm/include/asm/cpuidle.h
@@ -15,7 +15,6 @@ static inline int arm_cpuidle_simple_enter(struct cpuidle_device *dev,
15 .exit_latency = 1,\ 15 .exit_latency = 1,\
16 .target_residency = 1,\ 16 .target_residency = 1,\
17 .power_usage = p,\ 17 .power_usage = p,\
18 .flags = CPUIDLE_FLAG_TIME_VALID,\
19 .name = "WFI",\ 18 .name = "WFI",\
20 .desc = "ARM WFI",\ 19 .desc = "ARM WFI",\
21} 20}
diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c
index f1ac1c94ac0f..b4675fc28f83 100644
--- a/arch/arm/mach-davinci/cpuidle.c
+++ b/arch/arm/mach-davinci/cpuidle.c
@@ -66,7 +66,6 @@ static struct cpuidle_driver davinci_idle_driver = {
66 .enter = davinci_enter_idle, 66 .enter = davinci_enter_idle,
67 .exit_latency = 10, 67 .exit_latency = 10,
68 .target_residency = 10000, 68 .target_residency = 10000,
69 .flags = CPUIDLE_FLAG_TIME_VALID,
70 .name = "DDR SR", 69 .name = "DDR SR",
71 .desc = "WFI and DDR Self Refresh", 70 .desc = "WFI and DDR Self Refresh",
72 }, 71 },
diff --git a/arch/arm/mach-imx/cpuidle-imx5.c b/arch/arm/mach-imx/cpuidle-imx5.c
index 5a47e3c6172f..3feca526d16b 100644
--- a/arch/arm/mach-imx/cpuidle-imx5.c
+++ b/arch/arm/mach-imx/cpuidle-imx5.c
@@ -24,7 +24,6 @@ static struct cpuidle_driver imx5_cpuidle_driver = {
24 .enter = imx5_cpuidle_enter, 24 .enter = imx5_cpuidle_enter,
25 .exit_latency = 2, 25 .exit_latency = 2,
26 .target_residency = 1, 26 .target_residency = 1,
27 .flags = CPUIDLE_FLAG_TIME_VALID,
28 .name = "IMX5 SRPG", 27 .name = "IMX5 SRPG",
29 .desc = "CPU state retained,powered off", 28 .desc = "CPU state retained,powered off",
30 }, 29 },
diff --git a/arch/arm/mach-imx/cpuidle-imx6q.c b/arch/arm/mach-imx/cpuidle-imx6q.c
index aa935787b743..d76d08623f9f 100644
--- a/arch/arm/mach-imx/cpuidle-imx6q.c
+++ b/arch/arm/mach-imx/cpuidle-imx6q.c
@@ -53,8 +53,7 @@ static struct cpuidle_driver imx6q_cpuidle_driver = {
53 { 53 {
54 .exit_latency = 50, 54 .exit_latency = 50,
55 .target_residency = 75, 55 .target_residency = 75,
56 .flags = CPUIDLE_FLAG_TIME_VALID | 56 .flags = CPUIDLE_FLAG_TIMER_STOP,
57 CPUIDLE_FLAG_TIMER_STOP,
58 .enter = imx6q_enter_wait, 57 .enter = imx6q_enter_wait,
59 .name = "WAIT", 58 .name = "WAIT",
60 .desc = "Clock off", 59 .desc = "Clock off",
diff --git a/arch/arm/mach-imx/cpuidle-imx6sl.c b/arch/arm/mach-imx/cpuidle-imx6sl.c
index d4b6b8171fa9..7d92e6584551 100644
--- a/arch/arm/mach-imx/cpuidle-imx6sl.c
+++ b/arch/arm/mach-imx/cpuidle-imx6sl.c
@@ -40,8 +40,7 @@ static struct cpuidle_driver imx6sl_cpuidle_driver = {
40 { 40 {
41 .exit_latency = 50, 41 .exit_latency = 50,
42 .target_residency = 75, 42 .target_residency = 75,
43 .flags = CPUIDLE_FLAG_TIME_VALID | 43 .flags = CPUIDLE_FLAG_TIMER_STOP,
44 CPUIDLE_FLAG_TIMER_STOP,
45 .enter = imx6sl_enter_wait, 44 .enter = imx6sl_enter_wait,
46 .name = "WAIT", 45 .name = "WAIT",
47 .desc = "Clock off", 46 .desc = "Clock off",
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index e18709d3b95d..aa7b379e2661 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -265,7 +265,6 @@ static struct cpuidle_driver omap3_idle_driver = {
265 .enter = omap3_enter_idle_bm, 265 .enter = omap3_enter_idle_bm,
266 .exit_latency = 2 + 2, 266 .exit_latency = 2 + 2,
267 .target_residency = 5, 267 .target_residency = 5,
268 .flags = CPUIDLE_FLAG_TIME_VALID,
269 .name = "C1", 268 .name = "C1",
270 .desc = "MPU ON + CORE ON", 269 .desc = "MPU ON + CORE ON",
271 }, 270 },
@@ -273,7 +272,6 @@ static struct cpuidle_driver omap3_idle_driver = {
273 .enter = omap3_enter_idle_bm, 272 .enter = omap3_enter_idle_bm,
274 .exit_latency = 10 + 10, 273 .exit_latency = 10 + 10,
275 .target_residency = 30, 274 .target_residency = 30,
276 .flags = CPUIDLE_FLAG_TIME_VALID,
277 .name = "C2", 275 .name = "C2",
278 .desc = "MPU ON + CORE ON", 276 .desc = "MPU ON + CORE ON",
279 }, 277 },
@@ -281,7 +279,6 @@ static struct cpuidle_driver omap3_idle_driver = {
281 .enter = omap3_enter_idle_bm, 279 .enter = omap3_enter_idle_bm,
282 .exit_latency = 50 + 50, 280 .exit_latency = 50 + 50,
283 .target_residency = 300, 281 .target_residency = 300,
284 .flags = CPUIDLE_FLAG_TIME_VALID,
285 .name = "C3", 282 .name = "C3",
286 .desc = "MPU RET + CORE ON", 283 .desc = "MPU RET + CORE ON",
287 }, 284 },
@@ -289,7 +286,6 @@ static struct cpuidle_driver omap3_idle_driver = {
289 .enter = omap3_enter_idle_bm, 286 .enter = omap3_enter_idle_bm,
290 .exit_latency = 1500 + 1800, 287 .exit_latency = 1500 + 1800,
291 .target_residency = 4000, 288 .target_residency = 4000,
292 .flags = CPUIDLE_FLAG_TIME_VALID,
293 .name = "C4", 289 .name = "C4",
294 .desc = "MPU OFF + CORE ON", 290 .desc = "MPU OFF + CORE ON",
295 }, 291 },
@@ -297,7 +293,6 @@ static struct cpuidle_driver omap3_idle_driver = {
297 .enter = omap3_enter_idle_bm, 293 .enter = omap3_enter_idle_bm,
298 .exit_latency = 2500 + 7500, 294 .exit_latency = 2500 + 7500,
299 .target_residency = 12000, 295 .target_residency = 12000,
300 .flags = CPUIDLE_FLAG_TIME_VALID,
301 .name = "C5", 296 .name = "C5",
302 .desc = "MPU RET + CORE RET", 297 .desc = "MPU RET + CORE RET",
303 }, 298 },
@@ -305,7 +300,6 @@ static struct cpuidle_driver omap3_idle_driver = {
305 .enter = omap3_enter_idle_bm, 300 .enter = omap3_enter_idle_bm,
306 .exit_latency = 3000 + 8500, 301 .exit_latency = 3000 + 8500,
307 .target_residency = 15000, 302 .target_residency = 15000,
308 .flags = CPUIDLE_FLAG_TIME_VALID,
309 .name = "C6", 303 .name = "C6",
310 .desc = "MPU OFF + CORE RET", 304 .desc = "MPU OFF + CORE RET",
311 }, 305 },
@@ -313,7 +307,6 @@ static struct cpuidle_driver omap3_idle_driver = {
313 .enter = omap3_enter_idle_bm, 307 .enter = omap3_enter_idle_bm,
314 .exit_latency = 10000 + 30000, 308 .exit_latency = 10000 + 30000,
315 .target_residency = 30000, 309 .target_residency = 30000,
316 .flags = CPUIDLE_FLAG_TIME_VALID,
317 .name = "C7", 310 .name = "C7",
318 .desc = "MPU OFF + CORE OFF", 311 .desc = "MPU OFF + CORE OFF",
319 }, 312 },
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 2498ab025fa2..01e398a868bc 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -196,7 +196,6 @@ static struct cpuidle_driver omap4_idle_driver = {
196 /* C1 - CPU0 ON + CPU1 ON + MPU ON */ 196 /* C1 - CPU0 ON + CPU1 ON + MPU ON */
197 .exit_latency = 2 + 2, 197 .exit_latency = 2 + 2,
198 .target_residency = 5, 198 .target_residency = 5,
199 .flags = CPUIDLE_FLAG_TIME_VALID,
200 .enter = omap_enter_idle_simple, 199 .enter = omap_enter_idle_simple,
201 .name = "C1", 200 .name = "C1",
202 .desc = "CPUx ON, MPUSS ON" 201 .desc = "CPUx ON, MPUSS ON"
@@ -205,7 +204,7 @@ static struct cpuidle_driver omap4_idle_driver = {
205 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */ 204 /* C2 - CPU0 OFF + CPU1 OFF + MPU CSWR */
206 .exit_latency = 328 + 440, 205 .exit_latency = 328 + 440,
207 .target_residency = 960, 206 .target_residency = 960,
208 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, 207 .flags = CPUIDLE_FLAG_COUPLED,
209 .enter = omap_enter_idle_coupled, 208 .enter = omap_enter_idle_coupled,
210 .name = "C2", 209 .name = "C2",
211 .desc = "CPUx OFF, MPUSS CSWR", 210 .desc = "CPUx OFF, MPUSS CSWR",
@@ -214,7 +213,7 @@ static struct cpuidle_driver omap4_idle_driver = {
214 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */ 213 /* C3 - CPU0 OFF + CPU1 OFF + MPU OSWR */
215 .exit_latency = 460 + 518, 214 .exit_latency = 460 + 518,
216 .target_residency = 1100, 215 .target_residency = 1100,
217 .flags = CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_COUPLED, 216 .flags = CPUIDLE_FLAG_COUPLED,
218 .enter = omap_enter_idle_coupled, 217 .enter = omap_enter_idle_coupled,
219 .name = "C3", 218 .name = "C3",
220 .desc = "CPUx OFF, MPUSS OSWR", 219 .desc = "CPUx OFF, MPUSS OSWR",
diff --git a/arch/arm/mach-s3c64xx/cpuidle.c b/arch/arm/mach-s3c64xx/cpuidle.c
index 3c8ab07c2012..2eb072440dfa 100644
--- a/arch/arm/mach-s3c64xx/cpuidle.c
+++ b/arch/arm/mach-s3c64xx/cpuidle.c
@@ -48,7 +48,6 @@ static struct cpuidle_driver s3c64xx_cpuidle_driver = {
48 .enter = s3c64xx_enter_idle, 48 .enter = s3c64xx_enter_idle,
49 .exit_latency = 1, 49 .exit_latency = 1,
50 .target_residency = 1, 50 .target_residency = 1,
51 .flags = CPUIDLE_FLAG_TIME_VALID,
52 .name = "IDLE", 51 .name = "IDLE",
53 .desc = "System active, ARM gated", 52 .desc = "System active, ARM gated",
54 }, 53 },
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
index 7e5c2676c489..0e37da654ed5 100644
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -423,7 +423,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
423 .desc = "Core Standby Mode", 423 .desc = "Core Standby Mode",
424 .exit_latency = 10, 424 .exit_latency = 10,
425 .target_residency = 20 + 10, 425 .target_residency = 20 + 10,
426 .flags = CPUIDLE_FLAG_TIME_VALID,
427 .enter = sh7372_enter_core_standby, 426 .enter = sh7372_enter_core_standby,
428 }, 427 },
429 .states[2] = { 428 .states[2] = {
@@ -431,7 +430,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
431 .desc = "A3SM PLL ON", 430 .desc = "A3SM PLL ON",
432 .exit_latency = 20, 431 .exit_latency = 20,
433 .target_residency = 30 + 20, 432 .target_residency = 30 + 20,
434 .flags = CPUIDLE_FLAG_TIME_VALID,
435 .enter = sh7372_enter_a3sm_pll_on, 433 .enter = sh7372_enter_a3sm_pll_on,
436 }, 434 },
437 .states[3] = { 435 .states[3] = {
@@ -439,7 +437,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
439 .desc = "A3SM PLL OFF", 437 .desc = "A3SM PLL OFF",
440 .exit_latency = 120, 438 .exit_latency = 120,
441 .target_residency = 30 + 120, 439 .target_residency = 30 + 120,
442 .flags = CPUIDLE_FLAG_TIME_VALID,
443 .enter = sh7372_enter_a3sm_pll_off, 440 .enter = sh7372_enter_a3sm_pll_off,
444 }, 441 },
445 .states[4] = { 442 .states[4] = {
@@ -447,7 +444,6 @@ static struct cpuidle_driver sh7372_cpuidle_driver = {
447 .desc = "A4S PLL OFF", 444 .desc = "A4S PLL OFF",
448 .exit_latency = 240, 445 .exit_latency = 240,
449 .target_residency = 30 + 240, 446 .target_residency = 30 + 240,
450 .flags = CPUIDLE_FLAG_TIME_VALID,
451 .enter = sh7372_enter_a4s, 447 .enter = sh7372_enter_a4s,
452 .disabled = true, 448 .disabled = true,
453 }, 449 },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra114.c b/arch/arm/mach-tegra/cpuidle-tegra114.c
index e3ebdce3e71f..b30908235d52 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra114.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra114.c
@@ -75,7 +75,6 @@ static struct cpuidle_driver tegra_idle_driver = {
75 .exit_latency = 500, 75 .exit_latency = 500,
76 .target_residency = 1000, 76 .target_residency = 1000,
77 .power_usage = 0, 77 .power_usage = 0,
78 .flags = CPUIDLE_FLAG_TIME_VALID,
79 .name = "powered-down", 78 .name = "powered-down",
80 .desc = "CPU power gated", 79 .desc = "CPU power gated",
81 }, 80 },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra20.c b/arch/arm/mach-tegra/cpuidle-tegra20.c
index b30bf5cba65b..4f25a7c7ca0f 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra20.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra20.c
@@ -59,8 +59,7 @@ static struct cpuidle_driver tegra_idle_driver = {
59 .exit_latency = 5000, 59 .exit_latency = 5000,
60 .target_residency = 10000, 60 .target_residency = 10000,
61 .power_usage = 0, 61 .power_usage = 0,
62 .flags = CPUIDLE_FLAG_TIME_VALID | 62 .flags = CPUIDLE_FLAG_COUPLED,
63 CPUIDLE_FLAG_COUPLED,
64 .name = "powered-down", 63 .name = "powered-down",
65 .desc = "CPU power gated", 64 .desc = "CPU power gated",
66 }, 65 },
diff --git a/arch/arm/mach-tegra/cpuidle-tegra30.c b/arch/arm/mach-tegra/cpuidle-tegra30.c
index 35561274f6cf..f8815ed65d9d 100644
--- a/arch/arm/mach-tegra/cpuidle-tegra30.c
+++ b/arch/arm/mach-tegra/cpuidle-tegra30.c
@@ -56,7 +56,6 @@ static struct cpuidle_driver tegra_idle_driver = {
56 .exit_latency = 2000, 56 .exit_latency = 2000,
57 .target_residency = 2200, 57 .target_residency = 2200,
58 .power_usage = 0, 58 .power_usage = 0,
59 .flags = CPUIDLE_FLAG_TIME_VALID,
60 .name = "powered-down", 59 .name = "powered-down",
61 .desc = "CPU power gated", 60 .desc = "CPU power gated",
62 }, 61 },
diff --git a/arch/mips/include/asm/idle.h b/arch/mips/include/asm/idle.h
index 1c967abd545c..a2d18ab57ac6 100644
--- a/arch/mips/include/asm/idle.h
+++ b/arch/mips/include/asm/idle.h
@@ -22,7 +22,6 @@ extern int mips_cpuidle_wait_enter(struct cpuidle_device *dev,
22 .exit_latency = 1,\ 22 .exit_latency = 1,\
23 .target_residency = 1,\ 23 .target_residency = 1,\
24 .power_usage = UINT_MAX,\ 24 .power_usage = UINT_MAX,\
25 .flags = CPUIDLE_FLAG_TIME_VALID,\
26 .name = "wait",\ 25 .name = "wait",\
27 .desc = "MIPS wait",\ 26 .desc = "MIPS wait",\
28} 27}
diff --git a/arch/sh/kernel/cpu/shmobile/cpuidle.c b/arch/sh/kernel/cpu/shmobile/cpuidle.c
index e3abfd4277e2..53b8eeb1db20 100644
--- a/arch/sh/kernel/cpu/shmobile/cpuidle.c
+++ b/arch/sh/kernel/cpu/shmobile/cpuidle.c
@@ -59,7 +59,6 @@ static struct cpuidle_driver cpuidle_driver = {
59 .exit_latency = 1, 59 .exit_latency = 1,
60 .target_residency = 1 * 2, 60 .target_residency = 1 * 2,
61 .power_usage = 3, 61 .power_usage = 3,
62 .flags = CPUIDLE_FLAG_TIME_VALID,
63 .enter = cpuidle_sleep_enter, 62 .enter = cpuidle_sleep_enter,
64 .name = "C1", 63 .name = "C1",
65 .desc = "SuperH Sleep Mode", 64 .desc = "SuperH Sleep Mode",
@@ -68,7 +67,6 @@ static struct cpuidle_driver cpuidle_driver = {
68 .exit_latency = 100, 67 .exit_latency = 100,
69 .target_residency = 1 * 2, 68 .target_residency = 1 * 2,
70 .power_usage = 1, 69 .power_usage = 1,
71 .flags = CPUIDLE_FLAG_TIME_VALID,
72 .enter = cpuidle_sleep_enter, 70 .enter = cpuidle_sleep_enter,
73 .name = "C2", 71 .name = "C2",
74 .desc = "SuperH Sleep Mode [SF]", 72 .desc = "SuperH Sleep Mode [SF]",
@@ -78,7 +76,6 @@ static struct cpuidle_driver cpuidle_driver = {
78 .exit_latency = 2300, 76 .exit_latency = 2300,
79 .target_residency = 1 * 2, 77 .target_residency = 1 * 2,
80 .power_usage = 1, 78 .power_usage = 1,
81 .flags = CPUIDLE_FLAG_TIME_VALID,
82 .enter = cpuidle_sleep_enter, 79 .enter = cpuidle_sleep_enter,
83 .name = "C3", 80 .name = "C3",
84 .desc = "SuperH Mobile Standby Mode [SF]", 81 .desc = "SuperH Mobile Standby Mode [SF]",
diff --git a/arch/x86/kernel/apm_32.c b/arch/x86/kernel/apm_32.c
index 584874451414..927ec9235947 100644
--- a/arch/x86/kernel/apm_32.c
+++ b/arch/x86/kernel/apm_32.c
@@ -378,7 +378,6 @@ static struct cpuidle_driver apm_idle_driver = {
378 { /* entry 1 is for APM idle */ 378 { /* entry 1 is for APM idle */
379 .name = "APM", 379 .name = "APM",
380 .desc = "APM idle", 380 .desc = "APM idle",
381 .flags = CPUIDLE_FLAG_TIME_VALID,
382 .exit_latency = 250, /* WAG */ 381 .exit_latency = 250, /* WAG */
383 .target_residency = 500, /* WAG */ 382 .target_residency = 500, /* WAG */
384 .enter = &apm_cpu_idle 383 .enter = &apm_cpu_idle
diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 17f9ec501972..380b4b43f361 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -985,8 +985,8 @@ static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr)
985 state->flags = 0; 985 state->flags = 0;
986 switch (cx->type) { 986 switch (cx->type) {
987 case ACPI_STATE_C1: 987 case ACPI_STATE_C1:
988 if (cx->entry_method == ACPI_CSTATE_FFH) 988 if (cx->entry_method != ACPI_CSTATE_FFH)
989 state->flags |= CPUIDLE_FLAG_TIME_VALID; 989 state->flags |= CPUIDLE_FLAG_TIME_INVALID;
990 990
991 state->enter = acpi_idle_enter_c1; 991 state->enter = acpi_idle_enter_c1;
992 state->enter_dead = acpi_idle_play_dead; 992 state->enter_dead = acpi_idle_play_dead;
@@ -994,14 +994,12 @@ static int acpi_processor_setup_cpuidle_states(struct acpi_processor *pr)
994 break; 994 break;
995 995
996 case ACPI_STATE_C2: 996 case ACPI_STATE_C2:
997 state->flags |= CPUIDLE_FLAG_TIME_VALID;
998 state->enter = acpi_idle_enter_simple; 997 state->enter = acpi_idle_enter_simple;
999 state->enter_dead = acpi_idle_play_dead; 998 state->enter_dead = acpi_idle_play_dead;
1000 drv->safe_state_index = count; 999 drv->safe_state_index = count;
1001 break; 1000 break;
1002 1001
1003 case ACPI_STATE_C3: 1002 case ACPI_STATE_C3:
1004 state->flags |= CPUIDLE_FLAG_TIME_VALID;
1005 state->enter = pr->flags.bm_check ? 1003 state->enter = pr->flags.bm_check ?
1006 acpi_idle_enter_bm : 1004 acpi_idle_enter_bm :
1007 acpi_idle_enter_simple; 1005 acpi_idle_enter_simple;
diff --git a/drivers/cpuidle/cpuidle-arm64.c b/drivers/cpuidle/cpuidle-arm64.c
index 50997ea942fc..87320e62c721 100644
--- a/drivers/cpuidle/cpuidle-arm64.c
+++ b/drivers/cpuidle/cpuidle-arm64.c
@@ -73,7 +73,6 @@ static struct cpuidle_driver arm64_idle_driver = {
73 .exit_latency = 1, 73 .exit_latency = 1,
74 .target_residency = 1, 74 .target_residency = 1,
75 .power_usage = UINT_MAX, 75 .power_usage = UINT_MAX,
76 .flags = CPUIDLE_FLAG_TIME_VALID,
77 .name = "WFI", 76 .name = "WFI",
78 .desc = "ARM64 WFI", 77 .desc = "ARM64 WFI",
79 } 78 }
diff --git a/drivers/cpuidle/cpuidle-at91.c b/drivers/cpuidle/cpuidle-at91.c
index a0774370c6bc..1964ff07117c 100644
--- a/drivers/cpuidle/cpuidle-at91.c
+++ b/drivers/cpuidle/cpuidle-at91.c
@@ -43,7 +43,6 @@ static struct cpuidle_driver at91_idle_driver = {
43 .enter = at91_enter_idle, 43 .enter = at91_enter_idle,
44 .exit_latency = 10, 44 .exit_latency = 10,
45 .target_residency = 10000, 45 .target_residency = 10000,
46 .flags = CPUIDLE_FLAG_TIME_VALID,
47 .name = "RAM_SR", 46 .name = "RAM_SR",
48 .desc = "WFI and DDR Self Refresh", 47 .desc = "WFI and DDR Self Refresh",
49 }, 48 },
diff --git a/drivers/cpuidle/cpuidle-big_little.c b/drivers/cpuidle/cpuidle-big_little.c
index fbc00a1d3c48..e3e225fe6b45 100644
--- a/drivers/cpuidle/cpuidle-big_little.c
+++ b/drivers/cpuidle/cpuidle-big_little.c
@@ -67,8 +67,7 @@ static struct cpuidle_driver bl_idle_little_driver = {
67 .enter = bl_enter_powerdown, 67 .enter = bl_enter_powerdown,
68 .exit_latency = 700, 68 .exit_latency = 700,
69 .target_residency = 2500, 69 .target_residency = 2500,
70 .flags = CPUIDLE_FLAG_TIME_VALID | 70 .flags = CPUIDLE_FLAG_TIMER_STOP,
71 CPUIDLE_FLAG_TIMER_STOP,
72 .name = "C1", 71 .name = "C1",
73 .desc = "ARM little-cluster power down", 72 .desc = "ARM little-cluster power down",
74 }, 73 },
@@ -89,8 +88,7 @@ static struct cpuidle_driver bl_idle_big_driver = {
89 .enter = bl_enter_powerdown, 88 .enter = bl_enter_powerdown,
90 .exit_latency = 500, 89 .exit_latency = 500,
91 .target_residency = 2000, 90 .target_residency = 2000,
92 .flags = CPUIDLE_FLAG_TIME_VALID | 91 .flags = CPUIDLE_FLAG_TIMER_STOP,
93 CPUIDLE_FLAG_TIMER_STOP,
94 .name = "C1", 92 .name = "C1",
95 .desc = "ARM big-cluster power down", 93 .desc = "ARM big-cluster power down",
96 }, 94 },
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index 6e51114057d0..6541b0bfdfaa 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -55,7 +55,6 @@ static struct cpuidle_driver calxeda_idle_driver = {
55 { 55 {
56 .name = "PG", 56 .name = "PG",
57 .desc = "Power Gate", 57 .desc = "Power Gate",
58 .flags = CPUIDLE_FLAG_TIME_VALID,
59 .exit_latency = 30, 58 .exit_latency = 30,
60 .power_usage = 50, 59 .power_usage = 50,
61 .target_residency = 200, 60 .target_residency = 200,
diff --git a/drivers/cpuidle/cpuidle-cps.c b/drivers/cpuidle/cpuidle-cps.c
index fc7b62720deb..1adb6980b707 100644
--- a/drivers/cpuidle/cpuidle-cps.c
+++ b/drivers/cpuidle/cpuidle-cps.c
@@ -79,7 +79,6 @@ static struct cpuidle_driver cps_driver = {
79 .enter = cps_nc_enter, 79 .enter = cps_nc_enter,
80 .exit_latency = 200, 80 .exit_latency = 200,
81 .target_residency = 450, 81 .target_residency = 450,
82 .flags = CPUIDLE_FLAG_TIME_VALID,
83 .name = "nc-wait", 82 .name = "nc-wait",
84 .desc = "non-coherent MIPS wait", 83 .desc = "non-coherent MIPS wait",
85 }, 84 },
@@ -87,8 +86,7 @@ static struct cpuidle_driver cps_driver = {
87 .enter = cps_nc_enter, 86 .enter = cps_nc_enter,
88 .exit_latency = 300, 87 .exit_latency = 300,
89 .target_residency = 700, 88 .target_residency = 700,
90 .flags = CPUIDLE_FLAG_TIME_VALID | 89 .flags = CPUIDLE_FLAG_TIMER_STOP,
91 CPUIDLE_FLAG_TIMER_STOP,
92 .name = "clock-gated", 90 .name = "clock-gated",
93 .desc = "core clock gated", 91 .desc = "core clock gated",
94 }, 92 },
@@ -96,8 +94,7 @@ static struct cpuidle_driver cps_driver = {
96 .enter = cps_nc_enter, 94 .enter = cps_nc_enter,
97 .exit_latency = 600, 95 .exit_latency = 600,
98 .target_residency = 1000, 96 .target_residency = 1000,
99 .flags = CPUIDLE_FLAG_TIME_VALID | 97 .flags = CPUIDLE_FLAG_TIMER_STOP,
100 CPUIDLE_FLAG_TIMER_STOP,
101 .name = "power-gated", 98 .name = "power-gated",
102 .desc = "core power gated", 99 .desc = "core power gated",
103 }, 100 },
diff --git a/drivers/cpuidle/cpuidle-exynos.c b/drivers/cpuidle/cpuidle-exynos.c
index ba9b34b579f3..64d12a855ec6 100644
--- a/drivers/cpuidle/cpuidle-exynos.c
+++ b/drivers/cpuidle/cpuidle-exynos.c
@@ -47,7 +47,6 @@ static struct cpuidle_driver exynos_idle_driver = {
47 .enter = exynos_enter_lowpower, 47 .enter = exynos_enter_lowpower,
48 .exit_latency = 300, 48 .exit_latency = 300,
49 .target_residency = 100000, 49 .target_residency = 100000,
50 .flags = CPUIDLE_FLAG_TIME_VALID,
51 .name = "C1", 50 .name = "C1",
52 .desc = "ARM power down", 51 .desc = "ARM power down",
53 }, 52 },
diff --git a/drivers/cpuidle/cpuidle-kirkwood.c b/drivers/cpuidle/cpuidle-kirkwood.c
index 41ba843251b8..d88f8d7c2143 100644
--- a/drivers/cpuidle/cpuidle-kirkwood.c
+++ b/drivers/cpuidle/cpuidle-kirkwood.c
@@ -47,7 +47,6 @@ static struct cpuidle_driver kirkwood_idle_driver = {
47 .enter = kirkwood_enter_idle, 47 .enter = kirkwood_enter_idle,
48 .exit_latency = 10, 48 .exit_latency = 10,
49 .target_residency = 100000, 49 .target_residency = 100000,
50 .flags = CPUIDLE_FLAG_TIME_VALID,
51 .name = "DDR SR", 50 .name = "DDR SR",
52 .desc = "WFI and DDR Self Refresh", 51 .desc = "WFI and DDR Self Refresh",
53 }, 52 },
diff --git a/drivers/cpuidle/cpuidle-mvebu-v7.c b/drivers/cpuidle/cpuidle-mvebu-v7.c
index 45371bb16214..dd4c176df2a3 100644
--- a/drivers/cpuidle/cpuidle-mvebu-v7.c
+++ b/drivers/cpuidle/cpuidle-mvebu-v7.c
@@ -53,7 +53,6 @@ static struct cpuidle_driver armadaxp_idle_driver = {
53 .exit_latency = 10, 53 .exit_latency = 10,
54 .power_usage = 50, 54 .power_usage = 50,
55 .target_residency = 100, 55 .target_residency = 100,
56 .flags = CPUIDLE_FLAG_TIME_VALID,
57 .name = "MV CPU IDLE", 56 .name = "MV CPU IDLE",
58 .desc = "CPU power down", 57 .desc = "CPU power down",
59 }, 58 },
@@ -62,8 +61,7 @@ static struct cpuidle_driver armadaxp_idle_driver = {
62 .exit_latency = 100, 61 .exit_latency = 100,
63 .power_usage = 5, 62 .power_usage = 5,
64 .target_residency = 1000, 63 .target_residency = 1000,
65 .flags = CPUIDLE_FLAG_TIME_VALID | 64 .flags = MVEBU_V7_FLAG_DEEP_IDLE,
66 MVEBU_V7_FLAG_DEEP_IDLE,
67 .name = "MV CPU DEEP IDLE", 65 .name = "MV CPU DEEP IDLE",
68 .desc = "CPU and L2 Fabric power down", 66 .desc = "CPU and L2 Fabric power down",
69 }, 67 },
@@ -78,8 +76,7 @@ static struct cpuidle_driver armada370_idle_driver = {
78 .exit_latency = 100, 76 .exit_latency = 100,
79 .power_usage = 5, 77 .power_usage = 5,
80 .target_residency = 1000, 78 .target_residency = 1000,
81 .flags = (CPUIDLE_FLAG_TIME_VALID | 79 .flags = MVEBU_V7_FLAG_DEEP_IDLE,
82 MVEBU_V7_FLAG_DEEP_IDLE),
83 .name = "Deep Idle", 80 .name = "Deep Idle",
84 .desc = "CPU and L2 Fabric power down", 81 .desc = "CPU and L2 Fabric power down",
85 }, 82 },
@@ -94,7 +91,6 @@ static struct cpuidle_driver armada38x_idle_driver = {
94 .exit_latency = 10, 91 .exit_latency = 10,
95 .power_usage = 5, 92 .power_usage = 5,
96 .target_residency = 100, 93 .target_residency = 100,
97 .flags = CPUIDLE_FLAG_TIME_VALID,
98 .name = "Idle", 94 .name = "Idle",
99 .desc = "CPU and SCU power down", 95 .desc = "CPU and SCU power down",
100 }, 96 },
diff --git a/drivers/cpuidle/cpuidle-powernv.c b/drivers/cpuidle/cpuidle-powernv.c
index 7d3a3497dd4c..e9248bb9173a 100644
--- a/drivers/cpuidle/cpuidle-powernv.c
+++ b/drivers/cpuidle/cpuidle-powernv.c
@@ -93,7 +93,6 @@ static struct cpuidle_state powernv_states[MAX_POWERNV_IDLE_STATES] = {
93 { /* Snooze */ 93 { /* Snooze */
94 .name = "snooze", 94 .name = "snooze",
95 .desc = "snooze", 95 .desc = "snooze",
96 .flags = CPUIDLE_FLAG_TIME_VALID,
97 .exit_latency = 0, 96 .exit_latency = 0,
98 .target_residency = 0, 97 .target_residency = 0,
99 .enter = &snooze_loop }, 98 .enter = &snooze_loop },
@@ -202,7 +201,7 @@ static int powernv_add_idle_states(void)
202 /* Add NAP state */ 201 /* Add NAP state */
203 strcpy(powernv_states[nr_idle_states].name, "Nap"); 202 strcpy(powernv_states[nr_idle_states].name, "Nap");
204 strcpy(powernv_states[nr_idle_states].desc, "Nap"); 203 strcpy(powernv_states[nr_idle_states].desc, "Nap");
205 powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIME_VALID; 204 powernv_states[nr_idle_states].flags = 0;
206 powernv_states[nr_idle_states].exit_latency = 205 powernv_states[nr_idle_states].exit_latency =
207 ((unsigned int)latency_ns) / 1000; 206 ((unsigned int)latency_ns) / 1000;
208 powernv_states[nr_idle_states].target_residency = 207 powernv_states[nr_idle_states].target_residency =
@@ -215,8 +214,7 @@ static int powernv_add_idle_states(void)
215 /* Add FASTSLEEP state */ 214 /* Add FASTSLEEP state */
216 strcpy(powernv_states[nr_idle_states].name, "FastSleep"); 215 strcpy(powernv_states[nr_idle_states].name, "FastSleep");
217 strcpy(powernv_states[nr_idle_states].desc, "FastSleep"); 216 strcpy(powernv_states[nr_idle_states].desc, "FastSleep");
218 powernv_states[nr_idle_states].flags = 217 powernv_states[nr_idle_states].flags = CPUIDLE_FLAG_TIMER_STOP;
219 CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TIMER_STOP;
220 powernv_states[nr_idle_states].exit_latency = 218 powernv_states[nr_idle_states].exit_latency =
221 ((unsigned int)latency_ns) / 1000; 219 ((unsigned int)latency_ns) / 1000;
222 powernv_states[nr_idle_states].target_residency = 220 powernv_states[nr_idle_states].target_residency =
diff --git a/drivers/cpuidle/cpuidle-pseries.c b/drivers/cpuidle/cpuidle-pseries.c
index 6f7b01956885..bb9e2b6f3ecc 100644
--- a/drivers/cpuidle/cpuidle-pseries.c
+++ b/drivers/cpuidle/cpuidle-pseries.c
@@ -142,14 +142,12 @@ static struct cpuidle_state dedicated_states[] = {
142 { /* Snooze */ 142 { /* Snooze */
143 .name = "snooze", 143 .name = "snooze",
144 .desc = "snooze", 144 .desc = "snooze",
145 .flags = CPUIDLE_FLAG_TIME_VALID,
146 .exit_latency = 0, 145 .exit_latency = 0,
147 .target_residency = 0, 146 .target_residency = 0,
148 .enter = &snooze_loop }, 147 .enter = &snooze_loop },
149 { /* CEDE */ 148 { /* CEDE */
150 .name = "CEDE", 149 .name = "CEDE",
151 .desc = "CEDE", 150 .desc = "CEDE",
152 .flags = CPUIDLE_FLAG_TIME_VALID,
153 .exit_latency = 10, 151 .exit_latency = 10,
154 .target_residency = 100, 152 .target_residency = 100,
155 .enter = &dedicated_cede_loop }, 153 .enter = &dedicated_cede_loop },
@@ -162,7 +160,6 @@ static struct cpuidle_state shared_states[] = {
162 { /* Shared Cede */ 160 { /* Shared Cede */
163 .name = "Shared Cede", 161 .name = "Shared Cede",
164 .desc = "Shared Cede", 162 .desc = "Shared Cede",
165 .flags = CPUIDLE_FLAG_TIME_VALID,
166 .exit_latency = 0, 163 .exit_latency = 0,
167 .target_residency = 0, 164 .target_residency = 0,
168 .enter = &shared_cede_loop }, 165 .enter = &shared_cede_loop },
diff --git a/drivers/cpuidle/cpuidle-ux500.c b/drivers/cpuidle/cpuidle-ux500.c
index 5e35804b1a95..292e65a90308 100644
--- a/drivers/cpuidle/cpuidle-ux500.c
+++ b/drivers/cpuidle/cpuidle-ux500.c
@@ -101,8 +101,7 @@ static struct cpuidle_driver ux500_idle_driver = {
101 .enter = ux500_enter_idle, 101 .enter = ux500_enter_idle,
102 .exit_latency = 70, 102 .exit_latency = 70,
103 .target_residency = 260, 103 .target_residency = 260,
104 .flags = CPUIDLE_FLAG_TIME_VALID | 104 .flags = CPUIDLE_FLAG_TIMER_STOP,
105 CPUIDLE_FLAG_TIMER_STOP,
106 .name = "ApIdle", 105 .name = "ApIdle",
107 .desc = "ARM Retention", 106 .desc = "ARM Retention",
108 }, 107 },
diff --git a/drivers/cpuidle/cpuidle-zynq.c b/drivers/cpuidle/cpuidle-zynq.c
index c61b8b2a7c77..022dec86de8e 100644
--- a/drivers/cpuidle/cpuidle-zynq.c
+++ b/drivers/cpuidle/cpuidle-zynq.c
@@ -52,7 +52,6 @@ static struct cpuidle_driver zynq_idle_driver = {
52 .enter = zynq_enter_idle, 52 .enter = zynq_enter_idle,
53 .exit_latency = 10, 53 .exit_latency = 10,
54 .target_residency = 10000, 54 .target_residency = 10000,
55 .flags = CPUIDLE_FLAG_TIME_VALID,
56 .name = "RAM_SR", 55 .name = "RAM_SR",
57 .desc = "WFI and RAM Self Refresh", 56 .desc = "WFI and RAM Self Refresh",
58 }, 57 },
diff --git a/drivers/cpuidle/driver.c b/drivers/cpuidle/driver.c
index e431d11abf8d..2697e87d5b34 100644
--- a/drivers/cpuidle/driver.c
+++ b/drivers/cpuidle/driver.c
@@ -201,7 +201,6 @@ static void poll_idle_init(struct cpuidle_driver *drv)
201 state->exit_latency = 0; 201 state->exit_latency = 0;
202 state->target_residency = 0; 202 state->target_residency = 0;
203 state->power_usage = -1; 203 state->power_usage = -1;
204 state->flags = CPUIDLE_FLAG_TIME_VALID;
205 state->enter = poll_idle; 204 state->enter = poll_idle;
206 state->disabled = false; 205 state->disabled = false;
207} 206}
diff --git a/drivers/cpuidle/dt_idle_states.c b/drivers/cpuidle/dt_idle_states.c
index 52f4d11bbf3f..6e6f0b272835 100644
--- a/drivers/cpuidle/dt_idle_states.c
+++ b/drivers/cpuidle/dt_idle_states.c
@@ -73,7 +73,7 @@ static int init_state_node(struct cpuidle_state *idle_state,
73 return -EINVAL; 73 return -EINVAL;
74 } 74 }
75 75
76 idle_state->flags = CPUIDLE_FLAG_TIME_VALID; 76 idle_state->flags = 0;
77 if (of_property_read_bool(state_node, "local-timer-stop")) 77 if (of_property_read_bool(state_node, "local-timer-stop"))
78 idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP; 78 idle_state->flags |= CPUIDLE_FLAG_TIMER_STOP;
79 /* 79 /*
diff --git a/drivers/cpuidle/governors/ladder.c b/drivers/cpuidle/governors/ladder.c
index 06b57c4c4d80..37263d9a1051 100644
--- a/drivers/cpuidle/governors/ladder.c
+++ b/drivers/cpuidle/governors/ladder.c
@@ -79,7 +79,7 @@ static int ladder_select_state(struct cpuidle_driver *drv,
79 79
80 last_state = &ldev->states[last_idx]; 80 last_state = &ldev->states[last_idx];
81 81
82 if (drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_VALID) { 82 if (!(drv->states[last_idx].flags & CPUIDLE_FLAG_TIME_INVALID)) {
83 last_residency = cpuidle_get_last_residency(dev) - \ 83 last_residency = cpuidle_get_last_residency(dev) - \
84 drv->states[last_idx].exit_latency; 84 drv->states[last_idx].exit_latency;
85 } 85 }
diff --git a/drivers/cpuidle/governors/menu.c b/drivers/cpuidle/governors/menu.c
index 710a233b9b0d..659d7b0c9ebf 100644
--- a/drivers/cpuidle/governors/menu.c
+++ b/drivers/cpuidle/governors/menu.c
@@ -405,7 +405,7 @@ static void menu_update(struct cpuidle_driver *drv, struct cpuidle_device *dev)
405 * the measured amount of time is less than the exit latency, 405 * the measured amount of time is less than the exit latency,
406 * assume the state was never reached and the exit latency is 0. 406 * assume the state was never reached and the exit latency is 0.
407 */ 407 */
408 if (unlikely(!(target->flags & CPUIDLE_FLAG_TIME_VALID))) { 408 if (unlikely(target->flags & CPUIDLE_FLAG_TIME_INVALID)) {
409 /* Use timer value as is */ 409 /* Use timer value as is */
410 measured_us = data->next_timer_us; 410 measured_us = data->next_timer_us;
411 411
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 9b7ee7e427df..9cceacb92f9d 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -128,28 +128,28 @@ static struct cpuidle_state nehalem_cstates[] = {
128 { 128 {
129 .name = "C1-NHM", 129 .name = "C1-NHM",
130 .desc = "MWAIT 0x00", 130 .desc = "MWAIT 0x00",
131 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 131 .flags = MWAIT2flg(0x00),
132 .exit_latency = 3, 132 .exit_latency = 3,
133 .target_residency = 6, 133 .target_residency = 6,
134 .enter = &intel_idle }, 134 .enter = &intel_idle },
135 { 135 {
136 .name = "C1E-NHM", 136 .name = "C1E-NHM",
137 .desc = "MWAIT 0x01", 137 .desc = "MWAIT 0x01",
138 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 138 .flags = MWAIT2flg(0x01),
139 .exit_latency = 10, 139 .exit_latency = 10,
140 .target_residency = 20, 140 .target_residency = 20,
141 .enter = &intel_idle }, 141 .enter = &intel_idle },
142 { 142 {
143 .name = "C3-NHM", 143 .name = "C3-NHM",
144 .desc = "MWAIT 0x10", 144 .desc = "MWAIT 0x10",
145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 145 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
146 .exit_latency = 20, 146 .exit_latency = 20,
147 .target_residency = 80, 147 .target_residency = 80,
148 .enter = &intel_idle }, 148 .enter = &intel_idle },
149 { 149 {
150 .name = "C6-NHM", 150 .name = "C6-NHM",
151 .desc = "MWAIT 0x20", 151 .desc = "MWAIT 0x20",
152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 152 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
153 .exit_latency = 200, 153 .exit_latency = 200,
154 .target_residency = 800, 154 .target_residency = 800,
155 .enter = &intel_idle }, 155 .enter = &intel_idle },
@@ -161,35 +161,35 @@ static struct cpuidle_state snb_cstates[] = {
161 { 161 {
162 .name = "C1-SNB", 162 .name = "C1-SNB",
163 .desc = "MWAIT 0x00", 163 .desc = "MWAIT 0x00",
164 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 164 .flags = MWAIT2flg(0x00),
165 .exit_latency = 2, 165 .exit_latency = 2,
166 .target_residency = 2, 166 .target_residency = 2,
167 .enter = &intel_idle }, 167 .enter = &intel_idle },
168 { 168 {
169 .name = "C1E-SNB", 169 .name = "C1E-SNB",
170 .desc = "MWAIT 0x01", 170 .desc = "MWAIT 0x01",
171 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 171 .flags = MWAIT2flg(0x01),
172 .exit_latency = 10, 172 .exit_latency = 10,
173 .target_residency = 20, 173 .target_residency = 20,
174 .enter = &intel_idle }, 174 .enter = &intel_idle },
175 { 175 {
176 .name = "C3-SNB", 176 .name = "C3-SNB",
177 .desc = "MWAIT 0x10", 177 .desc = "MWAIT 0x10",
178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 178 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
179 .exit_latency = 80, 179 .exit_latency = 80,
180 .target_residency = 211, 180 .target_residency = 211,
181 .enter = &intel_idle }, 181 .enter = &intel_idle },
182 { 182 {
183 .name = "C6-SNB", 183 .name = "C6-SNB",
184 .desc = "MWAIT 0x20", 184 .desc = "MWAIT 0x20",
185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 185 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
186 .exit_latency = 104, 186 .exit_latency = 104,
187 .target_residency = 345, 187 .target_residency = 345,
188 .enter = &intel_idle }, 188 .enter = &intel_idle },
189 { 189 {
190 .name = "C7-SNB", 190 .name = "C7-SNB",
191 .desc = "MWAIT 0x30", 191 .desc = "MWAIT 0x30",
192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 192 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
193 .exit_latency = 109, 193 .exit_latency = 109,
194 .target_residency = 345, 194 .target_residency = 345,
195 .enter = &intel_idle }, 195 .enter = &intel_idle },
@@ -201,42 +201,42 @@ static struct cpuidle_state byt_cstates[] = {
201 { 201 {
202 .name = "C1-BYT", 202 .name = "C1-BYT",
203 .desc = "MWAIT 0x00", 203 .desc = "MWAIT 0x00",
204 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 204 .flags = MWAIT2flg(0x00),
205 .exit_latency = 1, 205 .exit_latency = 1,
206 .target_residency = 1, 206 .target_residency = 1,
207 .enter = &intel_idle }, 207 .enter = &intel_idle },
208 { 208 {
209 .name = "C1E-BYT", 209 .name = "C1E-BYT",
210 .desc = "MWAIT 0x01", 210 .desc = "MWAIT 0x01",
211 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 211 .flags = MWAIT2flg(0x01),
212 .exit_latency = 15, 212 .exit_latency = 15,
213 .target_residency = 30, 213 .target_residency = 30,
214 .enter = &intel_idle }, 214 .enter = &intel_idle },
215 { 215 {
216 .name = "C6N-BYT", 216 .name = "C6N-BYT",
217 .desc = "MWAIT 0x58", 217 .desc = "MWAIT 0x58",
218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 218 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
219 .exit_latency = 40, 219 .exit_latency = 40,
220 .target_residency = 275, 220 .target_residency = 275,
221 .enter = &intel_idle }, 221 .enter = &intel_idle },
222 { 222 {
223 .name = "C6S-BYT", 223 .name = "C6S-BYT",
224 .desc = "MWAIT 0x52", 224 .desc = "MWAIT 0x52",
225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 225 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
226 .exit_latency = 140, 226 .exit_latency = 140,
227 .target_residency = 560, 227 .target_residency = 560,
228 .enter = &intel_idle }, 228 .enter = &intel_idle },
229 { 229 {
230 .name = "C7-BYT", 230 .name = "C7-BYT",
231 .desc = "MWAIT 0x60", 231 .desc = "MWAIT 0x60",
232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 232 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
233 .exit_latency = 1200, 233 .exit_latency = 1200,
234 .target_residency = 1500, 234 .target_residency = 1500,
235 .enter = &intel_idle }, 235 .enter = &intel_idle },
236 { 236 {
237 .name = "C7S-BYT", 237 .name = "C7S-BYT",
238 .desc = "MWAIT 0x64", 238 .desc = "MWAIT 0x64",
239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 239 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 10000, 240 .exit_latency = 10000,
241 .target_residency = 20000, 241 .target_residency = 20000,
242 .enter = &intel_idle }, 242 .enter = &intel_idle },
@@ -248,35 +248,35 @@ static struct cpuidle_state ivb_cstates[] = {
248 { 248 {
249 .name = "C1-IVB", 249 .name = "C1-IVB",
250 .desc = "MWAIT 0x00", 250 .desc = "MWAIT 0x00",
251 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 251 .flags = MWAIT2flg(0x00),
252 .exit_latency = 1, 252 .exit_latency = 1,
253 .target_residency = 1, 253 .target_residency = 1,
254 .enter = &intel_idle }, 254 .enter = &intel_idle },
255 { 255 {
256 .name = "C1E-IVB", 256 .name = "C1E-IVB",
257 .desc = "MWAIT 0x01", 257 .desc = "MWAIT 0x01",
258 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 258 .flags = MWAIT2flg(0x01),
259 .exit_latency = 10, 259 .exit_latency = 10,
260 .target_residency = 20, 260 .target_residency = 20,
261 .enter = &intel_idle }, 261 .enter = &intel_idle },
262 { 262 {
263 .name = "C3-IVB", 263 .name = "C3-IVB",
264 .desc = "MWAIT 0x10", 264 .desc = "MWAIT 0x10",
265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 265 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
266 .exit_latency = 59, 266 .exit_latency = 59,
267 .target_residency = 156, 267 .target_residency = 156,
268 .enter = &intel_idle }, 268 .enter = &intel_idle },
269 { 269 {
270 .name = "C6-IVB", 270 .name = "C6-IVB",
271 .desc = "MWAIT 0x20", 271 .desc = "MWAIT 0x20",
272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 272 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
273 .exit_latency = 80, 273 .exit_latency = 80,
274 .target_residency = 300, 274 .target_residency = 300,
275 .enter = &intel_idle }, 275 .enter = &intel_idle },
276 { 276 {
277 .name = "C7-IVB", 277 .name = "C7-IVB",
278 .desc = "MWAIT 0x30", 278 .desc = "MWAIT 0x30",
279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 279 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
280 .exit_latency = 87, 280 .exit_latency = 87,
281 .target_residency = 300, 281 .target_residency = 300,
282 .enter = &intel_idle }, 282 .enter = &intel_idle },
@@ -288,28 +288,28 @@ static struct cpuidle_state ivt_cstates[] = {
288 { 288 {
289 .name = "C1-IVT", 289 .name = "C1-IVT",
290 .desc = "MWAIT 0x00", 290 .desc = "MWAIT 0x00",
291 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 291 .flags = MWAIT2flg(0x00),
292 .exit_latency = 1, 292 .exit_latency = 1,
293 .target_residency = 1, 293 .target_residency = 1,
294 .enter = &intel_idle }, 294 .enter = &intel_idle },
295 { 295 {
296 .name = "C1E-IVT", 296 .name = "C1E-IVT",
297 .desc = "MWAIT 0x01", 297 .desc = "MWAIT 0x01",
298 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 298 .flags = MWAIT2flg(0x01),
299 .exit_latency = 10, 299 .exit_latency = 10,
300 .target_residency = 80, 300 .target_residency = 80,
301 .enter = &intel_idle }, 301 .enter = &intel_idle },
302 { 302 {
303 .name = "C3-IVT", 303 .name = "C3-IVT",
304 .desc = "MWAIT 0x10", 304 .desc = "MWAIT 0x10",
305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 305 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
306 .exit_latency = 59, 306 .exit_latency = 59,
307 .target_residency = 156, 307 .target_residency = 156,
308 .enter = &intel_idle }, 308 .enter = &intel_idle },
309 { 309 {
310 .name = "C6-IVT", 310 .name = "C6-IVT",
311 .desc = "MWAIT 0x20", 311 .desc = "MWAIT 0x20",
312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 312 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
313 .exit_latency = 82, 313 .exit_latency = 82,
314 .target_residency = 300, 314 .target_residency = 300,
315 .enter = &intel_idle }, 315 .enter = &intel_idle },
@@ -321,28 +321,28 @@ static struct cpuidle_state ivt_cstates_4s[] = {
321 { 321 {
322 .name = "C1-IVT-4S", 322 .name = "C1-IVT-4S",
323 .desc = "MWAIT 0x00", 323 .desc = "MWAIT 0x00",
324 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 324 .flags = MWAIT2flg(0x00),
325 .exit_latency = 1, 325 .exit_latency = 1,
326 .target_residency = 1, 326 .target_residency = 1,
327 .enter = &intel_idle }, 327 .enter = &intel_idle },
328 { 328 {
329 .name = "C1E-IVT-4S", 329 .name = "C1E-IVT-4S",
330 .desc = "MWAIT 0x01", 330 .desc = "MWAIT 0x01",
331 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 331 .flags = MWAIT2flg(0x01),
332 .exit_latency = 10, 332 .exit_latency = 10,
333 .target_residency = 250, 333 .target_residency = 250,
334 .enter = &intel_idle }, 334 .enter = &intel_idle },
335 { 335 {
336 .name = "C3-IVT-4S", 336 .name = "C3-IVT-4S",
337 .desc = "MWAIT 0x10", 337 .desc = "MWAIT 0x10",
338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 338 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
339 .exit_latency = 59, 339 .exit_latency = 59,
340 .target_residency = 300, 340 .target_residency = 300,
341 .enter = &intel_idle }, 341 .enter = &intel_idle },
342 { 342 {
343 .name = "C6-IVT-4S", 343 .name = "C6-IVT-4S",
344 .desc = "MWAIT 0x20", 344 .desc = "MWAIT 0x20",
345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 345 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
346 .exit_latency = 84, 346 .exit_latency = 84,
347 .target_residency = 400, 347 .target_residency = 400,
348 .enter = &intel_idle }, 348 .enter = &intel_idle },
@@ -354,28 +354,28 @@ static struct cpuidle_state ivt_cstates_8s[] = {
354 { 354 {
355 .name = "C1-IVT-8S", 355 .name = "C1-IVT-8S",
356 .desc = "MWAIT 0x00", 356 .desc = "MWAIT 0x00",
357 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 357 .flags = MWAIT2flg(0x00),
358 .exit_latency = 1, 358 .exit_latency = 1,
359 .target_residency = 1, 359 .target_residency = 1,
360 .enter = &intel_idle }, 360 .enter = &intel_idle },
361 { 361 {
362 .name = "C1E-IVT-8S", 362 .name = "C1E-IVT-8S",
363 .desc = "MWAIT 0x01", 363 .desc = "MWAIT 0x01",
364 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 364 .flags = MWAIT2flg(0x01),
365 .exit_latency = 10, 365 .exit_latency = 10,
366 .target_residency = 500, 366 .target_residency = 500,
367 .enter = &intel_idle }, 367 .enter = &intel_idle },
368 { 368 {
369 .name = "C3-IVT-8S", 369 .name = "C3-IVT-8S",
370 .desc = "MWAIT 0x10", 370 .desc = "MWAIT 0x10",
371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 371 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
372 .exit_latency = 59, 372 .exit_latency = 59,
373 .target_residency = 600, 373 .target_residency = 600,
374 .enter = &intel_idle }, 374 .enter = &intel_idle },
375 { 375 {
376 .name = "C6-IVT-8S", 376 .name = "C6-IVT-8S",
377 .desc = "MWAIT 0x20", 377 .desc = "MWAIT 0x20",
378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 378 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
379 .exit_latency = 88, 379 .exit_latency = 88,
380 .target_residency = 700, 380 .target_residency = 700,
381 .enter = &intel_idle }, 381 .enter = &intel_idle },
@@ -387,56 +387,56 @@ static struct cpuidle_state hsw_cstates[] = {
387 { 387 {
388 .name = "C1-HSW", 388 .name = "C1-HSW",
389 .desc = "MWAIT 0x00", 389 .desc = "MWAIT 0x00",
390 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 390 .flags = MWAIT2flg(0x00),
391 .exit_latency = 2, 391 .exit_latency = 2,
392 .target_residency = 2, 392 .target_residency = 2,
393 .enter = &intel_idle }, 393 .enter = &intel_idle },
394 { 394 {
395 .name = "C1E-HSW", 395 .name = "C1E-HSW",
396 .desc = "MWAIT 0x01", 396 .desc = "MWAIT 0x01",
397 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 397 .flags = MWAIT2flg(0x01),
398 .exit_latency = 10, 398 .exit_latency = 10,
399 .target_residency = 20, 399 .target_residency = 20,
400 .enter = &intel_idle }, 400 .enter = &intel_idle },
401 { 401 {
402 .name = "C3-HSW", 402 .name = "C3-HSW",
403 .desc = "MWAIT 0x10", 403 .desc = "MWAIT 0x10",
404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 404 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
405 .exit_latency = 33, 405 .exit_latency = 33,
406 .target_residency = 100, 406 .target_residency = 100,
407 .enter = &intel_idle }, 407 .enter = &intel_idle },
408 { 408 {
409 .name = "C6-HSW", 409 .name = "C6-HSW",
410 .desc = "MWAIT 0x20", 410 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .exit_latency = 133, 412 .exit_latency = 133,
413 .target_residency = 400, 413 .target_residency = 400,
414 .enter = &intel_idle }, 414 .enter = &intel_idle },
415 { 415 {
416 .name = "C7s-HSW", 416 .name = "C7s-HSW",
417 .desc = "MWAIT 0x32", 417 .desc = "MWAIT 0x32",
418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 418 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
419 .exit_latency = 166, 419 .exit_latency = 166,
420 .target_residency = 500, 420 .target_residency = 500,
421 .enter = &intel_idle }, 421 .enter = &intel_idle },
422 { 422 {
423 .name = "C8-HSW", 423 .name = "C8-HSW",
424 .desc = "MWAIT 0x40", 424 .desc = "MWAIT 0x40",
425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 425 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
426 .exit_latency = 300, 426 .exit_latency = 300,
427 .target_residency = 900, 427 .target_residency = 900,
428 .enter = &intel_idle }, 428 .enter = &intel_idle },
429 { 429 {
430 .name = "C9-HSW", 430 .name = "C9-HSW",
431 .desc = "MWAIT 0x50", 431 .desc = "MWAIT 0x50",
432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 432 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
433 .exit_latency = 600, 433 .exit_latency = 600,
434 .target_residency = 1800, 434 .target_residency = 1800,
435 .enter = &intel_idle }, 435 .enter = &intel_idle },
436 { 436 {
437 .name = "C10-HSW", 437 .name = "C10-HSW",
438 .desc = "MWAIT 0x60", 438 .desc = "MWAIT 0x60",
439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 439 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
440 .exit_latency = 2600, 440 .exit_latency = 2600,
441 .target_residency = 7700, 441 .target_residency = 7700,
442 .enter = &intel_idle }, 442 .enter = &intel_idle },
@@ -447,56 +447,56 @@ static struct cpuidle_state bdw_cstates[] = {
447 { 447 {
448 .name = "C1-BDW", 448 .name = "C1-BDW",
449 .desc = "MWAIT 0x00", 449 .desc = "MWAIT 0x00",
450 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 450 .flags = MWAIT2flg(0x00),
451 .exit_latency = 2, 451 .exit_latency = 2,
452 .target_residency = 2, 452 .target_residency = 2,
453 .enter = &intel_idle }, 453 .enter = &intel_idle },
454 { 454 {
455 .name = "C1E-BDW", 455 .name = "C1E-BDW",
456 .desc = "MWAIT 0x01", 456 .desc = "MWAIT 0x01",
457 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_TIME_VALID, 457 .flags = MWAIT2flg(0x01),
458 .exit_latency = 10, 458 .exit_latency = 10,
459 .target_residency = 20, 459 .target_residency = 20,
460 .enter = &intel_idle }, 460 .enter = &intel_idle },
461 { 461 {
462 .name = "C3-BDW", 462 .name = "C3-BDW",
463 .desc = "MWAIT 0x10", 463 .desc = "MWAIT 0x10",
464 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 464 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
465 .exit_latency = 40, 465 .exit_latency = 40,
466 .target_residency = 100, 466 .target_residency = 100,
467 .enter = &intel_idle }, 467 .enter = &intel_idle },
468 { 468 {
469 .name = "C6-BDW", 469 .name = "C6-BDW",
470 .desc = "MWAIT 0x20", 470 .desc = "MWAIT 0x20",
471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 471 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
472 .exit_latency = 133, 472 .exit_latency = 133,
473 .target_residency = 400, 473 .target_residency = 400,
474 .enter = &intel_idle }, 474 .enter = &intel_idle },
475 { 475 {
476 .name = "C7s-BDW", 476 .name = "C7s-BDW",
477 .desc = "MWAIT 0x32", 477 .desc = "MWAIT 0x32",
478 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 478 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
479 .exit_latency = 166, 479 .exit_latency = 166,
480 .target_residency = 500, 480 .target_residency = 500,
481 .enter = &intel_idle }, 481 .enter = &intel_idle },
482 { 482 {
483 .name = "C8-BDW", 483 .name = "C8-BDW",
484 .desc = "MWAIT 0x40", 484 .desc = "MWAIT 0x40",
485 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 485 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .exit_latency = 300, 486 .exit_latency = 300,
487 .target_residency = 900, 487 .target_residency = 900,
488 .enter = &intel_idle }, 488 .enter = &intel_idle },
489 { 489 {
490 .name = "C9-BDW", 490 .name = "C9-BDW",
491 .desc = "MWAIT 0x50", 491 .desc = "MWAIT 0x50",
492 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 492 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
493 .exit_latency = 600, 493 .exit_latency = 600,
494 .target_residency = 1800, 494 .target_residency = 1800,
495 .enter = &intel_idle }, 495 .enter = &intel_idle },
496 { 496 {
497 .name = "C10-BDW", 497 .name = "C10-BDW",
498 .desc = "MWAIT 0x60", 498 .desc = "MWAIT 0x60",
499 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 499 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
500 .exit_latency = 2600, 500 .exit_latency = 2600,
501 .target_residency = 7700, 501 .target_residency = 7700,
502 .enter = &intel_idle }, 502 .enter = &intel_idle },
@@ -508,28 +508,28 @@ static struct cpuidle_state atom_cstates[] = {
508 { 508 {
509 .name = "C1E-ATM", 509 .name = "C1E-ATM",
510 .desc = "MWAIT 0x00", 510 .desc = "MWAIT 0x00",
511 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 511 .flags = MWAIT2flg(0x00),
512 .exit_latency = 10, 512 .exit_latency = 10,
513 .target_residency = 20, 513 .target_residency = 20,
514 .enter = &intel_idle }, 514 .enter = &intel_idle },
515 { 515 {
516 .name = "C2-ATM", 516 .name = "C2-ATM",
517 .desc = "MWAIT 0x10", 517 .desc = "MWAIT 0x10",
518 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TIME_VALID, 518 .flags = MWAIT2flg(0x10),
519 .exit_latency = 20, 519 .exit_latency = 20,
520 .target_residency = 80, 520 .target_residency = 80,
521 .enter = &intel_idle }, 521 .enter = &intel_idle },
522 { 522 {
523 .name = "C4-ATM", 523 .name = "C4-ATM",
524 .desc = "MWAIT 0x30", 524 .desc = "MWAIT 0x30",
525 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 525 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
526 .exit_latency = 100, 526 .exit_latency = 100,
527 .target_residency = 400, 527 .target_residency = 400,
528 .enter = &intel_idle }, 528 .enter = &intel_idle },
529 { 529 {
530 .name = "C6-ATM", 530 .name = "C6-ATM",
531 .desc = "MWAIT 0x52", 531 .desc = "MWAIT 0x52",
532 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 532 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
533 .exit_latency = 140, 533 .exit_latency = 140,
534 .target_residency = 560, 534 .target_residency = 560,
535 .enter = &intel_idle }, 535 .enter = &intel_idle },
@@ -540,14 +540,14 @@ static struct cpuidle_state avn_cstates[] = {
540 { 540 {
541 .name = "C1-AVN", 541 .name = "C1-AVN",
542 .desc = "MWAIT 0x00", 542 .desc = "MWAIT 0x00",
543 .flags = MWAIT2flg(0x00) | CPUIDLE_FLAG_TIME_VALID, 543 .flags = MWAIT2flg(0x00),
544 .exit_latency = 2, 544 .exit_latency = 2,
545 .target_residency = 2, 545 .target_residency = 2,
546 .enter = &intel_idle }, 546 .enter = &intel_idle },
547 { 547 {
548 .name = "C6-AVN", 548 .name = "C6-AVN",
549 .desc = "MWAIT 0x51", 549 .desc = "MWAIT 0x51",
550 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TIME_VALID | CPUIDLE_FLAG_TLB_FLUSHED, 550 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
551 .exit_latency = 15, 551 .exit_latency = 15,
552 .target_residency = 45, 552 .target_residency = 45,
553 .enter = &intel_idle }, 553 .enter = &intel_idle },
diff --git a/include/linux/cpuidle.h b/include/linux/cpuidle.h
index 25e0df6155a4..a07e087f54b2 100644
--- a/include/linux/cpuidle.h
+++ b/include/linux/cpuidle.h
@@ -53,7 +53,7 @@ struct cpuidle_state {
53}; 53};
54 54
55/* Idle State Flags */ 55/* Idle State Flags */
56#define CPUIDLE_FLAG_TIME_VALID (0x01) /* is residency time measurable? */ 56#define CPUIDLE_FLAG_TIME_INVALID (0x01) /* is residency time measurable? */
57#define CPUIDLE_FLAG_COUPLED (0x02) /* state applies to multiple cpus */ 57#define CPUIDLE_FLAG_COUPLED (0x02) /* state applies to multiple cpus */
58#define CPUIDLE_FLAG_TIMER_STOP (0x04) /* timer is stopped on this state */ 58#define CPUIDLE_FLAG_TIMER_STOP (0x04) /* timer is stopped on this state */
59 59
@@ -90,7 +90,7 @@ DECLARE_PER_CPU(struct cpuidle_device, cpuidle_dev);
90 * cpuidle_get_last_residency - retrieves the last state's residency time 90 * cpuidle_get_last_residency - retrieves the last state's residency time
91 * @dev: the target CPU 91 * @dev: the target CPU
92 * 92 *
93 * NOTE: this value is invalid if CPUIDLE_FLAG_TIME_VALID isn't set 93 * NOTE: this value is invalid if CPUIDLE_FLAG_TIME_INVALID is set
94 */ 94 */
95static inline int cpuidle_get_last_residency(struct cpuidle_device *dev) 95static inline int cpuidle_get_last_residency(struct cpuidle_device *dev)
96{ 96{
generated by cgit v1.2.2 (git 2.25.0) at 2025-08-23 21:49:34 -0400